KR101046226B1 - Burst Length Counter in Combo Memory Device - Google Patents

Abstract

A burst length counter of a combo memory device incorporating both the functions of DDR SDRAM and DDR2 / DDR3 SDRAM according to the present invention, wherein the burst length counter is configured to be the first internal of the combo memory device in response to a read or write command from the outside. Receiving a first pulse signal for enabling a column address signal and a second pulse signal for enabling a second internal column address signal to satisfy a burst length after generation of the first pulse signal, thereby receiving first and second bursts; A fuse unit for generating a count signal and determining which function is applied to the DDR SDRAM and the DDR2 / DDR3 SDRAM; and a counter order of the first and second burst counter signals differs depending on whether the fuse unit is disconnected. The number of pulses generated by the second pulse signal is adjusted.

Description

Burst length counter of combo memory device

1 is a block diagram illustrating the concept of the present invention.

FIG. 2 is an example of the burst length controller mentioned in FIG. 1.

3 is an example of the burst length counter mentioned in FIG.

4 is a waveform diagram of a signal applied to the circuits of FIGS. 2 and 3 when a burst length = 8 and a memory device is to be used as a DDR SDRAM.

FIG. 5 is a waveform diagram for explaining the case where burst length = 8 is applied to the DDR SDRAM and the case applied to the DDR2 / DDR3 SDRAM.

The present invention relates to a burst length counter of a memory device, and more particularly to a burst length counter of a combo-type memory device incorporating the functions of DDR SDRAM and DDR2 / DDR3 SDRAM simultaneously.

In general, DDR SDRAM has a 2-bit prefetch capability, while DDR2 / DDR3 SDRAM has a 4-bit prefetch capability. Therefore, when the burst length is 4, the DDR SDRAM must generate the internal column address signal twice, whereas the DDR2 / DDR3 SDRAM is sufficient to generate the internal column address signal once. Also, when the burst length is 8, DDR SDRAM with 2-bit prefetch must generate an internal column address signal four times, while DDR2 / DDR3 SDRAM with 4-bit prefetch can generate 2 internal column address signals. It is enough to generate once.

However, in connection with such a burst length operation, the conventional combo-type memory device has a built-in burst length counter for DDR SDRAM and a burst length counter for DDR2 / DDR3 SDRAM, respectively. There was a problem against this task.

The present invention has been proposed to solve the conventional problem, and the internal column according to the case where the DDR SDRAM is selected and the DDR2 / DDR3 SDRAM is selected by changing the initial value of the count bits output from the burst length counter of the combo-type memory device. A memory device capable of adjusting the number of occurrences of an address signal is provided.

A burst length counter of a combo memory device incorporating both the functions of DDR SDRAM and DDR2 / DDR3 SDRAM according to the present invention, wherein the burst length counter is configured to be the first internal of the combo memory device in response to a read or write command from the outside. Receiving a first pulse signal for enabling a column address signal and a second pulse signal for enabling a second internal column address signal to satisfy a burst length after generation of the first pulse signal, thereby receiving first and second bursts; A fuse unit for generating a count signal and determining which function is applied to the DDR SDRAM and the DDR2 / DDR3 SDRAM; and a counter order of the first and second burst counter signals differs depending on whether the fuse unit is disconnected. By adjusting the number of pulses generated by the second pulse signal.

In the present invention, when the burst length is 8 and the DDR SDRAM is selected, the second pulse signal generates three consecutive pulse signals, when the burst length is 8 and the DDR2 / DDR3 SDRAM is selected, The second pulse signal generates one pulse signal.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating the concept of the present invention.

In Fig. 1, the command decoder 101 has a chip selector signal cs, a ras signal, a ras signal, a cas signal, a write enable signal we, a clock signal clk, and a burst length. A decoding circuit for receiving the enabled burst enable signal (yburst) and the like and generating the internal signals (casp_wt, casp_rd, icasp). Here, the signal casp_wt is an internal write pulse signal generated when an external write command is applied, the signal casp_rd is an internal read pulse signal generated when an external read command is applied, and the signal icasp is used for burst length operation. The generated internal pulse signal is actually a pulse signal that is supplied to an internal circuit of the memory device to enable the write or read operation.

The burst length control unit 102 outputs the output signals casp_wt, casp_rd, and icasp of the command decoder, the burst count signals blcnt <0>, blcnt <1> and the burst length signals (output from the burst length counter 103 to be described later). A circuit for receiving bl2 and bl8 and outputting a burst enable signal yburst and signals extp and intp.

The burst length counter 103 is a circuit which receives the output signals extp and intp of the burst length control part 102 and outputs the burst count signals blcnt <0> and blcnt <1>.

FIG. 2 is an example of the burst length controller mentioned in FIG. 1.

As shown in FIG. 2, the signal extp is generated by a logical combination of the internal write pulse signal casp_wt and the internal read pulse signal casp_rd, and the internal pulse signal icasp is delayed for a predetermined time to generate the signal int. Create

In FIG. 2, the power-up signal pwrup is an initialization signal that detects when an external voltage reaches a stable level and operates an internal circuit. Also, if "bl2" is enabled, it means that it will operate with a burst length of 2; if "bl8" is enabled, it means that it will operate with a burst length of 8; if both "b12" and "bl8" are disabled, it will burst. It means it works with length 4. The burst stop enable signal bstenp is a signal for terminating the burst operation, and the signal is an interrupt signal applied to abruptly block the read or write operation during the burst length.

3 is an example of the burst length counter mentioned in FIG.

As shown in the figure, the output signals intp and extp of the burst length control unit are received to output the burst count signals blcnt <1> and blcnt <0>.

First, the case where the fuse is cut and the circuit of FIG. 3 is applied to the DDR SDRAM will be described.

When cutting the fuse, node A is at a low level. At this time, when the signal extp is input as a high pulse, the burst count signal blcnt <0>, which is an output signal of the burst length counter, maintains a high level, and the burst count signal blcnt <1> maintains a low level. do. The signal int is generated internally by the burst length operation, and the burst count signal blcnt <0> transitions to a low level by the burst length operation, and the burst count signal blcnt <1> is a high level. To transition. For example, when the burst length = 8 operation in the DDR SDRAM, the signal extp generates one pulse signal by an external command, and the signal int generates three consecutive pulses by the burst length operation. Thus, when burst length = 8, the internal column address signal is enabled four times. The burst count signals blcnt <1> and blcnt <0> in the burst length = 8 operation change in the order of 01, 10, 11, 00. Here, when the burst count signals blcnt <1> and blcnt <0> are all at a high level, a signal yburst having a function of stopping the burst length operation is disabled.

Next, a case where the circuit of FIG. 3 is applied to a DDR2 / DDR3 SDRAM while the fuse is connected as it is will be described.

When the fuse is connected, node A is at a high level. At this time, when the signal extp is first applied by the read command or the write command, the burst count signal blcnt <0> and the burst count signal blcnt <1> are both at a high level to disable the signal yburst. . Unlike DDR SDRAM, signal extp is enabled once and signal int once to enable the internal column address signal.

4 is a waveform diagram of a signal applied to the circuits of FIGS. 2 and 3 when a burst length = 8 and a memory device is to be used as a DDR SDRAM.

As can be seen in FIG. 4, after the signal extp that triggers the generation of the internal column address signal is generated once in response to the read command or the write command, the signal int is generated three times in succession to satisfy the burst length. It can be seen that. Since the signals extp and intp are associated with the generation of the internal column address signal, this means that the internal column address signal is enabled four times to read or write 8 bits of data. As shown, the burst count signals blcnt <1>, blcnt <0> change to 01, 10, 11, 00, and if 11, the signal yburst is disabled to a low level so that the internal column address signal Block the occurrence.

FIG. 5 is a waveform diagram for explaining the case where burst length = 8 is applied to the DDR SDRAM and the case applied to the DDR2 / DDR3 SDRAM.

The waveform diagram of the DDR SDRAM is substantially the same as that of FIG. 4, and in the case of the DDR2 / DDR3 SDRAM, the signal extp and the signal int are generated once each to enable the internal column address signal. Since DDR2 / DDR3 SDRAM has a 4-bit prefetch function, when the internal column address signal is enabled by the signal extp, the 4-bit data is read or written and the internal column address signal by the signal int. Reads or writes 4-bit data when is enabled, resulting in 8-bit data processing.

Summarizing once again the technical idea of the present invention, when the two-bit burst count signals blcnt <1> and blcnt <0> are all at a high level, the process terminates the burst by disabling the signal yburst. In the case of DDR SDRAM, the burst count signals (blcnt <1>, blcnt <0>) are changed to 01, 10, 11, and 00, and in the case of DDR2 / DDR3 SDRAM, the burst count signals (blcnt <1>) are set to high. In the state fixed at the level, the burst count signal blcnt <0> is changed in the order of 0, 1, and 0 to perform the burst length operation.

That is, in case of DDR SDRAM, when the burst count signals blcnt <1> and blcnt <0> are 11, the signal is recognized and disabled, and in the case of DDR2 / DDR3 SDRAM, the burst count signal blcnt (0) disables the signal yburst by recognizing that it is at a high level. For reference, as can be seen from the figure, the signal yburst is enabled at a high level after the signal extp occurs to enable the internal column address signal for the first time when the read command or the write command is applied and additionally adds the internal column address signal. The signal is generated at the time when the read or write operation corresponding to the burst length is completed.

As can be seen from the above, in the case of applying the circuit of the present invention, when DDR SDRAM is selected, it has a 2-bit prefetch function, thereby enabling 8 times of internal column address signals to strobe 8 data. In addition, when DDR2 / DDR3 SDRAM is selected, it has a 4-bit prefetch function, so it can be understood that eight data can be strobe by enabling the internal column address signal only twice.

By using one burst length counter proposed in the present invention, when the combo memory device is selected as either DDR SDRAM or DDR2 / DDR3 SDRAM, the number of generations of the internal column address signal can be efficiently controlled.

Claims (2)

In the burst length counter of a combo memory device that incorporates the functions of both DDR SDRAM and DDR2 / DDR3 SDRAM, The burst length counter may include a first pulse signal for enabling a first internal column address signal of the combo memory device in response to a read or write command from an external source, and for satisfying a burst length after generating the first pulse signal. Receives a second pulse signal to enable a second internal column address signal to generate the first and second burst count signal, and has a fuse to determine which function of the DDR SDRAM and DDR2 / DDR3 SDRAM to apply to , The burst length counter of the combo memory device, wherein the number of pulses generated by the second pulse signal is adjusted by changing a counter order of the first and second burst counter signals according to whether the fuse is cut. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, When the burst length is 8 and the DDR SDRAM is selected, the second pulse signal generates three consecutive pulse signals, And when the burst length is 8 and the DDR2 / DDR3 SDRAM is selected, the second pulse signal generates one pulse signal.

Images