KR101044388B1 - Method for manufacturing bcd device - Google Patents

Method for manufacturing bcd device Download PDF

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KR101044388B1
KR101044388B1 KR1020040057696A KR20040057696A KR101044388B1 KR 101044388 B1 KR101044388 B1 KR 101044388B1 KR 1020040057696 A KR1020040057696 A KR 1020040057696A KR 20040057696 A KR20040057696 A KR 20040057696A KR 101044388 B1 KR101044388 B1 KR 101044388B1
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film
forming
substrate
cmos
conductive pattern
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KR20060008042A (en
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손영란
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매그나칩 반도체 유한회사
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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Abstract

본 발명은 CMOS 캐패시터의 손상을 막을 수 있는 BCD 소자의 제조방법을 개시한다. 개시된 본 발명의 방법은, CMOS 영역과 DMOS 영역이 정의된 기판을 제공하는 단계; 상기 기판의 소정 부분에 소자분리막을 형성하는 단계; 상기 소자분리막을 포함한 상기 기판 상에 패드산화막 및 HLD 산화막을 차례로 형성하는 단계; 상기 HLD 산화막 및 패드산화막을 선택적으로 식각하여 DMOS 게이트 전극 형성영역 및 버스 전극 형성영역에 대응되는 기판 부분을 노출시키는 단계; 상기 식각후 잔류된 HLD 산화막을 식각 장벽으로 이용하여 상기 기판을 식각하여 제1트렌치 및 제2트렌치를 형성하는 단계; 상기 제1 및 제2트렌치 표면에 게이트 산화막을 형성하는 단계; 상기 제1 및 제2트렌치를 포함한 상기 기판 상에 제1 및 제2트렌치를 매립하도록 제1다결정실리콘막을 형성하는 단계; 상기 제1다결정실리콘막을 식각하여 상기 제1트렌치를 매립하는 DMOS 게이트 전극 및 제2트렌치를 매립하는 제1도전패턴을 형성하는 단계; 상기 DMOS 게이트 전극 및 제1도전패턴을 포함한 전면 상에 제2다결정실리콘막 및 유전체막 형성용 절연막을 차례로 형성하는 단계; 상기 유전체막 형성용 절연막과 제2다결정실리콘막을 선택적으로 식각하여 CMOS 캐패시터용 하부 전극 및 유전체막을 형성함과 동시에, 상기 제1도전패턴과 연결되는 제2도전패턴을 형성하는 단계; 상기 제2도전패턴 상에 잔류되는 유전체막 형성용 절연막을 제거하여 상기 제1 및 제2도전패턴으로 이루어지는 DMOS 버스 전극을 형성하는 단계; 상기 CMOS 액티브 영역에 잔류된 HLD 산화막 및 패드산화막 부분을 선택적으로 제거하는 단계; 및 상기 CMOS 액티브 영역의 기판 상에 CMOS 게이트 전극을 형성하고, 상기 유전체막 상에 CMOS 캐패시터용 상부 전극을 형성하는 단계를 포함한다. The present invention discloses a method of manufacturing a BCD device that can prevent damage to a CMOS capacitor. The disclosed method includes providing a substrate having a CMOS region and a DMOS region defined therein; Forming an isolation layer on a predetermined portion of the substrate; Sequentially forming a pad oxide film and an HLD oxide film on the substrate including the device isolation film; Selectively etching the HLD oxide and pad oxide layers to expose a substrate portion corresponding to a DMOS gate electrode formation region and a bus electrode formation region; Etching the substrate using the HLD oxide layer remaining after the etching as an etch barrier to form a first trench and a second trench; Forming a gate oxide layer on surfaces of the first and second trenches; Forming a first polycrystalline silicon film to fill the first and second trenches on the substrate including the first and second trenches; Etching the first polysilicon layer to form a DMOS gate electrode filling the first trench and a first conductive pattern filling the second trench; Sequentially forming an insulating film for forming a second polycrystalline silicon film and a dielectric film on the entire surface including the DMOS gate electrode and the first conductive pattern; Selectively etching the dielectric film forming insulating film and the second polycrystalline silicon film to form a lower electrode and a dielectric film for a CMOS capacitor and forming a second conductive pattern connected to the first conductive pattern; Removing a dielectric film forming insulating film remaining on the second conductive pattern to form a DMOS bus electrode formed of the first and second conductive patterns; Selectively removing portions of the HLD oxide film and the pad oxide film remaining in the CMOS active region; And forming a CMOS gate electrode on the substrate in the CMOS active region, and forming an upper electrode for the CMOS capacitor on the dielectric film.

Description

ＢＣＤ 소자의 제조방법{METHOD FOR MANUFACTURING BCD DEVICE}Manufacturing Method of VCD Device {METHOD FOR MANUFACTURING BCD DEVICE}

도 1a 내지 도 1g는 종래의 기술에 따른 BCD 소자의 제조방법을 설명하기 위한 공정별 단면도.1A to 1G are cross-sectional views for each process for explaining a method of manufacturing a BCD device according to the related art.

도 2는 종래의 기술에 따른 문제점을 설명하기 위한 단면도.2 is a cross-sectional view for explaining a problem according to the prior art.

도 3a 내지 도 3g는 본 발명의 실시예에 따른 BCD 소자의 제조방법을 설명하기 위한 공정별 단면도. 3A to 3G are cross-sectional views of processes for explaining a method of manufacturing a BCD device according to an embodiment of the present invention.

-도면의 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing

40 : 기판 41 : 소자분리막40 substrate 41 device isolation film

42 : 패드산화막 43 : HLD 산화막42: pad oxide film 43: HLD oxide film

42a, 42b : 잔류된 패드산화막42a, 42b: remaining pad oxide film

43a, 43b : 잔류된 HLD 산화막43a, 43b: remaining HLD oxide film

44 : 감광막 패턴 45a : 제1트렌치44: photosensitive film pattern 45a: first trench

45b : 제2트렌치 46 : 게이트 산화막45b: second trench 46: gate oxide film

47 : 제1다결정실리콘막 47a : 제1도전패턴47: first polysilicon film 47a: first conductive pattern

47b : 제2도전패턴 48 : 제2다결정실리콘막47b: second conductive pattern 48: second polycrystalline silicon film

49 : 유전체막 형성용 절연막 48a : 하부 전극49 dielectric film forming dielectric film 48a lower electrode

49a : 유전체막 48b : 제3도전패턴 49a: dielectric film 48b: third conductive pattern                 

50a : 게이트 전극 50b : 상부 전극50a: gate electrode 50b: upper electrode

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 최근 수요가 급증하는 자동 추진력(automotive power) IC 및 직류/직류 변환기(DC/DC converter) 등의 고주파 고내압 정보통신 시스템 구현을 위한 스마트(smart) IC 용 바이폴라-CMOS-DMOS(Bipolar-CMOS-DMOS : 이하 BCD라 함) 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to realize a high frequency high voltage information communication system such as an automatic power IC and a DC / DC converter, which have recently increased in demand. The present invention relates to a method for manufacturing a bipolar-CMOS-DMOS (Bipolar-CMOS-DMOS) device for an IC.

최근 고성능 컴퓨터 시스템의 대중화와 함께 고속 하드디스크 장치(hard disk device, 이하 HDD라 칭함) 개발이 활발하게 이루어지고 있으며, 핵심부품으로는 읽기/쓰기(read/write) 동작용 고성능 시모스(CMOS), 신호 처리용 고속 바이폴라 소자, 12볼트급에서 동작하는 구동단 전력 소자를 들 수 있다. 또한, 자동차 내장(automotive)의 각종 제어장치에서 요구되는 특성은 수십 볼트급 내전압 및 10 암페어 내외의 전류 특성이다.Recently, along with the popularization of high-performance computer systems, the development of high-speed hard disk devices (hereinafter referred to as HDDs) has been actively conducted, and the key components are high-performance CMOS (read / write) devices for read / write operations. High-speed bipolar elements for signal processing, and drive stage power elements operating at a 12 volt class. In addition, the characteristics required for various control devices of the automotive interior are the tens of volts withstand voltage and the current characteristic of about 10 amps.

이러한 고내압/고전류 특성은 자동차의 각 모터를 구동하기에 필수적이며, 이를 제어하기 위한 반도체 회로로써 원-칩(one-chip)화된 첨단 지능형 집적회로(integrated circuit, 이하 IC라 칭함) 기술이 절실히 요구된다.These high breakdown voltage / high current characteristics are essential for driving each motor of an automobile, and a state-of-the-art intelligent integrated circuit (IC) technology that is one-chip as a semiconductor circuit for controlling this is urgently needed. Required.

도 1a 내지 도 1g는 종래의 기술에 따른 BCD 소자의 제조방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다.1A to 1G are cross-sectional views illustrating processes for manufacturing a BCD device according to the related art, which will be described below.

종래의 BCD 소자의 제조방법은, 도 1a에 도시된 바와 같이, CMOS 영역(미도시)과 DMOS 영역(미도시)이 정의된 기판(10)을 제공한 다음, 상기 기판(10)의 소정 부분에 소자분리막(11)을 형성한다. 이어서, 상기 소자분리막(11)을 포함한 기판(10) 상에 패드산화막(12) 및 패드질화막(13)을 차례로 형성한다. In the conventional method of manufacturing a BCD device, as shown in FIG. An element isolation film 11 is formed on the substrate. Subsequently, the pad oxide film 12 and the pad nitride film 13 are sequentially formed on the substrate 10 including the device isolation film 11.

다음으로, 도 1b에 도시된 바와 같이, 상기 패드질화막(13) 상에 DMOS 게이트 전극 형성영역(미도시) 및 버스 전극 형성영역(미도시)에 대응되는 부분을 노출시키는 감광막 패턴(14)을 형성한 다음, 상기 감광막 패턴(14)을 식각 장벽으로 이용하여 상기 패드질화막 및 패드산화막을 식각한다. 이때, 도 1b에서 미설명된 도면부호 12a 및 13a는 각각 식각후 잔류된 패드산화막 및 식각후 잔류된 패드질화막을 나타낸 것이다. Next, as illustrated in FIG. 1B, a photoresist pattern 14 exposing portions corresponding to the DMOS gate electrode formation region (not shown) and the bus electrode formation region (not shown) is exposed on the pad nitride layer 13. After the formation, the pad nitride layer and the pad oxide layer are etched using the photoresist pattern 14 as an etching barrier. In this case, reference numerals 12a and 13a, which are not described in FIG. 1B, respectively indicate pad oxide films remaining after etching and pad nitride films remaining after etching.

그리고나서, 도 1c에 도시된 바와 같이, 상기 감광막 패턴을 제거한 후, 상기 식각후 잔류된 패드질화막(13a)을 식각 장벽으로 이용하여 상기 기판(10)을 소정 두께만큼 식각하여 DMOS 게이트 전극 형성영역의 제1트렌치(15a) 및 버스 전극 형성영역의 제2트렌치(15b)를 각각 형성한다. Then, as shown in FIG. 1C, after removing the photoresist pattern, the substrate 10 is etched by a predetermined thickness by using the pad nitride film 13a remaining after the etching as an etch barrier to form a DMOS gate electrode formation region. First trenches 15a and second trenches 15b of the bus electrode formation region are formed, respectively.

그런다음, 상기 제1 및 제2트렌치(15a, 15b) 형성을 위한 식각 공정시 발생된 식각 데미지(damage)를 회복시키기 위해 희생산화 공정을 수행하여 희생산화막(미도시)을 형성한 후, 다시 상기 희생산화막을 제거하고 나서, 상기 제1 및 제2트렌치(15a, 15b) 표면에 게이트 산화막(16)을 형성한다. Then, a sacrificial oxidation process is performed to recover the etch damage generated during the etching process for forming the first and second trenches 15a and 15b to form a sacrificial oxide film (not shown), and then again. After the sacrificial oxide film is removed, the gate oxide film 16 is formed on the first and second trenches 15a and 15b.

이어서, 도 1d에 도시된 바와 같이, 상기 제1 및 제2트렌치(15a,15b)를 포함한 기판(10) 상에 제1 및 제2트렌치(15a, 15b)를 매립하도록 제1다결정실리콘막(17)을 형성한다. Subsequently, as illustrated in FIG. 1D, the first polysilicon film (eg, the first and second trenches 15a and 15b) is embedded in the substrate 10 including the first and second trenches 15a and 15b. 17).

그런다음, 도 1e에 도시된 바와 같이, 상기 제1다결정실리콘막을 식각하여 상기 제1 및 제2트렌치(15a, 15b)를 각각 매립하는 제1도전패턴(17a) 및 제2도전패턴(17b)을 형성한다. 여기서, 상기 제1도전패턴(17a)은 DMOS 게이트 전극으로 이용된다. Then, as shown in FIG. 1E, the first conductive pattern 17a and the second conductive pattern 17b which etch the first polycrystalline silicon film to fill the first and second trenches 15a and 15b, respectively. To form. Here, the first conductive pattern 17a is used as the DMOS gate electrode.

계속해서, 도 1f에 도시된 바와 같이, 상기 제1 및 제2도전패턴(17a,17b)을 포함한 전면 상에 제2다결정실리콘막(18) 및 ONO막(산화막/질화막/산화막) 구조의 유전체막 형성용 절연막(19)을 차례로 형성한다. Subsequently, as shown in FIG. 1F, a dielectric of a second polycrystalline silicon film 18 and an ONO film (oxide film / nitride film / oxide film) structure is formed on the entire surface including the first and second conductive patterns 17a and 17b. The film formation insulating film 19 is formed in order.

그런후에, 도 1g에 도시된 바와 같이, 상기 ONO 구조의 유전체막 형성용 절연막과 제2다결정실리콘막을 선택적으로 식각하여 CMOS 캐패시터용 하부(bottom) 전극(18a) 및 유전체막(19a)을 형성함과 동시에, 상기 제2도전패턴(17b)과 연결되는 제3도전패턴(18b)을 형성한다. 그런다음, 상기 제3도전패턴(18b) 상에 잔류되는 유전체막 형성용 절연막을 제거하여, 상기 제2 및 제3도전패턴(17b, 18b)으로 이루어지는 DMOS 버스 전극을 형성한다. Thereafter, as shown in FIG. 1G, the insulating film for forming the dielectric film and the second polysilicon film of the ONO structure are selectively etched to form the bottom electrode 18a and the dielectric film 19a for the CMOS capacitor. At the same time, a third conductive pattern 18b connected to the second conductive pattern 17b is formed. Thereafter, an insulating film for forming a dielectric film remaining on the third conductive pattern 18b is removed to form a DMOS bus electrode including the second and third conductive patterns 17b and 18b.

이어서, CMOS 액티브영역(미도시)에 잔류된 패드질화막 및 패드산화막 부분을 선택적으로 제거한다. 이때, 상기 패드질화막(13)의 제거 공정은 H3PO4 용액을 이용하여 수행한다. 이때, 도 1g에서 미설명된 도면부호 12b 및 13b는 각각 잔류된 패드산화막 및 질화막을 나타낸 것이다. Subsequently, portions of the pad nitride film and the pad oxide film remaining in the CMOS active region (not shown) are selectively removed. At this time, the removal process of the pad nitride film 13 is performed using a H 3 PO 4 solution. In this case, reference numerals 12b and 13b, which are not described in FIG. 1g, indicate the remaining pad oxide and nitride films, respectively.

이후, 상기 CMOS 액티브영역의 기판(10) 상에 CMOS 게이트 전극(20a)을 형성하고, 상기 유전체막(19a) 상에 CMOS 캐패시터용 상부(top) 전극(20b)을 형성한다. Thereafter, a CMOS gate electrode 20a is formed on the substrate 10 of the CMOS active region, and a top electrode 20b for a CMOS capacitor is formed on the dielectric film 19a.

그러나, 전술한 바와 같은 종래의 BCD 소자의 제조방법에서는 다음과 같은 문제점이 발생된다. However, the following problem occurs in the conventional manufacturing method of the BCD device as described above.

도 2는 종래의 기술에 따른 문제점을 설명하기 위한 단면도이다. 2 is a cross-sectional view illustrating a problem according to the prior art.

종래의 기술에서는, 도 2에 도시된 바와 같이, 기판의 CMOS 액티브영역에 잔류된 패드질화막 부분을 H3PO4 용액으로 선택적으로 제거할 때에, 상기 CMOS 캐패시터용 유전체막(19a)을 이루고 있는 ONO막의 질화막 측벽부분(A)이 함께 제거되어 CMOS 캐패시터가 손상을 입게되고, 나아가, BCD 소자의 특성이 저하되는 문제점이 발생된다. In the prior art, as shown in FIG. 2, when selectively removing the pad nitride film portion remaining in the CMOS active region of the substrate with the H 3 PO 4 solution, the ONO forming the dielectric film 19a for the CMOS capacitor is formed. The nitride film sidewall portion A of the film is removed together, thereby damaging the CMOS capacitor, and furthermore, a problem occurs that the characteristics of the BCD element are deteriorated.

이에, 상기 ONO막의 질화막이 함께 제거되는 것을 방지하기 위하여, 상기 패드질화막의 제거 공정을 상기 ONO막 형성 이전, 즉, 제1 및 제2트렌치(15a, 15b)를 형성한 다음에 실시하게 되면, 제1다결정실리콘막 및 제2다결정실리콘막의 식각 공정 시에 제1 및 제2트렌치(15a, 15b) 탑 코너 부분의 게이트 산화막(16)과 실리콘 기판(10)의 표면이 손상되는 문제점이 발생된다. Accordingly, in order to prevent the nitride film of the ONO film from being removed together, when the removal process of the pad nitride film is performed before forming the ONO film, that is, after forming the first and second trenches 15a and 15b, In the etching process of the first polysilicon film and the second polysilicon film, the gate oxide film 16 and the surface of the silicon substrate 10 at the top corners of the first and second trenches 15a and 15b are damaged. .

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, CMOS 캐패시터용 유전체막을 이루고 있는 ONO막의 질화막 측벽부분이 제거되는 것을 방지함으로써, CMOS 캐패시터의 손상을 막을 수 있으며, 나아가, BCD 소자의 특성을 향상시킬 수 있는 BCD 소자의 제조방법을 제공함에 그 목적이 있다. Accordingly, the present invention has been made to solve the above problems, and by preventing the sidewall portion of the nitride film of the ONO film forming the dielectric film for CMOS capacitors from being removed, damage to the CMOS capacitor can be prevented, and furthermore, It is an object of the present invention to provide a method for manufacturing a BCD device capable of improving characteristics.

상기와 같은 목적을 달성하기 위한 본 발명의 BCD 소자의 제조방법은, CMOS 영역과 DMOS 영역이 정의된 기판을 제공하는 단계; 상기 기판의 소정 부분에 소자분리막을 형성하는 단계; 상기 소자분리막을 포함한 기판 상에 패드산화막 및 HLD 산화막을 차례로 형성하는 단계; 상기 HLD 산화막 및 패드산화막을 선택적으로 식각하여 DMOS 게이트 전극 형성영역 및 버스 전극 형성영역에 대응되는 기판 부분을 노출시키는 단계; 상기 식각후 잔류된 HLD 산화막을 식각 장벽으로 이용하여 상기 기판을 식각하여 제1트렌치 및 제2트렌치를 각각 형성하는 단계; 상기 제1 및 제2트렌치 표면에 게이트 산화막을 형성하는 단계; 상기 제1 및 제2트렌치를 포함한 상기 기판 상에 제1 및 제2트렌치를 매립하도록 제1다결정실리콘막을 형성하는 단계; 상기 제1다결정실리콘막을 식각하여 상기 제1트렌치를 매립하는 DMOS 게이트 전극 및 제2트렌치를 매립하는 제1도전패턴을 각각 형성하는 단계; 상기 DMOS 게이트 전극 및 제1도전패턴을 포함한 전면 상에 제2다결정실리콘막 및 유전체막 형성용 절연막을 차례로 형성하는 단계; 상기 유전체막 형성용 절연막과 제2다결정실리콘막을 선택적으로 식각하여 CMOS 캐패시터용 하부 전극 및 유전체막을 형성함과 동시에, 상기 제1도전패턴과 연결되는 제2도전패턴을 형성하는 단계; 상기 제2도전패턴 상에 잔류되는 유전체막 형성용 절연막을 제거하여 상기 제1 및 제2도전패턴으로 이루어지는 DMOS 버스 전극을 형성하는 단계; 상기 CMOS 액티브영역에 잔류된 HLD 산화막 및 패드산화막 부분을 선택적으로 제거하는 단계; 및 상기 CMOS 액티브영역의 기판 상에 CMOS 게이트 전극을 형성하고, 상기 유전체막 상에 CMOS 캐패시터용 상부 전극을 형성하는 단계를 포함한다. A method of manufacturing a BCD device of the present invention for achieving the above object comprises the steps of: providing a substrate in which a CMOS region and a DMOS region are defined; Forming an isolation layer on a predetermined portion of the substrate; Sequentially forming a pad oxide film and an HLD oxide film on a substrate including the device isolation film; Selectively etching the HLD oxide and pad oxide layers to expose a substrate portion corresponding to a DMOS gate electrode formation region and a bus electrode formation region; Etching the substrate by using the HLD oxide layer remaining after the etching as an etch barrier to form a first trench and a second trench, respectively; Forming a gate oxide layer on surfaces of the first and second trenches; Forming a first polycrystalline silicon film to fill the first and second trenches on the substrate including the first and second trenches; Etching the first polysilicon layer to form a DMOS gate electrode filling the first trench and a first conductive pattern filling the second trench; Sequentially forming an insulating film for forming a second polycrystalline silicon film and a dielectric film on the entire surface including the DMOS gate electrode and the first conductive pattern; Selectively etching the dielectric film forming insulating film and the second polycrystalline silicon film to form a lower electrode and a dielectric film for a CMOS capacitor and forming a second conductive pattern connected to the first conductive pattern; Removing a dielectric film forming insulating film remaining on the second conductive pattern to form a DMOS bus electrode formed of the first and second conductive patterns; Selectively removing portions of the HLD oxide film and the pad oxide film remaining in the CMOS active region; And forming a CMOS gate electrode on the substrate in the CMOS active region, and forming an upper electrode for the CMOS capacitor on the dielectric layer.

여기서, 상기 HLD 산화막은 3000~5000Å의 두께로 형성하고, 상기 제1 및 제 2트렌치는 1.1~1.9㎛의 깊이를 갖도록 형성한다. Here, the HLD oxide film is formed to a thickness of 3000 ~ 5000Å, the first and second trenches are formed to have a depth of 1.1 ~ 1.9㎛.

그리고, 상기 게이트 산화막은 300Å의 두께로 형성하며, 상기 제1다결정실리콘막은 5000Å의 두께로 형성한다. The gate oxide film is formed to a thickness of 300 GPa and the first polycrystalline silicon film is formed to a thickness of 5000 GPa.

또한, 상기 제1다결정실리콘막의 식각 공정은, 상기 DMOS 게이트 전극 및 제1도전패턴의 상부가 상기 기판 표면 보다 1000~1200Å 정도 높은 지점에 위치될 때까지 진행한다. In addition, the etching process of the first polysilicon film is performed until the upper portion of the DMOS gate electrode and the first conductive pattern is positioned at about 1000 to 1200 Å above the surface of the substrate.

(실시예)(Example)

이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3g는 본 발명의 실시예에 따른 BCD 소자의 제조방법을 설명하기 위한 공정별 단면도이다. 3A to 3G are cross-sectional views of processes for describing a method of manufacturing a BCD device according to an embodiment of the present invention.

본 발명의 실시예에 따른 BCD 소자의 제조방법은, 도 3a에 도시된 바와 같이, CMOS 영역(미도시)과 DMOS 영역(미도시)이 정의된 기판(40)을 제공한 다음, 상기 기판(40)의 소정 부분에 소자분리막(41)을 형성한다. 여기서, 상기 소자분리막(41)은 6000~7000Å의 두께로 형성한다. 이어서, 상기 소자분리막(41)을 포함한 기판(40) 상에 패드산화막(42) 및 HLD(high temperature low pressure deposition) 산화막(43)을 차례로 형성한다. 이때, 상기 패드산화막(42)은 100Å의 두께로 형성하고, 상기 HLD 산화막(43)은 3000~5000Å의 두께로 형성한다. In the method of manufacturing a BCD device according to an embodiment of the present invention, as shown in FIG. An element isolation film 41 is formed in a predetermined portion of the 40. Here, the device isolation layer 41 is formed to a thickness of 6000 ~ 7000Å. Subsequently, a pad oxide film 42 and a high temperature low pressure deposition (HLD) oxide film 43 are sequentially formed on the substrate 40 including the device isolation film 41. In this case, the pad oxide film 42 is formed to a thickness of 100 Å, the HLD oxide film 43 is formed to a thickness of 3000 ~ 5000 Å.

다음으로, 도 3b에 도시된 바와 같이, 상기 HLD 산화막(43) 상에 DMOS 게이트 전극 형성영역(미도시) 및 버스 전극 형성영역(미도시)에 대응되는 부분을 노출 시키는 감광막 패턴(44)을 형성한 다음, 상기 감광막 패턴(44)을 식각 장벽으로 이용하여 상기 HLD 산화막 및 패드산화막을 식각한다. 이때, 도 3b에서 미설명된 도면부호 42a 및 43a는 각각 식각후 잔류된 패드산화막 및 HLD 산화막을 나타낸 것이다. Next, as shown in FIG. 3B, a photoresist pattern 44 exposing portions corresponding to the DMOS gate electrode formation region (not shown) and the bus electrode formation region (not shown) is exposed on the HLD oxide layer 43. After the formation, the HLD oxide layer and the pad oxide layer are etched using the photoresist pattern 44 as an etching barrier. In this case, reference numerals 42a and 43a, which are not described with reference to FIG. 3B, show pad oxide films and HLD oxide films remaining after etching, respectively.

그리고나서, 도 3c에 도시된 바와 같이, 상기 감광막 패턴을 제거한 후, 상기 식각후 잔류된 HLD 산화막(43a)을 식각 장벽으로 이용하여 상기 기판(40)을 소정 두께만큼 식각하여 DMOS 게이트 전극 형성영역 및 버스 전극 형성영역에 각각 제1 및 제2트렌치(45a,45b)를 형성한다. 여기서, 상기 제1 및 제2트렌치(45a, 45b)는 1.1~1.9㎛의 깊이(depth)를 갖도록 형성한다. 3C, after the photoresist pattern is removed, the substrate 40 is etched by a predetermined thickness using the HLD oxide layer 43a remaining after the etching as an etch barrier, thereby forming a DMOS gate electrode forming region. And first and second trenches 45a and 45b in the bus electrode formation region, respectively. Here, the first and second trenches 45a and 45b are formed to have a depth of 1.1 to 1.9 탆.

그런다음, 상기 제1 및 제2트렌치(45a, 45b) 형성을 위한 식각 공정시 발생된 식각 데미지(damage)를 회복시키기 위해 희생산화 공정을 수행하여 희생산화막(미도시)을 형성한 후, 다시 상기 희생산화막을 제거하고 나서, 상기 제1 및 제2트렌치(45a, 45b) 표면에 게이트 산화막(46)을 형성한다. 이때, 상기 게이트 산화막(46)은 300Å의 두께로 형성한다. Then, a sacrificial oxide process (not shown) is formed by performing a sacrificial oxidation process to recover the etch damage generated during the etching process for forming the first and second trenches 45a and 45b. After removing the sacrificial oxide layer, a gate oxide layer 46 is formed on the first and second trenches 45a and 45b. At this time, the gate oxide layer 46 is formed to a thickness of 300 Å.

이어서, 도 3d에 도시된 바와 같이, 상기 제1 및 제2트렌칭(45a,45b)를포함한 기판(40) 상에 제1 및 제2트렌치(45a, 45b)를 매립하도록 제1다결정실리콘막(47)을 형성한다. 여기서, 상기 제1다결정실리콘막(47)은 5000Å의 두께로 형성한다. Subsequently, as shown in FIG. 3D, the first polysilicon film is embedded to fill the first and second trenches 45a and 45b on the substrate 40 including the first and second trenches 45a and 45b. Form 47. Here, the first polysilicon film 47 is formed to a thickness of 5000 kPa.

그런다음, 도 3e에 도시된 바와 같이, 상기 제1다결정실리콘막을 식각하여 상기 제1트렌치(45a)를 매립하는 제1도전패턴(47a) 및 상기 제2트렌치(45b)를 매립하는 제2도전패턴(47b)을 형성한다. 여기서, 상기 제1도전패턴(47a)은 DMOS 게이트 전극으로 이용된다. 한편, 상기 제1다결정실리콘막의 식각 공정은, 상기 제1 및 제2트렌치(45a, 45b) 탑 코너 부분의 게이트 산화막(46)을 보호하기 위하여, 상기 제1 및 제2도전패턴(47a, 47b)의 상부가 상기 기판(40) 표면 보다 1000~1200Å 정도 높은 지점에 위치될 때까지 진행한다. Then, as illustrated in FIG. 3E, the first conductive pattern 47a filling the first trench 45a and the second conductive filling the second trench 45b are etched by etching the first polycrystalline silicon film. The pattern 47b is formed. Here, the first conductive pattern 47a is used as the DMOS gate electrode. In the etching process of the first polysilicon layer, the first and second conductive patterns 47a and 47b may be used to protect the gate oxide layer 46 at the top corners of the first and second trenches 45a and 45b. ) Until the top of the substrate is positioned at a point 1000 to 1200 mm higher than the surface of the substrate 40.

계속해서, 도 3f에 도시된 바와 같이, 상기 제1 및 제2도전패턴(47a,47b)을 포함한 전면 상에 제2다결정실리콘막(48) 및 ONO막(산화막/질화막/산화막) 구조의 유전체막 형성용 절연막(49)을 차례로 형성한다. Subsequently, as shown in FIG. 3F, a dielectric of a second polycrystalline silicon film 48 and an ONO film (oxide film / nitride film / oxide film) structure is formed on the entire surface including the first and second conductive patterns 47a and 47b. The film formation insulating film 49 is formed in order.

그런후에, 도 3g에 도시된 바와 같이, 상기 ONO 구조의 유전체막 형성용 절연막과 제2다결정실리콘막을 선택적으로 식각하여 CMOS 캐패시터용 하부(bottom) 전극(48a) 및 유전체막(49a)을 형성함과 동시에, 상기 제2도전패턴(47b)과 연결되는 제3도전패턴(48b)을 형성한다. 그런다음, 상기 제3도전패턴(48b) 상에 잔류되는 유전체막 형성용 절연막을 제거하여, 상기 제2 및 제3도전패턴(47b, 48b)으로 이루어지는 DMOS 버스 전극을 형성한다. Thereafter, as shown in FIG. 3G, the insulating film for forming a dielectric film and the second polysilicon film of the ONO structure are selectively etched to form a bottom electrode 48a and a dielectric film 49a for a CMOS capacitor. At the same time, a third conductive pattern 48b connected to the second conductive pattern 47b is formed. Thereafter, an insulating film for forming a dielectric film remaining on the third conductive pattern 48b is removed to form a DMOS bus electrode including the second and third conductive patterns 47b and 48b.

이어서, 상기 CMOS 액티브영역(미도시)에 잔류된 HLD 산화막 및 패드산화막 부분을 선택적으로 제거한다. 이때, 도 3g에서 미설명된 도면부호 42b 및 43b는 각각 잔류된 패드산화막 및 HLD 산화막을 나타낸 것이다. 여기서, 상기 HLD 산화막의 제거 공정 시에는 기존과 달리 H3PO4 용액을 이용하지 않아도 되므로, 상기 ONO 구조의 유전체막(49a)을 이루고 있는 질화막의 측벽이 손실될 염려가 없다. Subsequently, portions of the HLD oxide film and the pad oxide film remaining in the CMOS active region (not shown) are selectively removed. In this case, reference numerals 42b and 43b, which are not described in FIG. 3G, indicate the remaining pad oxide film and the HLD oxide film, respectively. Here, the removal process of the oxide film, the HLD so unlike the conventional H 3 PO 4 without using a solution, there is no fear of the nitride film which forms a dielectric film (49a) of the ONO structure sidewall loss.

이후, 상기 CMOS 액티브영역의 기판(40) 상에 CMOS 게이트 전극(50a)을 형성하고, 상기 유전체막(49a) 상에 CMOS 캐패시터용 상부(top) 전극(50b)을 형성하여 BCD 소자를 완성한다. Thereafter, a CMOS gate electrode 50a is formed on the substrate 40 in the CMOS active region, and a top electrode 50b for a CMOS capacitor is formed on the dielectric film 49a to complete a BCD device. .

이상에서와 같이, 본 발명은 DMOS 게이트 전극 형성영역의 제1트렌치 및 버스 전극 형성영역의 제2트렌치 형성을 위한 기판의 식각 공정에 있어서, 식각 장벽으로서 HLD 산화막을 사용함으로써, 이후의 공정에서 CMOS 액티브영역 기판 상의 HLD 산화막을 선택적으로 제거할 때에, 기존과 달리 H3PO4 용액을 이용하지 않아도 되므로, 상기 CMOS 캐패시터용 유전체막을 이루고 있는 ONO막의 질화막 측벽부분이 함께 제거되는 것을 방지할 수 있다. As described above, in the etching process of the substrate for forming the first trench of the DMOS gate electrode forming region and the second trench of the bus electrode forming region, the present invention uses a HLD oxide film as an etching barrier, thereby providing CMOS in a subsequent process. When selectively removing the HLD oxide film on the active region substrate, it is not necessary to use the H 3 PO 4 solution unlike the conventional one, and thus the sidewall portion of the nitride film of the ONO film forming the dielectric film for the CMOS capacitor can be prevented from being removed together.

따라서, 본 발명은 CMOS 캐패시터의 손상을 막을 수 있으며, 나아가, BCD 소자의 특성을 향상시킬 수 있다. Therefore, the present invention can prevent the damage of the CMOS capacitor, and can further improve the characteristics of the BCD element.

Claims (6)

CMOS 영역과 DMOS 영역이 정의된 기판을 제공하는 단계;Providing a substrate in which a CMOS region and a DMOS region are defined; 상기 기판의 소정 부분에 소자분리막을 형성하는 단계;Forming an isolation layer on a predetermined portion of the substrate; 상기 소자분리막을 포함한 상기 기판 상에 패드산화막 및 HLD 산화막을 차례로 형성하는 단계;Sequentially forming a pad oxide film and an HLD oxide film on the substrate including the device isolation film; 상기 HLD 산화막 및 패드산화막을 선택적으로 식각하여 DMOS 게이트 전극 형성영역 및 버스 전극 형성영역에 대응되는 기판 부분을 노출시키는 단계;Selectively etching the HLD oxide and pad oxide layers to expose a substrate portion corresponding to a DMOS gate electrode formation region and a bus electrode formation region; 상기 식각후 잔류된 HLD 산화막을 식각 장벽으로 이용하여 상기 기판을 식각하여 제1트렌치 및 제2트렌치를 각각 형성하는 단계;Etching the substrate by using the HLD oxide layer remaining after the etching as an etch barrier to form a first trench and a second trench, respectively; 상기 제1 및 제2트렌치 표면에 게이트 산화막을 형성하는 단계;Forming a gate oxide layer on surfaces of the first and second trenches; 상기 제1 및 제2트렌치를 포함한 전면 상에 제1 및 제2트렌치를 매립하도록 제1다결정실리콘막을 형성하는 단계;Forming a first polycrystalline silicon film to fill the first and second trenches on the entire surface including the first and second trenches; 상기 제1다결정실리콘막을 식각하여 상기 제1트렌치를 매립하는 DMOS 게이트 전극 및 제2트렌치를 매립하는 제1도전패턴을 각각 형성하는 단계;Etching the first polysilicon layer to form a DMOS gate electrode filling the first trench and a first conductive pattern filling the second trench; 상기 DMOS 게이트 전극 및 제1도전패턴을 포함한 전면 상에 제2다결정실리콘막 및 유전체막 형성용 절연막을 차례로 형성하는 단계;Sequentially forming an insulating film for forming a second polycrystalline silicon film and a dielectric film on the entire surface including the DMOS gate electrode and the first conductive pattern; 상기 유전체막 형성용 절연막과 제2다결정실리콘막을 선택적으로 식각하여 CMOS 캐패시터용 하부 전극 및 유전체막을 형성함과 동시에, 상기 제1도전패턴과 연결되는 제2도전패턴을 형성하는 단계;Selectively etching the dielectric film forming insulating film and the second polycrystalline silicon film to form a lower electrode and a dielectric film for a CMOS capacitor and forming a second conductive pattern connected to the first conductive pattern; 상기 제2도전패턴 상에 잔류되는 유전체막 형성용 절연막을 제거하여 상기 제1 및 제2도전패턴으로 이루어지는 DMOS 버스 전극을 형성하는 단계;Removing a dielectric film forming insulating film remaining on the second conductive pattern to form a DMOS bus electrode formed of the first and second conductive patterns; 상기 CMOS 액티브영역에 잔류된 HLD 산화막 및 패드산화막 부분을 선택적으로 제거하는 단계; 및 Selectively removing portions of the HLD oxide film and the pad oxide film remaining in the CMOS active region; And 상기 CMOS 액티브영역의 상기 기판 상에 CMOS 게이트 전극을 형성하고, 상기 유전체막 상에 CMOS 캐패시터용 상부 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 BCD 소자의 제조방법.And forming a CMOS gate electrode on the substrate in the CMOS active region, and forming an upper electrode for a CMOS capacitor on the dielectric layer. 제 1 항에 있어서, 상기 HLD 산화막은 3000~5000Å의 두께로 형성하는 것을 특징으로 하는 BCD 소자의 제조방법.The method of claim 1, wherein the HLD oxide film is formed to a thickness of 3000 ~ 5000Å. 제 1 항에 있어서, 상기 제1 및 제2트렌치는 1.1~1.9㎛의 깊이를 갖도록 형성하는 것을 특징으로 하는 BCD 소자의 제조방법.The method of claim 1, wherein the first and second trenches are formed to have a depth of about 1.1 μm to about 1.9 μm. 제 1 항에 있어서, 상기 게이트 산화막은 300Å의 두께로 형성하는 것을 특징으로 하는 BCD 소자의 제조방법.The method of manufacturing a BCD device according to claim 1, wherein the gate oxide film is formed to a thickness of 300 GPa. 제 1 항에 있어서, 상기 제1다결정실리콘막은 5000Å의 두께로 형성하는 것을 특징으로 하는 BCD 소자의 제조방법.The method of claim 1, wherein the first polysilicon film is formed to a thickness of 5000 kPa. 제 1 항에 있어서, 상기 제1다결정실리콘막의 식각 공정은, 상기 DMOS 게이 트 전극 및 제1도전패턴의 상부가 상기 기판 표면 보다 1000~1200Å 정도 높은 지점에 위치될 때까지 진행하는 것을 특징으로 하는 BCD 소자의 제조방법.The method of claim 1, wherein the etching process of the first polysilicon layer is performed until the upper portions of the DMOS gate electrode and the first conductive pattern are positioned at about 1000 to 1200 ~ above the surface of the substrate. Method for manufacturing a BCD device.
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JPH09237841A (en) * 1996-02-29 1997-09-09 Toshiba Corp Semiconductor device and its manufacture
KR20020021817A (en) * 2000-08-31 2002-03-23 박종섭 Method for fabricating mosfet
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JPH09237841A (en) * 1996-02-29 1997-09-09 Toshiba Corp Semiconductor device and its manufacture
KR20020021817A (en) * 2000-08-31 2002-03-23 박종섭 Method for fabricating mosfet
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