KR101043680B1 - Thin Film Transistor Substrate And Fabricating Method Thereof - Google Patents

Abstract

The present invention relates to a thin film transistor substrate and a method of manufacturing the same, which can improve reliability by reducing the number of mask processes and preventing the pad from being transferred.

A thin film transistor substrate according to the present invention includes a thin film transistor connected to a pixel electrode; A signal line group which supplies a signal to the thin film transistor and is formed in a group unit; At least one insulating film formed to cover the signal line group; And a slit formed through the insulating film between the adjacent signal line groups to allow penetration of a stripper for removing the photoresist pattern formed on the at least one insulating film, and facing the signal with the slit interposed therebetween. The separation distance of the line group may be wider than the separation distance of the signal lines included in the signal line group.

Description

Thin Film Transistor Substrate and Fabrication Method {Thin Film Transistor Substrate And Fabricating Method Thereof}             

1 is a perspective view illustrating a conventional liquid crystal display panel.

2A and 2B are sectional views showing a pixel region and a link region of a thin film transistor substrate of the source invention.

3A through 3D are cross-sectional views for describing a third mask process of the thin film transistor substrate illustrated in FIGS. 2A and 2B in detail.

4 is a plan view illustrating a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the thin film transistor substrate cut along the lines "I-I '" and II-II' "of FIG. 4.

6 is a cross-sectional view showing another form of the slit shown in FIG. 5.

7 is a plan view illustrating a thin film transistor substrate according to a second exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating the thin film transistor substrate taken along the line "III-III '" in FIG. 7.                 

9A to 9F are cross-sectional views for describing a third mask process of the thin film transistor substrate illustrated in FIG. 8 in detail.

<Description of Symbols for Main Parts of Drawings>

1,11,142,220: substrate 2: gate line

4: data line 12: color filter

14 common electrode 16 liquid crystal

18: black matrix 22: pixel electrode

30: thin film transistor 50: gate pad

60: data pad 108: gate electrode

110: source electrode 112: drain electrode

114: active layer 144,222: gate insulating film

146: ohmic contact layer 150,224: protective film

170200: Gate link 172: dummy transparent conductive pattern

174,206: Slit 212: Gate pad lower electrode

214: gate pad upper electrode 216: contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method for manufacturing the same, and more particularly, to a thin film transistor substrate and a method for manufacturing the same, which can improve reliability by reducing the number of mask processes and preventing pad transfer.

In general, a liquid crystal display (LCD) displays an image by allowing each of the liquid crystal cells arranged in a matrix form on a liquid crystal panel to adjust light transmittance according to a video signal.

 As shown in FIG. 1, the liquid crystal display includes a thin film transistor substrate 70 and a color filter substrate 80 which are bonded to each other with the liquid crystal 16 interposed therebetween.

The color filter substrate 80 includes a color filter array including a black matrix 18 for preventing light leakage, a color filter 12 for implementing color, and a common electrode 14 forming a vertical electric field with the pixel electrode 22. It is formed on the upper substrate 11.

The thin film transistor substrate 70 has a gate line 2 and a data line 4 formed to cross each other, a thin film transistor 30 formed at an intersection of the two and four, and a thin film transistor 30 connected to the thin film transistor 30. A thin film transistor array including a pixel electrode 22, a gate pad 50 extending from the gate line 2, and a data pad 60 extending from the data line 4 is formed on the lower substrate 1. do.

In the liquid crystal display device, the thin film transistor substrate 70 includes a semiconductor process and requires a plurality of mask processes, and thus, the manufacturing process is complicated, which is an important cause of an increase in the manufacturing cost of the liquid crystal panel. In order to solve this problem, the thin film transistor substrate 70 is developing in a direction of reducing the number of mask processes. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, an inspection process, and the like. Accordingly, in recent years, a method for reducing the manufacturing cost by simplifying the manufacturing process of the thin film transistor substrate 70 is required.

Accordingly, an object of the present invention relates to a thin film transistor substrate and a method for manufacturing the same, which can reduce the number of mask processes.

In addition, another object of the present invention relates to a thin film transistor substrate and a method of manufacturing the same that can improve the reliability by preventing the pad transfer.

In order to achieve the above object, a thin film transistor substrate according to the present invention includes a thin film transistor connected to the pixel electrode; A signal line group which supplies a signal to the thin film transistor and is formed in a group unit; At least one insulating film formed to cover the signal line group; And a slit formed through the insulating film between the adjacent signal line groups to allow penetration of a stripper for removing the photoresist pattern formed on the at least one insulating film, and facing the signal with the slit interposed therebetween. The separation distance of the line group is characterized in that it is wider than the separation distance of the signal lines included in the signal line group.

In order to achieve the above object, a method of manufacturing a thin film transistor substrate according to the present invention comprises the steps of forming a signal line for supplying a signal to the thin film transistor together with the thin film transistor in groups; Forming at least one insulating film to cover the signal line group; Forming a slit penetrating the insulating film between the adjacent signal line groups using the photoresist pattern formed on the insulating film; Forming a transparent conductive film on the insulating film having the photoresist pattern; And removing the photoresist pattern covered with the transparent conductive film by the stripper penetrating through the slit to form a pixel electrode, wherein the separation distance of the signal line group facing each other with the slit interposed therebetween. Characterized in that it is wider than the separation distance of the included signal lines.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

First, the applicant of the present invention in the domestic patent application No. 2003-74138 (hereinafter referred to as a source invention) in order to improve the efficiency of the lift-off process used in the method for manufacturing a thin film transistor substrate using a three mask as shown in Figure 2a to 3c As shown, a method of forming a stripper penetration path on and between the wirings has been proposed.

2A and 2B illustrate cross-sectional structures of one pixel area of a display area and a gate link area of a non-display area of a thin film transistor substrate.

The thin film transistor substrate shown in FIG. 2A includes a thin film transistor 106 and a pixel electrode 118 formed in a pixel region defined by the intersection of the gate line 102 and the data line 104.

The thin film transistor 106 may include a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, and a pixel electrode 118 facing the source electrode 110. The active layer 114 and the source electrode 110 overlapping the gate electrode 108 with the drain electrode 112 and the gate insulating layer 144 therebetween and forming a channel between the source electrode 110 and the drain electrode 112. And an ohmic contact layer 146 formed between the drain electrode 112 and the active layer 114.

The pixel electrode 118 is formed in the pixel hole 160 that penetrates the passivation layer 150 and the gate insulating layer 144 in the pixel region, and is laterally connected to the drain electrode 112 exposed through the pixel hole 160. .

The gate link 170 illustrated in FIG. 2B electrically connects the gate pad and the gate line formed in the display area. The gate link 170 has a bent shape.

In addition, slits 172 that are used as stripper penetration paths are formed between the gate pads and between the gate links 170. The slit 172 is formed through the passivation layer 150 and the gate insulating layer 144, and the dummy transparent conductive pattern 174 remains during the lift-off process.

The thin film transistor substrate is formed by a three mask process. The three mask process will be described in detail as follows.                     

In the first mask process, a gate pattern including a gate line, a gate electrode 108, a gate link 170, and the like is formed on the substrate 142. The gate insulating layer 144 covering the gate pattern, the active layer 114 and the ohmic contact layer 146, the data line 104, the source electrode 110, the drain electrode 112, and the like are covered by the second mask process. Source / drain patterns are formed.

A protective film 150 covering the source / drain pattern is formed as shown in FIG. 3A, and the protective film 150 and the gate insulating film 144 are patterned on the protective film 150 by a photolithography process using a third mask. The photoresist pattern 152 is formed.

Subsequently, the pixel hole 160 and the slits 172 penetrating the passivation layer 150 and the gate insulating layer 144 are formed in the etching process using the photoresist pattern 152 as a mask, as shown in FIG. 3B.

Next, as illustrated in FIG. 3C, a transparent conductive film 154 covering the photoresist pattern 152 is formed on the entire surface, and a lift-off process of removing the photoresist pattern 152 is performed. The pixel electrode 118 and the dummy transparent conductive pattern 174 are formed. In this case, the pixel hole 160 and the slits 172 formed in the region where the photoresist pattern 152 is removed are used as the stripper penetration path A, and thus the photoresist pattern 152 and the passivation layer 150 may be formed. As many strippers penetrate into the boundary portion, the photoresist pattern 152 covered with the transparent conductive film 154 may be easily separated from the protective film 150. When the edge of the photoresist pattern 152 is formed to protrude more than the edge of the passivation layer 150 due to overetching of the passivation layer 150, the transparent conductive layer 154 is formed at the edge of the photoresist pattern 152. Is open so that the stripper can easily penetrate.

As described above, in the source invention, a plurality of slits 172, ie, stripper penetration paths, in which the photoresist pattern 152 is removed, are formed in the non-display area of the thin film transistor substrate, thereby improving lift-off capability.

In order to form the slit 172, a space of at least 12 μm is required. However, as the liquid crystal display panel increases in resolution, the number of gate links 170 also increases, so that the distance d1 between the gate links 170 is also narrowed. In this case, the slit 172 formed between the gate links 170 may expose the gate link 170 so that a short circuit between the gate link 170 and the dummy transparent conductive pattern 174 may occur. Accordingly, the present invention seeks to further improve lift-off capability and to prevent short circuits between signal links and dummy transparent conductive patterns. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 9F.

4 and 5 are a plan view and a cross-sectional view illustrating a gate pad and a gate link region of a thin film transistor substrate according to a first embodiment of the present invention.

The gate pad 215 is formed in the contact hole 216 penetrating the gate pad lower electrode 212, the passivation layer 224, and the gate insulating layer 222, and is connected to the gate pad lower electrode 212. 214. The gate pad lower electrode 212 is connected to the gate line 102 formed in the display area via the gate link 200 having a bent shape.

The bent gate link 200 includes a first gate link pattern 200a parallel to the gate line 102 and a second gate link pattern bent at a predetermined angle with the first gate link pattern 200a ( 200b). Among them, the second gate link pattern 200b is formed in a group form. The separation distance d1 between the second gate link patterns 200b included in each group may be shorter than that of the related art, and may be short enough to prevent a short circuit therebetween, for example, about 8 to 12 μm. The spacing between the second gate link pattern groups is widened due to the spacing d1 between the second gate link patterns 200b which is reduced than before. That is, the last second gate link pattern 200b included in the i th second gate link pattern group and the first second gate link pattern 200 b included in the i + 1 th second gate link pattern group are relative to each other. Spaced apart with a wide distance (d2) in between.

Slits 206 are formed in the widened region between the second gate link pattern groups. The separation distance W between the slit 206 and the slit 206 formed with the second gate link pattern group therebetween is 200 to 500 μm.

The slit 206 is formed to penetrate the gate insulating film 222 and the protective film 224 as shown in FIG. 5, or to expose the gate insulating film 222 through the protective film 224 as shown in FIG. 6. Is formed. 6, the slit 206 is formed to penetrate the passivation layer 224 so that the gate insulating layer 222 remains as shown in FIG. 6. Exposure can be prevented.                     

In addition, the slits 206 may be used as stripper penetration paths in the lift-off process to facilitate separation of the photoresist pattern and the protective layer 224. The dummy transparent conductive pattern 226 remains in the slit 206 during the leaf-off process.

In addition, since the slit 206 is formed in a relatively wide area, the separation distance d3 between the end of the slit 206 and the end of the second gate link pattern 200b is farther than that of the conventional art. Accordingly, a short circuit between the dummy transparent conductive pattern 226 and the second gate link pattern 200b formed in the slit 206 can be prevented.

These slits are formed between the gate pads as well as the gate links, and are formed between the data links and between the data pads. The slits may be formed individually in each region or may be formed by integrating the slits of the link region and the slits of the pad region.

As described above, the thin film transistor substrate according to the first exemplary embodiment of the present invention is spaced apart so as to prevent a short circuit and a plurality of gate links are formed in each gate link group. Accordingly, the separation distance between the adjacent gate link groups is relatively far apart, and the slit formed in the separation region is spaced apart with the gate link and a sufficient margin area therebetween, thereby preventing a short circuit between the gate link and the dummy transparent conductive pattern.

7 and 8 are a plan view and a cross-sectional view showing a gate pad region of a thin film transistor substrate according to the second embodiment of the present invention.

The gate pad regions shown in FIGS. 7 and 8 have the same components except that the slits are formed to overlap the gate links as compared to the gate pad regions shown in FIGS. 5 and 6. Accordingly, detailed description of the same components will be omitted.

The slits 206 are used as stripper penetration paths during the lift-off process to facilitate separation of the photoresist pattern and the protective film 224. The slits 206 are formed to penetrate the passivation layer 224, and the dummy transparent conductive patterns 226 remain in the slits 206 during the lift-off process.

Since the gate link 200 is protected by the gate insulating layer 222 by the slits 206 formed to pass through the passivation layer 224, a short circuit between the gate link 200 and the dummy transparent conductive pattern 226 can be prevented. have.

In addition, since the slits 206 are formed to overlap the gate links 200, the slits may be easily formed in the link area that decreases with higher resolution.

The gate links 200 formed to overlap the slits 206 are formed to be spaced at equal intervals or as a plurality of gate links spaced at a first interval as shown in FIG. 5 to form an adjacent gate link. Groups may be formed spaced at a second interval.

As described above, the thin film transistor substrate according to the second embodiment of the present invention includes a slit that passes through the passivation layer and overlaps the gate link. Accordingly, since the gate insulating film is protected by the gate link, a short circuit between the gate link and the dummy transparent conductive pattern can be prevented. In addition, the present invention can be applied to a high resolution model by the slit overlapping the gate link.

9A to 9F illustrate cross-sectional views for describing a third mask process in detail in the method of manufacturing the thin film transistor substrate illustrated in FIG. 8. Here, the gate pad manufacturing method and the gate link manufacturing method will be described together.

Referring to FIG. 9A, a passivation layer 224 is entirely formed on the gate insulating layer 222, and a photoresist pattern 250 is formed on the passivation layer 224 by a photolithography process using a third mask. The gate insulating film 222 and the protective film 224 are patterned by a dry etching process using the photoresist pattern 250. Accordingly, as shown in FIG. 9B, a contact hole 216 penetrating through the passivation layer 224 and the gate insulating layer 222 is formed. The contact hole 216 passes through the passivation layer 224 and the gate insulating layer 222 to expose the gate pad lower electrode 212.

Subsequently, a photoresist pattern 250 having a relatively low height is removed as shown in FIG. 9C by an ashing process in a region overlapping a slit to be formed later.

Then, the protective film 224 is patterned by a wet etching process using a hydrofluoric acid-based etching solution using the ashed photoresist pattern as a mask, so that the slit 206 penetrating the protective film 224 as shown in FIG. 9D. ) Is formed. In the portion where the contact hole 216 and the slit 206 are formed in the passivation layer 225, an edge portion of the photoresist pattern 250 protrudes more than an edge portion of the passivation layer 224 due to overetching of the passivation layer 224 (not shown). Has                     

Here, an etching solution of hydrofluoric acid, for example, NH ₄ F, HF, BOE (Buffered Oxide Etchant), and the like are used. In particular, since the BOE is more reactive with an inorganic insulating material such as silicon nitride than the metal, only the protective film 224 is selectively etched. The protective film 224 etched by the BOE is formed to have a gentle inclination angle.

Subsequently, as shown in FIG. 9E, the transparent conductive film 252 is formed on the entire surface of the thin film transistor substrate on which the photoresist pattern 250 exists by a deposition method such as sputtering or the like. The transparent conductive film 252 may be indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). ) Is used.

The transparent conductive film 252 is patterned by removing the photoresist pattern 250 and the transparent conductive film 252 thereon in a lift-off process. At this time, the transparent conductive layer 252 deposited with straightness between the edge portion of the protruding photoresist pattern 250 and the edge portion of the protective film 224 is opened or relatively thinly deposited so that the stripper easily penetrates. can do. As a result, the photoresist pattern 250 covered with the transparent conductive layer 252 is easily separated from the protective film 224 by a stripper.

Accordingly, as shown in FIG. 9F, a third conductive pattern group including the gate pad upper electrode 214 and the dummy transparent conductive pattern 226 is formed.

 As described above, the thin film transistor substrate and the method of manufacturing the same according to the present invention are spaced apart so that a plurality of gate links can be prevented from short-circuit and form them into each gate link group. Accordingly, the separation distance between the adjacent gate link groups is relatively far apart, and the slit formed in the separation region is spaced apart with the gate link and a sufficient margin area therebetween, thereby preventing a short circuit between the gate link and the dummy transparent conductive pattern.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (16)

A thin film transistor connected to the pixel electrode; A signal line group which supplies a signal to the thin film transistor and is formed in a group unit; At least one insulating film formed to cover the signal line group; And a slit formed through the insulating film between the adjacent signal line groups so as to allow penetration of a stripper for removing the photoresist pattern formed on the insulating film of the at least one layer, The separation distance of the signal line group facing the slit between the thin film transistor substrate, characterized in that larger than the separation distance of the signal lines included in the signal line group. The method of claim 1, The slit is The thin film transistor substrate of claim 1, wherein the thin film transistor is formed in a non-display area except for the display area in which the thin film transistor and the pixel electrode are formed. The method of claim 2, The insulating film includes a gate insulating film covering a gate line and a protective film covering a data line, The signal line of the display area includes the gate line and the data line connected to the thin film transistor and crossing the gate insulating layer to define a pixel area; The pixel electrode is formed in the pixel region bordering the protective film formed on the thin film transistor substrate. The method of claim 3, wherein The slit is The thin film transistor substrate of claim 1, wherein the protective layer and the gate insulating layer are formed between the gate link groups connecting the gate line and the gate pad. The method of claim 3, wherein The slit is And a passivation layer formed through the passivation layer to expose the gate insulating layer between the gate link groups connecting the gate line and the gate pad. The method of claim 3, wherein And a second slit formed to cross the gate link connecting the gate line and the gate pad and penetrating through the passivation layer to expose the gate insulating layer. The method of claim 1, The thin film transistor substrate, wherein the separation distance between the slit and the slit formed with the signal line group therebetween is 200 ~ 500㎛. The method of claim 1, The thin film transistor substrate further comprises a dummy transparent conductive pattern remaining in the slit. Supplying a signal to the thin film transistor and forming a signal line group formed in group units; Forming at least one insulating film to cover the signal line group; Forming a slit penetrating the insulating film between the adjacent signal line groups by using the photoresist pattern formed on the insulating film; Removing the photoresist pattern by the stripper penetrated through the slit, The separation distance of the signal line group facing each other with the slit is greater than the separation distance of the signal lines included in the signal line group manufacturing method of a thin film transistor substrate. The method of claim 9, The slit is And a non-display area except for the display area in which the thin film transistor and the pixel electrode are formed. 11. The method of claim 10, Forming the insulating film Forming a gate insulating film covering the gate line and a protective film covering the data line; Forming a signal line of the display area And forming the gate line and the data line connected to the thin film transistor and intersecting the gate insulating layer therebetween. The method of claim 11, The slit is And through the passivation layer and the gate insulating layer between the gate link groups connecting the gate line and the gate pad. The method of claim 11, The slit is And through the passivation layer to expose the gate insulating layer between the gate link groups connecting the gate line and the gate pad. The method of claim 11, And forming a second slit formed to intersect the gate link connecting the gate line and the gate pad and penetrating the passivation layer so that the gate insulating layer is exposed. The method of claim 9, Removing the photoresist pattern by the stripper penetrated through the slit Forming a transparent conductive film on the insulating film having the photoresist pattern for forming the slit; And removing the photoresist pattern covered with the transparent conductive film by the stripper penetrating through the slit, thereby forming a pixel electrode connected to the thin film transistor. The method of claim 15, And forming a transparent conductive pattern in the slit when forming the pixel electrode.

Images