KR101043614B1 - Multiplexing module and multiplexing method for reference clock - Google Patents

Abstract

The present invention relates to a reference clock multiplexing module. The present invention provides a first input unit for inputting a first clock, a second input unit for inputting a second clock, a detector for determining whether the second clock is input, and generating a control signal corresponding thereto; A switch unit for outputting one of the second clocks, a phase locked loop (PLL) for generating an up / down signal by comparing a phase of a clock applied from the first clock and the switch unit, and an up / down signal A reference clock multiplexing module and a method thereof include a voltage adjusting unit for adjusting an output voltage and an oscillator for outputting a reference clock having a frequency equal to a frequency of a first clock corresponding to the output voltage.

Reference Clock, Clock Multiplexing

Description

Reference clock multiplexing module and its method {MULTIPLEXING MODULE AND MULTIPLEXING METHOD FOR REFERENCE CLOCK}

The present invention relates to a reference clock multiplexing module and method thereof.

In general, a mobile communication system includes an exchange, a base station controller, a base station, a repeater, and a mobile communication terminal. The base station and the mobile communication terminal communicate using a specific frequency band.

Base stations and repeaters of telecommunication systems use reference clocks for signal processing.

Recently, base stations and repeaters for 3G or 3.5G mobile communication services have been installed, and these 3G or 3.5G mobile communication services also perform signal processing using a reference clock.

The mobile communication system generates a reference clock at the base station and provides it to the repeater. However, if a failure or replacement of the equipment generating the reference clock occurs, it cannot be recognized, which causes a problem of a call failure of the user of the mobile communication terminal located in the coverage area of the repeater.

In addition, there is a problem that a relay failure occurs because a reference clock signal is not applied to the repeater due to a poor cable connection between the base station and the repeater.

An object of the present invention is to propose a reference clock multiplexing module and a method for reusing an internal reference clock when a reference clock inputted from a base station to a repeater has an error.

Another object of the present invention is to propose a reference clock multiplexing module and a method for using the reference clock input from the third generation mobile communication base station when an error occurs in the reference clock input from the second generation mobile communication base station.

It is another object of the present invention to propose a reference clock multiplexing module and a method for reusing an internal reference clock when frequencies of an input reference clock are different.

According to an aspect of the invention, the first input unit to which the first clock is input; A second input unit to which a second clock is input; A detector configured to determine whether the second clock is input and generate a control signal corresponding thereto; A switch unit configured to output one of the first and second clocks in response to the control signal; A PLL for generating an up / down signal by comparing a phase of the first clock and a clock applied from the switch unit; A voltage controller configured to adjust an output voltage using the up / down signals; And an oscillator for outputting a reference clock having a frequency equal to the frequency of the first clock in correspondence with the output voltage.

According to another aspect of the invention, the step of inputting a first clock; Inputting a second clock; Determining whether the first clock and the second clock are input and generating a control signal corresponding thereto; A switch step of outputting a clock of any one of the first and second clocks in response to the control signal; Generating an up / down signal by comparing a phase of the first clock and a clock output through the switch step; Adjusting an output voltage using the up / down signal; And outputting a reference clock having a frequency equal to the frequency of the first clock in response to the output voltage.

In the reference clock multiplexing module and method according to the present invention, even if an error occurs in the reference clock received from the base station by multiplexing the reference clock, the repeater or equipment below the repeater can perform signal processing using the reference clock using the internal clock. There is an advantage that can prevent the mobile communication system error.

In addition, the reference clock multiplexing module and its method according to the present invention can be easily implemented by using an internal component or a FPGA.

The reference clock multiplexing module and the method according to the present invention can generate an enable clock signal to quickly check whether the frequency of the input clock is equal to the output frequency.

In addition, the reference clock multiplexing module and the method according to the present invention can reduce the cost since the reference clock outputted with the divider can be used in various equipments.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In order to facilitate a thorough understanding of the present invention, the same reference numerals are used for the same means regardless of the number of the drawings.

Prior to the detailed description of the drawings, it is intended to clarify that the division of the components in the present specification is only divided by the main function of each component. That is, two or more components to be described below may be combined into one component, or one component may be provided divided into two or more for each function. Each of the components to be described below may additionally perform some or all of the functions of other components in addition to the main functions of the components, and some of the main functions of each of the components are different. Of course, it may be carried out exclusively by.

1 is a block diagram schematically illustrating a communication system in which a reference clock multiplexing module is installed according to an embodiment of the present invention.

Referring to FIG. 1, the communication system in which the reference clock multiplexing module of the present invention is installed includes a base station 310 and 320, a reference clock multiplexing module 330, a repeater 340 and 350, and a mobile communication terminal 360 and 370. can do.

In detail, the base stations 310 and 320 may include a second generation mobile communication base station 310 and a third generation mobile communication base station 320. In FIG. 1, a case where the second generation mobile communication base station 310 and the third generation mobile communication base station 320 are located at the same place will be described as an example.

The second generation mobile communication base station 310 transmits a communication signal input from the mobile communication terminal 370 or the second generation mobile communication repeater 350 of the subscriber using the second generation mobile communication network to the switching center. The second generation mobile communication base station 310 transmits the signal received from the switching center to the mobile communication terminal 370 or the second generation mobile communication repeater 350.

The third generation mobile communication base station 320 transmits a communication signal input from the mobile communication terminal 360 or the third generation mobile communication repeater 340 of the subscriber using the third generation mobile communication network to the switching center. The third generation mobile communication base station 320 transmits the signal received from the switching center to the mobile communication terminal 360 or the third generation mobile communication repeater 340.

The second generation mobile communication base station 310 or the third generation mobile communication base station 320 may be connected to a plurality of repeaters for communication with a mobile communication terminal located in a communication shadow area other than coverage.

The second generation mobile communication base station 310 is connected with a plurality of second generation mobile communication repeaters 350, and the third generation mobile communication base station 320 is connected with a plurality of third generation mobile communication repeaters 340.

The second generation mobile communication repeater 350 may be installed in an area other than the coverage of the second generation mobile communication base station 320, for example, the interior of a building, the interior of a high-rise building, and a dense residential area. As the second generation mobile communication repeater 350, an optical repeater or an RF repeater may be used. In the present invention, it will be described with an example that the optical repeater is used.

The optical repeater is connected to the base station and the optical fiber, and may include a main hub and a plurality of remote units connected to the main hub. The optical repeater may convert the optical signal input from the base station into an RF signal and provide the signal to the mobile communication terminal after signal processing. In addition, the optical repeater optically modulates the communication signal input from the mobile communication terminal to the base station after digital signal processing. At this time, the reference clock that can synchronize the digital signal processing in the optical repeater is used. The reference clock uses a clock having a 10 MHz frequency input from the reference clock multiplexing module 330.

The reference clock multiplexing module 330 may be installed at an output terminal of the base stations 310 and 320 or an inlet of the repeaters 340 and 350. In addition, the reference clock multiplexing module 330 may be formed inside the repeaters 340 and 350.

The reference clock multiplexing module 330 feeds back the output reference clock and outputs the fed back reference clock when the reference clock is not supplied from the second generation mobile communication base station 310 or the third generation mobile communication base station 320. Through this, it is possible to prevent the communication failure in the various devices after the repeater (340, 350) or repeater (340, 350).

The reference clock multiplexing module 330 may receive the second and third clocks from the second generation mobile communication base station 310 and the third generation mobile communication base station 320.

The second clock is a 10 MHz signal used as a reference clock by the second generation mobile communication base station 310, and the third clock is a 10 MHz signal used as a reference clock by the third generation mobile communication base station 320 when the signal is processed in the repeater. The clock is synchronized.

The reference clock multiplexing module 330 outputs a reference clock of 10 MHz frequency through an internal oscillator using the input second clock. However, when the frequency is different from the frequency of the non-input or output reference clock, the second clock is used to output a reference clock having a 10 MHz frequency through the internal oscillator.

If the second clock and the third clock are not input or the frequency is different from the output reference clock, the reference clock multiplexing module 330 outputs a reference clock having a 10 MHz frequency through an internal oscillator by feeding back the output reference clock. .

A detailed description of the reference clock multiplexing module 330 will be described in more detail with reference to FIGS. 2 to 5.

In the embodiment of the present invention, a case where the second generation base station and the third generation base station are located at the same location is described as an example. However, the reference clock multiplexing module of the present invention may be used in the second generation base station and the third generation base station.

FIG. 2 is a block diagram schematically illustrating the reference clock multiplexing module shown in FIG. 1.

2, the reference clock multiplexing module according to the present invention includes first to third input units 10 to 30, a switch unit 40, a detection unit 50, a PLL 60, and a voltage adjusting unit 70. The oscillator 200 may include an alarm unit 250 and a divider 240.

In detail, a first clock is input to the first input unit 10, and a reference clock output from the oscillator 200 is fed back to the first clock. The second input unit 20 receives a second clock supplied from second generation communication equipment. The third input unit 30 receives a third clock supplied from the third generation communication equipment. Here, the second clock is a reference clock input from the second generation mobile communication base station, and the third clock is a reference clock input from the third generation mobile communication base station. The first to third clocks have a frequency of 10 MHz.

The detector 50 receives the first to third clocks, detects the magnitude of each clock, and generates a control signal corresponding thereto. For example, the detector 50 determines whether the second clock is present and generates a control signal to be supplied to the switch 40. In addition, the detector 50 determines whether the third clock is present and generates a control signal to be supplied to the switch 40.

The detector 50 may generate a control signal corresponding to the comparison result by comparing the input first to third clock sizes with a reference value. Here, the reference value may be 0 dBm. However, the reference value is not limited thereto and may vary depending on the system.

In addition, the detector 50 may generate an alarm signal and provide the generated alarm signal to the alarm unit 250. The detector 50 may generate a control signal when the frequency of the second clock or the third clock is different from the frequency of the first clock, when the second and third clocks are not input, and when the magnitude of the first clock is less than or equal to the reference value. . In this case, the control signal is supplied to the switch unit 40 and is a signal for controlling the switch unit 40 to output the first clock from the switch unit 40.

In addition, the detector 50 may generate an enable clock. The enable clock is generated using the first clock. The detector 50 may detect whether the second clock or the third clock is the same frequency as the first clock by using the enable clock.

The detection unit 50 will be described in more detail with reference to FIG. 4.

The switch unit 40 outputs a clock corresponding to the control signal among the input first to third clocks.

The PLL 60 compares the phase of the first clock with the clock inputted from the switch unit 40 and outputs an UP or DOWN value.

As shown in FIG. 3A, the PLL 60 has an UP value when the phase of the first clock is earlier than the phase of the clock (for example, the second clock) input from the switch 40. Outputs However, as illustrated in FIG. 3B, the PLL 60 outputs a DOWN value when the phase of the first clock is later than the phase of the clock input from the switch 40. The PLL 60 may have no output value when the phase of the first clock is the same as the phase of the clock input from the switch 40.

The voltage adjusting unit 70 changes the voltage level using the UP or DOWN value input from the PLL 60 to supply the oscillator 200. For example, the voltage adjusting unit 70 increases and outputs a voltage when receiving an UP value, and lowers and outputs a voltage by receiving a DOWN value.

When there is no input from the PLL 60, the voltage adjuster 70 may output an intermediate value of the maximum voltage output from the voltage adjuster 70. The intermediate value of the maximum voltage may be a voltage previously input to the voltage adjusting unit 70. For example, the voltage adjusting unit 70 may include a terminal for receiving an up / down value input from the PLL 60 and an external input terminal. The external input terminal uses half of the maximum output voltage. Here, the voltage adjusting unit 70 may include a switch for selecting an up / down value input from the PLL 60 and a voltage value input from an external input terminal.

The switch may switch according to a control signal input from the detector 50. That is, when there is no up / down value from the PLL 60, the voltage controller 70 may generate a case in which the second and third clocks are not input. In this case, the detector 50 generates a control signal corresponding to the case where the second and third clocks are not input, and transmits the generated control signal to the switch 40 and the voltage adjuster 70. The voltage regulator 70 may switch an internal switch to select an external input terminal through the transmitted control signal.

The oscillator 200 generates a reference clock corresponding to the voltage level input from the voltage adjuster 70. For example, the oscillator 200 may use an oven controlled crystal oscillator (OCXO) or a voltage controlled crystal oscillator (VCXO).

The reference clock output from the oscillator 200 is filtered through the filter 210 and amplified by the amplifier 220. Here, a coupler 230 is provided between the filter unit 210 and the amplifier 220 to feed back the reference clock to the first input unit 10.

The alarm unit 250 receives an alarm signal from the detector 50 and provides information to the user by means of light, sound, and the like. For example, the alarm unit 250 may operate when the second and third clocks are not input. In addition, the alarm unit 250 may be operated when the size of the reference clock input to the second input unit 20 is small and is changed to the reference clock input to the third input unit 30, or vice versa. .

In the reference clock multiplexing module 330 according to the present invention, the first to third input units 10 to 30, the switch unit 40, the detection unit 50, the PLL 60, and the voltage adjusting unit 70 have one circuit. It may be implemented as a chip 100. It may also be implemented using a field programmable gate array (FPGA).

4 is a block diagram illustrating in detail a detector illustrated in FIG. 2.

Referring to FIG. 4, the detector 50 may include a clock magnitude detector 51, an enable clock generator 52, a frequency comparator 55, a control signal generator 53, and an alarm signal generator 54. It may include.

In detail, the clock size detector 51 may detect sizes of input reference clocks. The clock size detector 51 may compare the maximum value or the effective value of the reference clock input to the first input unit 10 with a preset reference value. The clock size detector 51 may compare the maximum value or the effective value of the reference clocks input to each of the second and third input units 20 and 30 with a preset reference value.

The enable clock generator 52 generates an enable clock using the first clock. As shown in FIG. 5, the enable clock generation unit 52 generates an enable clock having a different period based on a clock in which the first clock is repeated every predetermined number of times. For example, the enable clock generator 52 may generate an enable clock having a predetermined period by generating one clock for every five rising parts of the first clock.

Here, the enable clock generator 52 may transmit the generated enable clock to the frequency comparator 55. In addition, the enable clock generator 52 may transmit the enable clock to the PLL 60.

The frequency comparator 55 compares the second clock with the enable clock to determine whether the frequency is the same as the first clock. As shown in FIG. 6, the frequency comparator 55 may quickly determine whether the frequency of the second clock is the same as the frequency of the first clock through clock counting of the second clock during one period of the enable clock. have. The frequency comparator 55 transmits the result to the alarm signal generator 54 when the frequency is different as a result of the frequency comparison.

The frequency comparison unit 55 determines whether the frequency of the third clock is the same as the frequency of the first clock through the clock counting of the third clock when the frequency is different as a result of the frequency comparison between the enable clock and the second clock. As a result of the determination, when the frequencies are the same, the determination result is transmitted to the control signal generator 53.

The control signal generator 53 generates a control signal for switching the switch of the switch 40 of FIG. 2. Table 1 summarizes the types of control signals generated by the control signal generator 53.

[Table 1] Control Signal

division Condition Control signal form First control signal When the second clock is detected (more than the reference value) 0001 Second control signal When the second clock is not detected and the third clock is detected (more than the reference value) 0010 Third control signal When the second and third clocks are not detected and the first clock is greater than or equal to the reference value 0011 Fourth control signal When the frequency of the second clock is different from the first clock, and the frequency of the third clock is the same as the first clock 0100 Fifth control signal If the frequency of the second and third clock is different from the first clock 0101

As shown in Table 1, the control signal generator 53 receives a result of detecting the second clock from the clock size detector 51 to generate a first control signal, and converts the generated first control signal into the switch unit 40. Supplies). In this case, the control signal generator 53 generates the first control signal when the magnitude of the second clock is greater than or equal to the reference value. The first control signal may be a binary signal and may be generated as “0001” as shown in Table 1.

The control signal generator 53 generates a second control signal by receiving a result from which the second clock is not detected from the clock size detector 51 or less than a reference value and a result of detecting the third clock. In this case, the second control signal may be a binary signal and may be generated as “0010”. The control signal generator 53 generates a second control signal when the third clock is equal to or greater than the reference value.

The control signal generator 53 generates a third control signal when the second and third clocks are undetected or less than or equal to the reference value and the first clock is greater than or equal to the reference value from the clock size detector 51. The third control signal may be a binary signal and may be generated as “0011”.

The control signal generator 53 generates a fourth control signal from the frequency comparator 55 when the frequency of the second clock is different from the first clock and the frequency of the third clock is the same as the first clock. The fourth control signal may be a binary signal and may be generated as “0100”.

The control signal generator 53 receives a result from the frequency comparator 55 when the frequencies of the second and third clocks are different from the first clock, and generates a fifth control signal. The fifth control signal may be generated as “0101” as a binary signal.

The switch unit 40 shown in FIG. 2 receives the first control signal and outputs a second clock. The switch unit 40 receives the second and fourth control signals and outputs a third clock. The switch unit 40 outputs the first clock when the third and fifth control signals are received. Through this, even when the reference clock is not input due to failure or replacement of the reference clock generator of the second and third generation mobile communication base stations, the reference clock may be output to prevent problems such as communication errors in the mobile communication system.

The above control signals are only an embodiment of the present invention, and may generate a control signal that can be supplied to the switch unit 40 in other cases. In addition, Table 1 illustrates a case where the control signal is 4 bits, for example. And so on.

The control signal generator 53 generates the control signal by receiving the result value from the clock size detector 51 or the frequency comparator 55, but the clock size detector 51 and the frequency comparator 55 It may be implemented with circuits that include.

The alarm signal generator 54 generates an alarm signal by using a result value input through the clock magnitude detector 51 or the frequency comparator 55.

For example, the alarm signal generator 54 may generate an alarm signal when the second clock is not detected by the clock size detector 51. The alarm signal generator 54 may generate an alarm signal even when the second and third clocks are not detected by the clock size detector 51. In addition, the alarm signal generator 54 may generate an alarm signal even when the magnitude of the first clock is less than or equal to the reference value.

The alarm signal generator 54 may generate an alarm signal through the frequency comparator 55 even when the frequency of the second clock is different from the first clock or the frequency of the second and third clocks is different from the first clock. Can be.

The alarm signal generated by the alarm signal generator 54 may be transmitted to the alarm 250 to provide the user with information about the clock status of the clock multiplexing module.

In the above description, the clock multiplexing module to which the first to third clocks are input is described as an example. However, even when the third clock is not input, the clock multiplexing module using the first and second clocks may operate.

7 is a flowchart illustrating a reference clock multiplexing method according to an embodiment of the present invention.

Referring to FIG. 7, the first and second clock input steps S100, the control signal generation step S200, the switch step corresponding to the control signal S300, the up / down signal generation step S400, and the output voltage adjustment A step S500 and a reference clock output step S600 may be included.

In detail, in the first and second clock input steps S100, the first and second clocks are input to the input unit of the reference clock multiplexing module. In this case, the first clock may be a clock to which the reference clock output from the reference clock multiplexing module is fed back, and the second clock may be a reference clock supplied from second or third generation communication equipment.

At this time, in the first and second clock input step S100, other clocks may be input in addition to the first and second clocks, and the input clock may be a reference clock supplied from second or third generation communication equipment.

In the control signal generation step (S200), the detector determines whether the first clock and the second clock are input and generates a control signal corresponding thereto.

In this case, the control signal may be generated for each condition of Table 1 described above. Here, the condition may be a condition for whether the first clock and the second clock are input, a condition for the set reference value and the magnitude of the input clocks, a condition for the input frequency, and the like. Detailed description thereof will be omitted. The control signal generated by the detector is supplied to the switch.

On the other hand, the alarm signal may be generated in the control signal generation step (S200). That is, an alarm signal may be generated when the magnitudes of the clock signals are compared with the reference value or less. In addition, an alarm signal may be generated when the frequency of the second clock is different from the first clock.

The switch step S300 corresponding to the control signal may receive the control signal to control the output of the switch unit. That is, the switch unit may selectively output one of the first clock and the second clock according to the input control signal.

The up / down signal generation step S400 generates an up / down signal by comparing the phase of the signal output from the first clock and the switch unit. For example, the PLL is used to compare the phase of the signal output from the first clock and the switch unit. As a result of the phase comparison, when the phase of the first clock is high, a signal having an UP value is generated. When the phase of the first clock is low, a signal having a DOWN value is generated.

The output voltage adjusting step S500 supplies a voltage to the oscillator in response to the up / down signal input from the PLL in the voltage regulator. When the voltage controller receives an UP value, the voltage controller increases and outputs the voltage. The voltage controller receives a DOWN value and lowers the voltage. In this case, when there is no signal output from the PLL and there is no value input to the voltage controller, the median value of the maximum voltage output from the voltage controller may be output.

The reference clock output step S600 outputs a reference clock corresponding to the voltage level input from the voltage adjuster in the oscillator. The oscillator outputs a reference clock using OCXO, VCXO, or the like.

The output reference clock may be filtered and amplified and output.

In the above embodiment, a case where the first and second clocks are input is described as an example. However, the present invention is not limited thereto, and a reference clock may be output even when a plurality of clocks are input.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

1 is a block diagram illustrating a communication system in which a reference clock multiplexing module of the present invention is used.

FIG. 2 is a block diagram schematically illustrating the reference clock multiplexing module shown in FIG. 1. FIG.

3 is a timing diagram illustrating an example of generating an up / down value in the PLL shown in FIG. 2;

4 is a block diagram illustrating in detail the detector illustrated in FIG. 2.

FIG. 5 is a waveform diagram illustrating an enable clock generated by the enable clock generator shown in FIG. 4. FIG.

6 is a waveform diagram of determining whether a frequency of a second or third clock is the same as the first clock by using an enable clock in a frequency comparator;

7 is a flowchart illustrating a reference clock multiplexing method according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10 to 30: first to third input unit 40: switch unit

50: detection unit 60: PLL (Phase Locked Loop)

70: voltage regulator 200: oscillator

210: filter unit 220: amplification unit

230: Coupler 240: Dividers

250: alarm unit 310, 320: base station

330: reference clock multiplexing module 340, 350: repeater

Claims (13)

A first input unit to which a first clock is input; A second input unit to which a second clock is input; A detector configured to determine whether the first and second clocks are input and generate a control signal corresponding thereto; A switch unit configured to output one of the first and second clocks in response to the control signal; A phase locked loop (PLL) for generating an up / down signal by comparing a phase of the first clock and a clock applied from the switch unit; A voltage controller configured to adjust an output voltage using the up / down signals; And And an oscillator for outputting a reference clock having a frequency equal to the frequency of the first clock in response to the output voltage. The method of claim 1, The first clock is a reference clock multiplexing module, characterized in that the reference clock is fed back. The method according to claim 1 or 2, And a divider, which divides the reference clock into at least two paths due to a defect in an output terminal of the oscillator. The method according to claim 1 or 2, A filter unit to filter the reference clock; And And amplifying unit for amplifying the reference clock output from the filter unit. The method according to claim 1 or 2, And the reference clock has a frequency of 10 MHz. The method according to claim 1 or 2, The detection unit A clock magnitude detector for detecting magnitudes of the first clock and the second clock; An enable clock generation unit generating a enable clock having a frequency lower than that of the first clock by generating a clock at a predetermined clock number of the first clock; A frequency comparison unit for counting the number of clocks of the second clock within one period of the enable clock and comparing the frequency of the second clock and the first clock; And a control signal generator configured to generate the control signal based on clock size information from the clock size detector and frequency information received from the frequency comparator. The method of claim 6, The clock size detector If the second clock is less than or equal to the reference value, and transmits a signal whose second clock is less than or equal to the reference value to the control signal generation unit, And the control signal generation unit generates the control signal to receive a signal having a second clock equal to or less than a reference value and to select the first clock. The method of claim 6, The clock size detector generates an alarm signal when the second clock is not present or less than a reference value, or when the frequency information input from the frequency comparator is not equal to the frequency of the first clock. A reference clock multiplexing module further comprising an alarm signal generator. The method according to claim 1 or 2, Further comprising a third input unit to which the third clock is input, And the detector generates a second control signal for outputting the third clock and transmits the second control signal to the switch unit when the second clock is not input to the second input unit. The method of claim 9, And the third clock is a base station reference clock input from a mobile communication base station. The method of claim 9, The detection unit The reference clock multiplexing module of claim 3, wherein when the third clock is not input to the third input unit or is less than a reference value, a third control signal for controlling the output of the first clock is generated and transmitted to the switch unit. The method of claim 1, The PLL is If the phase of the first clock is faster than the clock input through the switch unit transmits the up signal to the voltage adjusting unit, And if the phase of the first clock is later than a clock input through the switch, transmitting the down signal to the voltage adjuster. Inputting a first clock; Inputting a second clock; Determining whether the first clock and the second clock are input and generating a control signal corresponding thereto; A switch step of outputting a clock of any one of the first and second clocks in response to the control signal; Generating an up / down signal by comparing a phase of the first clock and a clock output through the switch step; Adjusting an output voltage using the up / down signal; And And outputting a reference clock having a frequency equal to the frequency of the first clock corresponding to the output voltage.

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