KR101028738B1 - Method for formating pattern of circuit on backplane - Google Patents

Abstract

PURPOSE: A method for forming a circuit pattern in a backplane is provided to remove weak problem of a vibration structure due to a cable connection by designing a star link pattern to a VME backplane. CONSTITUTION: Slots combined with each VME board for a two-way communication is installed on a first surface of a backplane(S200). A circuit pattern is formed on a second surface of a back plane which is communicable between VME boards through slots mounted on the first surface of the back plane(S210). A stripline is formed on a second surface of a back plane(S211). Another strip line is formed on a second surface of at least on back plane(S212). One or more signal line of the other standard is formed on the second surfa of backplane(S213).

Description

How to form a circuit pattern on the backplane {Method for formating pattern of circuit on backplane}

The present invention relates to a method of forming a circuit pattern on a backplane and to the backplane. More particularly, it relates to a method of forming a circuit pattern for communication on a backplane and a backplane thereof.

The starlink communication method, which has been conventionally connected with cables, has many problems such as cost increase due to rear card (rear transition module) and cable connection, fragility, vibration, and disassembly / assembly.

1 is a conceptual diagram illustrating a conventional star link communication connection structure. Star link communication connection between the conventional Versa Module Eurocard (VME) board 100, as shown in Figure 1 after mounting the rear card 120 to the P2 / J2 or P0 / J0 connector from the back of the VME backplane (110) The communication cable 130 is connected to the connector port 121 to provide a Starlink communication path between the VME boards.

However, when there are several VME boards that need to perform star link communication in the VME bus, structural weakness occurs due to mounting of multiple rear cards and cable connections. In this case, there are problems such as increased cost, weak vibration structure due to cables, poor maintenance due to difficulty in disassembly / assembly, weight increase, and structural complexity.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a backplane design technique, ie, a method of forming a circuit pattern on the backplane, and a backplane designed by implementing high-speed star link communication as a PCB pattern on a general-purpose VME backplane. The purpose.

SUMMARY OF THE INVENTION The present invention has been made to achieve the above object, comprising the steps of: (a) mounting slots coupled with respective Versa Module Eurocard (VME) boards for bidirectional communication to a first side of a backplane; And (b) forming a circuit pattern on the second side of the backplane to enable communication between VME boards through slots mounted on the first side. to provide.

Preferably, the step (b) comprises: (ba) patterning a stripline on the second surface for connecting terminals of two different slots protruding to the second surface; (bb) patterning at least one other stripline on the second side such that a predetermined first distance difference is formed with respect to the nearest stripline; And (bc) patterning at least one signal line having a different specification on the second surface such that a second predetermined distance difference is formed with respect to the nearest stripline.

Preferably, the strip line includes a pair of signal lines, and the step (ba) patterns the strip line in consideration of the distance between the signal lines and the width of each signal line.

Preferably, the step (bb) sets the first distance difference to 20 mils to 30 mils, and the step (bc) sets the second distance difference to 30 mils to 50 mils.

The present invention also provides a backplane in which a circuit pattern for communication is formed on one surface according to a method of forming a circuit pattern on the backplane.

According to the present invention, the following effects can be obtained by designing and applying a star link pattern to a VME backplane. First, cost savings are possible compared to traditional methods such as cabling. Second, it is possible to eliminate the problem of weak vibration structure due to the cable connection. Third, maintenance can be improved without disassembly / assembly. Fourth, effects such as weight reduction and structural complexity can be expected.

1 is a conceptual diagram illustrating a conventional star link communication connection structure.
2 is a flow chart illustrating a method of forming a circuit pattern on the backplane.
3 is a schematic diagram of a star link communication pattern in a VME backplane implemented according to the present embodiment.
4 is a diagram illustrating a stripline design method according to the present embodiment.
5 is a diagram showing a simulation result of a star link pattern design.
6 is a photograph of a VME backplane implemented with a star link pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are assigned to the same components as much as possible even if displayed on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the following will describe a preferred embodiment of the present invention, but the technical idea of the present invention is not limited thereto and may be variously modified and modified by those skilled in the art.

2 is a flow chart illustrating a method of forming a circuit pattern on the backplane. The following description refers to FIG. 2.

In the prior art, there was a difficulty in forming a communication pattern on the VME backplane. This is because the lack of technology to design and fabricate PCB patterns while maintaining the desired impedance has prevented the creation of precisely controlled boards. Therefore, in this embodiment, to solve this problem, a high speed communication pattern is realized by performing impedance matching using a micro strip technology, which is one of RF signal processing techniques.

First, slots coupled with each Versa Module Eurocard (VME) board for bidirectional communication are mounted on a first surface of the backplane (S200).

Thereafter, a circuit pattern is formed on the second surface of the backplane so as to communicate between the VME boards through slots mounted on the first surface of the backplane (S210). Preferably, the step of forming the circuit pattern (S210) can be embodied as follows.

In a first step, a strip line for connecting the terminals of two different slots protruding to the second surface of the backplane is patterned on the second surface of the backplane (S211). Thereafter, in the second step, another stripline is patterned on at least one second surface of the backplane such that a predetermined first distance difference is formed with respect to the nearest stripline (S212). When the stripped patterned strip line is referred to as a first strip line in step S211, the second strip line is patterned adjacent to the first strip line in step S212, and the third strip line is patterned adjacent to the second strip line. . In this embodiment at least three striplines are patterned on the second side of the backplane in this manner. Subsequently, in a third step, at least one signal line having a different specification is patterned on the second surface of the backplane such that a second predetermined distance difference is formed with respect to the nearest stripline (S213).

In this embodiment, the stripline includes a pair of signal lines. In this case, in the step S211 of forming a strip line on the second surface of the backplane, the strip line is patterned in consideration of the distance between the signal lines and the width of each signal line.

Patterning the stripline on the second surface of the at least one backplane (S212) may include a first distance difference of 20 mils to 30 mils, and patterning the at least one signal line on the second surface of the backplane (S213). The second distance difference is 30 mils to 50 mils.

According to the backplane according to the present embodiment, a circuit pattern for communication is formed on one surface of the backplane according to the method described above with reference to FIG. 2 (a method of forming a circuit pattern on the backplane).

Next, an actual implementation of a method of forming a circuit pattern on the backplane will be described.

The starlink pattern design in the VME backplane proposed through this embodiment is a starlink communication pattern for a VME backplane that uses starlink communication, which is used for high-speed serial communication, instead of a conventional cable connection method. By designing / applying, the safety and serviceability are improved.

A typical VME backplane supports the international standard Versa Module Eurocard (VME) bus and uses three DIN connectors (P0 / J0, P1 / J1, P2 / J2). The VME64 / 64X specification uses a 160-pin connector for P1 / J1 and P2 / J2 and a 95-pin connector for P0 / J0.

Starlink communications, which are widely used for military purposes as high-speed gigabit communications, are not supported by the VME standard but can be connected by cable using the P2 / J2 or P0 / J0 connector signal lines available for expansion in the VME.

For Starlink communication, the Star Memean Card (PMC) must be installed on the VME board. Maximum speed is 440MB / sec in one direction and 500MB / sec in both directions. The communication signal consists of one unidirectional channel with eight signal lines of low voltage differential signaling (LVDS) signals D0 ±, D1 ±, D2 ±, and D3 ±. The electrical specification of the Starlink signal is 2.5mA to 4.5mA (at 622Mbps rate) and nominal 400mV peak to peak (at typical center point at + 1.2Vdc).

Two-way communication requires at least two 16-channel signal lines and provides four communication channels (A, B, C, and D) per Starlink PMC. Two channels may be bundled and used in one bundle mode to transmit a large amount of communication data. To connect two boards in both directions with Starlink communication, two rear cards and four communication cables are required.

3 is a schematic diagram of a star link communication pattern in a VME backplane implemented according to the present embodiment. In particular, Figure 3 is an example of Starlink pattern design routing in a VME backplane that can accommodate 10 VME boards, where Slot # 2 is the root of the Starlink structure and the other slots are connected as leafs. Structure. A, B, C, and D mean each star link channel in the corresponding slot. Slot # 1 uses one Starlink PMC, so four channels (A, B, C, D) are shown on the P0 connector, and Slot # 2 through Slot # 8 use two Starlink PMCs for each slot. A total of 8 channels are connected to the P2 connector, 4 channels each. Hereinafter, a PCB pattern design method of each communication line connected between star link channels will be described in detail.

4 is a diagram illustrating a stripline design method according to the present embodiment. The stripline design method according to the present embodiment is used for impedance matching in RF circuit design, and adopts an edge-coupled shape pattern among two methods of stripline to implement a star link communication pattern. do. The stripline structure is used for line impedance equalization of LVDS starlink signals in the VME backplane layer. In FIG. 4, A indicates an edge-coupled shape pattern, and B indicates a broadside-coupled shape pattern. C points to the copper ground plane and D points to differential traces constructed in stripline.

5 is a diagram illustrating a simulation result of a starlink pattern design, and FIG. 6 is a photograph of a VME backplane in which a starlink pattern is implemented. Using the stripline simulation tool before PCB fabrication as shown in FIG. 5, the star link pattern may be matched to a desired impedance, and a trial and error may be reduced by fabricating a VME backplane.

In the conventional VME system, when high-speed star link communication between boards is required, a cost increase and structural problems occur because the rear card and the cable must be mounted and connected, but in the present invention, the cable is inserted into the inner layer of the VME backplane This problem is solved by designing a star link pattern.

A star link pattern is designed to allow impedance matching of LVDS signal lines using stripline circuit design method, which is widely used in RF circuit design. As a result, we confirmed that the communication speed equivalent to the cable connection is realized. The star link pattern design method in the VME backplane is as follows.

The star link signal is assigned to the inner layer pattern of the VME backplane, but not to the outer layer. The star link signal, which is a one pair pattern composed of LVDS signals, is designed by applying an edge-coupled pattern as a stripline type. At this time, the spacing between +/- patterns is maintained at 3.5 mils to 6.5 mils (preferably 5 mils) and the width of each pattern is designed to be 6 mils to 10 mils (preferably 8 mils). In the above, 1 mils = 1/1000 inch = 0.0254 mm. This figure is typical of 100Ω impedance differential traces (tolerance 100Ω ± 5%). Four pairs of signals in the same channel on the PCB pattern should maintain the same length (tolerance ± 0.13mm) on the same layer as possible. Minimize crosstalk effects by keeping at least 20 mils away from other LVDS pair signals. Minimize crosstalk effects by keeping at least 30 mils away from signal lines of other specifications such as CMOS and TTL.

As described above, the star link pattern design method enables high-speed data communication, and thus is applicable to other communication fields that require a high communication speed of more than a gigabit. For example, Gigabit Ethernet communication can be implemented with the same PCB pattern to achieve near equivalent communication speeds.

The above description is merely illustrative of the technical idea of the present invention, and various modifications, changes, and substitutions may be made by those skilled in the art without departing from the essential characteristics of the present invention. will be. Accordingly, the embodiments disclosed in the present invention and the accompanying drawings are not intended to limit the technical spirit of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by the embodiments and the accompanying drawings. . The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

The present invention can be applied to star link communication, which is widely used for military use in electronic warfare systems, avionics systems, command control systems, and the like as high speed gigabit communication.

100: VME board 110: VME backplane
120: rear card 121: connector port
130: communication cable

Claims (5)

A slot mounting step of mounting slots coupled with respective Versa Module Eurocard (VME) boards for bidirectional communication to a first side of the backplane; And
Forming a circuit pattern on a second side of the backplane to enable communication between VME boards through slots mounted on the first side, for connecting terminals of two different slots protruding to the second side; A first strip line including a pair of signal lines is patterned on the second surface, and the size of the first strip line is determined according to the distance between the signal lines included in the first strip line and the width of each signal line. A stripline forming step of adjusting and patterning the first stripline on the second surface; A stripline forming step of forming at least two patterns sequentially on the second surface of the second stripline at predetermined first intervals in one direction from the first stripline; And a communication line forming step of sequentially forming at least two pattern communication lines having different specifications from the first strip line on the second surface at predetermined second intervals in one direction from the first strip line.
Method for forming a circuit pattern on a backplane comprising a. delete delete The method of claim 1,
The step 2 of forming the stripline uses 20 mils to 30 mils at the first interval and the step of forming the communication line uses 30 mils to 50 mils at the second interval. delete

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