KR101025920B1 - METHOD FOR MANUFACTURING MaskROM CELL TRANSISTOR - Google Patents

METHOD FOR MANUFACTURING MaskROM CELL TRANSISTOR Download PDF

Info

Publication number
KR101025920B1
KR101025920B1 KR1020030051655A KR20030051655A KR101025920B1 KR 101025920 B1 KR101025920 B1 KR 101025920B1 KR 1020030051655 A KR1020030051655 A KR 1020030051655A KR 20030051655 A KR20030051655 A KR 20030051655A KR 101025920 B1 KR101025920 B1 KR 101025920B1
Authority
KR
South Korea
Prior art keywords
transistor
oxide film
poly
layer
oxygen
Prior art date
Application number
KR1020030051655A
Other languages
Korean (ko)
Other versions
KR20050012953A (en
Inventor
최성곤
Original Assignee
매그나칩 반도체 유한회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 매그나칩 반도체 유한회사 filed Critical 매그나칩 반도체 유한회사
Priority to KR1020030051655A priority Critical patent/KR101025920B1/en
Publication of KR20050012953A publication Critical patent/KR20050012953A/en
Application granted granted Critical
Publication of KR101025920B1 publication Critical patent/KR101025920B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

본 발명은 오프 트랜지스터를 생성하기 위해 선택적으로 이온 주입을 할 수 있도록 패턴을 형성한 후, 폴리 내에 산소를 이온 주입한 후 열을 가하여 폴리 내에 산화막을 형성함으로써, 폴리 내에 산화막이 형성되면 게이트 산화막이 두꺼워지는 현상과 동일하므로 임계전압을 상승시킬 수 있는 마스트롬 셀 트랜지스터 제조방법을 제공하는 것이다. 마스크롬 셀 트랜지스터 제조방법은 실리콘 기판 상에 BN+ 층을 형성한 후, 그 위에 BN+ 산화막을 형성하는 단계와, N-폴리층 및 텅스텐 실리사이드층을 순차적으로 형성하는 단계와, 오프 트랜지스터를 만들 영역에 대해 마스킹 층으로 포토레지스터를 이용하여 상기 오프 트랜지스터 영역에 산소를 이온주입하여 이온 주입된 산소와 폴리가 후에 가해지는 열에 의하여 산화막을 형성하는 단계를 포함한다.
According to the present invention, a pattern is formed to selectively perform ion implantation in order to produce an off transistor, and then ion implanted with oxygen in a poly, followed by heat to form an oxide film in the poly, thereby forming a gate oxide film in the poly. Since the same as the thickening phenomenon is to provide a method for manufacturing a mast cell transistor that can raise the threshold voltage. In the method of manufacturing a mask rom cell transistor, a BN + layer is formed on a silicon substrate, and then a BN + oxide film is formed thereon, an N-poly layer and a tungsten silicide layer are sequentially formed, and a region for making an off transistor is formed. Ion implanting oxygen into the off-transistor region using a photoresist as a masking layer, thereby forming an oxide film by heat applied after the ion-implanted oxygen and poly.

마스크롬 셀 트랜지스터, 산소이온주입, 게이트 산화막 Mask ROM Cell Transistor, Oxygen Ion Implantation, Gate Oxide

Description

마스크롬 셀 트랜지스터 제조방법{METHOD FOR MANUFACTURING MaskROM CELL TRANSISTOR} METHODE FOR MANUFACTURING MaskROM CELL TRANSISTOR             

도 1a 내지 도 1c는 본 발명의 바람직한 실시예에 따른 마스트롬 셀 트랜지스터 제조방법을 설명하기 위한 단면도들을 도시한다. 1A to 1C are cross-sectional views illustrating a method for manufacturing a mast cell transistor according to a preferred embodiment of the present invention.

도 2는 본 발명의 바람직한 실시예에 따라 형성된 오프 트랜지스터와 온 트랜지스터를 나타내기 위한 단면도이다. 2 is a cross-sectional view illustrating an off transistor and an on transistor formed according to a preferred embodiment of the present invention.

또한, 도 3은 본 발명의 바람직한 실시예에 따라 형성된 마스크롬 셀 트랜지스터의 레이아웃을 도시한다.
3 shows a layout of a mask ROM cell transistor formed in accordance with a preferred embodiment of the present invention.

- 도면의 주요부분에 대한 부호의 설명 -   -Explanation of symbols for the main parts of the drawings-

100 : 실리콘 기판 102 : BN+100 silicon substrate 102 BN +

104 : BN 산화막 106 : N-폴리104: BN oxide film 106: N-poly

108 : 텅스텐 실리사이드 110 : 포토 레지스트108: tungsten silicide 110: photoresist

112 : 게이트 산화막
112: gate oxide film

본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 보다 상세하게는, 마이크로 컨트롤러 유니트(MCU; micro controller unit) 칩과 같은 병합된 마스크롬(embeded MaskROM) 또는 마스크롬 단품에 적용할 수 있는 마스크롬 셀 트랜지스터의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a mask ROM cell applicable to an integrated mask ROM or a mask ROM unit such as a micro controller unit (MCU) chip. A method of manufacturing a transistor.

종래의 기술은 오프 트랜지스터를 형성하기 위해 게이트를 뚫고 지나서 채널 영역에 보론(boron)을 주입하여 고전압 임계전안(Vt; threshold voltage)를 갖는 오프 트랜지스터를 만들었다. Prior art has injected boron into the channel region past a gate to form an off transistor to create an off transistor with a high threshold voltage (Vt).

이러한 종래 기술의 문제점은 주입한 보론이 후공정에서의 히트 사이클(heat cycle)로 인하여 확산이 되어 온 트랜지스터의 Vt를 상승시키고 있어 전류가 감소되는 것이다. The problem of the prior art is that the injected boron raises the Vt of the transistor which has been diffused due to the heat cycle in a later process, so that the current is reduced.

또한, 게이트를 뚫고 들어가는 이온주입을 하기 위해서는 이온 주입하는 에너지가 약 150 KeV 정도로 상당히 높아야 하며, 에너지가 높을수록 보론의 산란(scattering) 현상이 심해지는 문제점이 있다. In addition, in order to perform ion implantation through the gate, the ion implantation energy should be considerably high, about 150 KeV, and the higher the energy, the worse the scattering phenomenon of boron.

본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 주목적은 오프 트랜지스터를 생성하기 위해 선택적으로 이온 주입을 할 수 있도록 패턴을 형성한 후, 폴리 내에 산소를 이온 주입한 후 열을 가하여 폴리 내에 산화 막을 형성함으로써, 폴리 내에 산화막이 형성되면 게이트 산화막이 두꺼워지는 현상과 동일하므로 임계전압을 상승시킬 수 있는 마스트롬 셀 트랜지스터 제조방법을 제공하는 것이다.
The present invention was devised to solve the above problems, and the main purpose of the present invention is to form a pattern for selectively ion implantation in order to generate an off transistor, and then ion-inject oxygen into the poly and then heat it. The present invention provides a method for manufacturing a mast cell transistor which can increase the threshold voltage by adding an oxide film in the poly, thereby increasing the gate voltage when the oxide film is formed in the poly.

상기와 같은 목적을 실현하기 위한 본 발명은 실리콘 기판 상에 BN+ 층을 형성한 후, 그 위에 BN+ 산화막을 형성하는 단계와, N-폴리층 및 텅스텐 실리사이드층을 순차적으로 형성하는 단계와, 오프 트랜지스터를 만들 영역에 대해 마스킹 층으로 포토레지스터를 이용하여 상기 오프 트랜지스터 영역에 산소를 이온주입하여 이온 주입된 산소와 폴리가 후에 가해지는 열에 의하여 산화막을 형성하는 단계를 포함하는 것을 특징으로 하는 마스크롬 셀 트랜지스터 제조방법을 제공한다. The present invention for realizing the above object is a step of forming a BN + layer on a silicon substrate, and then forming a BN + oxide film thereon, sequentially forming an N-poly layer and a tungsten silicide layer, the off transistor And implanting oxygen into the off-transistor region using a photoresist as a masking layer for the region to be formed, thereby forming an oxide film by heat applied after ion-implanted oxygen and poly. Provided is a method for manufacturing a transistor.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment is not intended to limit the scope of the present invention, but is presented by way of example only.

도 1a 내지 도 1c는 본 발명의 바람직한 실시예에 따른 마스크롬 셀 트랜지스터 제조방법을 설명하기 위한 단면도들을 도시한다. 1A to 1C are cross-sectional views illustrating a method of manufacturing a mask ROM cell transistor according to a preferred embodiment of the present invention.

먼저, 도 1a에 도시한 바와 같이, 본 발명의 바람직한 실시예에 따르는 마스크롬에서 사용되는 트랜지스터를 도식화하였으며, BN+는 각 트랜지스터의 소오스/드레인을 형성하며 게이트는 N-폴리와 텅스텐 실리사이드(WSix)로 구성되어있다. 먼저, 실리콘 기판(100) 상에 BN+ 층(102)을 형성한 후, 그 위에 BN+ 산화막(104) 을 형성한다. 그리고 나서, N-폴리층(106) 및 텅스텐 실리사이드층(108)을 순차적으로 형성한다. First, as illustrated in FIG. 1A, a transistor used in a mask rom according to a preferred embodiment of the present invention is illustrated, BN + forms a source / drain of each transistor, and the gate is N-poly and tungsten silicide (WSix). Consists of First, a BN + layer 102 is formed on the silicon substrate 100, and then a BN + oxide film 104 is formed thereon. Then, N-poly layer 106 and tungsten silicide layer 108 are sequentially formed.

이어서, 도 1b에 도시한 바와 같이, 오프 트랜지스터를 만들 영역에 대해 마스킹 층으로 포토레지스터(110)를 이용한다. 오프 트랜지스터 영역에 산소를 이온주입하며 이온 주입된 산소와 폴 리가 후에 가해지는 열에 의하여 산화막(112)을 형성하게 된다. Subsequently, as shown in FIG. 1B, the photoresist 110 is used as a masking layer for the region where the off transistor is to be made. Oxygen is implanted into the off-transistor region, and the oxide film 112 is formed by the heat applied after the ion-implanted oxygen and poly.

다음 단계로, 도 1c에 도시한 바와 같이, 형성된 산화막(112)은 게이트 산화막(111) 위에까지 자동으로 형성된다. 결과적으로, 게이트에는 실리콘(Si)에 대한 소오스가 없으므로 두꺼운 게이트 산화막(111)을 형성한 오프 트랜지스터를 형성할 수 있다. Next, as shown in FIG. 1C, the formed oxide film 112 is automatically formed up to the gate oxide film 111. As a result, since there is no source for silicon (Si) in the gate, an off transistor having a thick gate oxide film 111 can be formed.

본 발명의 바람직한 실시예에 따르면, 산소 이온주입은 4회에 걸쳐서 멀티 레벨(multi-level)로 진행한다. 즉, N-폴리(106)를 1500 Å 정도의 두께로 형성함으로 4 V이상의 Vt를 만들기 위해서는 800 Å의 산화막 두께가 필요하므로 산소 이온주입시 130 KeV, 110 KeV, 90 KeV, 70 KeV로 차별화하여 이온 주입을 하여 두껍게 산화될 수 있도록 한다.According to a preferred embodiment of the present invention, oxygen ion implantation proceeds multi-level four times. That is, the oxide film thickness of 800 kW is required to form Vt of 4 V or more by forming the N-poly 106 to a thickness of about 1500 kPa, so that oxygen ion implantation is differentiated into 130 KeV, 110 KeV, 90 KeV, and 70 KeV. Ion implantation allows for thick oxidation.

도 2는 본 발명의 바람직한 실시예에 따라 형성된 오프 트랜지스터와 온 트랜지스터를 나타내기 위한 단면도이다. 2 is a cross-sectional view illustrating an off transistor and an on transistor formed according to a preferred embodiment of the present invention.

도 2에 도시한 바와 같이, 본 발명의 바람직한 실시예에 따르면, 온 트랜지스터(Ton) 영역에서 형성된 게이트 산화막(111B)은 대략 68 Å 정도의 두께이며, 오프 트랜지스터(Toff) 영역에 형성된 게이트 산화막(111A)은 대략 800 Å 정도의 두께로 형성하였다. As shown in FIG. 2, according to a preferred embodiment of the present invention, the gate oxide film 111B formed in the on transistor (Ton) region has a thickness of about 68 kW, and the gate oxide film formed in the off transistor (Toff) region ( 111A) was formed to a thickness of approximately 800 mm 3.

또한, 도 3은 본 발명의 바람직한 실시예에 따라 형성된 마스크롬 셀 트랜지스터의 레이아웃을 도시한다. 3 shows a layout of a mask ROM cell transistor formed in accordance with a preferred embodiment of the present invention.

본 발명을 본 명세서 내에서 몇몇 바람직한 실시예에 따라 기술하였으나, 당업자라면 첨부한 특허 청구 범위에서 개시된 본 발명의 진정한 범주 및 사상으로부터 벗어나지 않고 많은 변형 및 향상이 이루어질 수 있다는 것을 알 수 있을 것이다.
While the invention has been described in accordance with some preferred embodiments herein, those skilled in the art will recognize that many modifications and improvements can be made without departing from the true scope and spirit of the invention as set forth in the appended claims.

상기한 바와 같이, 종래의 기술은 높은 Vt를 만들기 위하여 NMOS에 대하여 보론을 이온주입 하였으나, 이에 나타나는 문제점은 보론이 후속 열처리에 의하여 원자량이 작기 때문에 확산 현상이 심하여 온 트랜지스터 영역까지 확산하여 온 트랜지스터의 Vt를 상승시키고 전류를 감소시켜 칩에서의 속도나 센싱 마진에 문제를 일으키지만, 본 발명은 산소를 폴리 내에 이온 주입을 함에 따라 온 트랜지스터의 Vt 상승을 막을 수 있는 효과가 있다. As described above, the conventional technique has ion implanted boron with respect to the NMOS to make a high Vt, but the problem is that the boron has a small atomic weight by the subsequent heat treatment, so the diffusion phenomenon is severe, so that the diffusion of the transistor to the on transistor region Increasing Vt and decreasing current cause problems in speed or sensing margin in the chip. However, the present invention has the effect of preventing the on transistor from increasing Vt by implanting oxygen into the poly.

또한, 보론 이온주입이 게이트 산화막을 뚫고 지나 채널 영역에 침투하여 게이트 산화막의 누설(leakage) 문제를 유발하고 있으며 전체적으로 칩의 신뢰성을 야기시키는데 본 발명은 이러한 문제점을 개선시킬 수 있다. In addition, boron ion implantation penetrates through the gate oxide layer and penetrates into the channel region, causing leakage of the gate oxide layer and causing chip reliability as a whole, and the present invention can improve this problem.

Claims (5)

실리콘 기판 상에 BN+ 층을 형성한 후, 그 위에 BN+ 산화막을 형성하는 단계와, Forming a BN + layer on the silicon substrate, and then forming a BN + oxide film thereon; N-폴리층 및 텅스텐 실리사이드층을 순차적으로 형성하여 상기 N-폴리층 및 텅스텐 실리사이드층으로 이루어진 게이트를 형성하는 단계와, Sequentially forming an N-poly layer and a tungsten silicide layer to form a gate composed of the N-poly layer and tungsten silicide layer; 오프 트랜지스터를 만들 영역에 대해 마스킹 층으로 포토레지스터를 이용하여 상기 오프 트랜지스터 영역에 산소를 이온주입하여 이온 주입된 산소와 폴리가 후에 가해지는 열에 의하여 산화막을 형성하는 단계를Ion implanting oxygen into the off-transistor region using a photoresist as a masking layer for the region where the off-transistor is to be formed, and forming an oxide film by heat applied after ion-implanted oxygen and poly 포함하는 것을 특징으로 하는 마스크롬 셀 트랜지스터 제조방법. Method of manufacturing a mask rom cell transistor comprising a. 제 1항에 있어서, 상기 형성된 산화막이 게이트 산화막 위에까지 자동으로 형성되는 것을 특징으로 하는 마스크롬 셀 트랜지스터 제조방법. The method of claim 1, wherein the formed oxide film is automatically formed on the gate oxide film. 제 1항에 있어서, 상기 게이트에는 실리콘(Si)에 대한 소오스가 없으므로 두꺼운 게이트 산화막을 형성한 오프 트랜지스터를 형성할 수 있는 것을 특징으로 하는 마스크롬 셀 트랜지스터 제조방법. The method of claim 1, wherein an off-transistor having a thick gate oxide layer is formed because the gate does not have a source for silicon (Si). 제 1항에 있어서, 상기 산소 이온주입은 4회에 걸쳐서 멀티 레벨(multi-level)로 진행하는 것을 특징으로 하는 마스크롬 셀 트랜지스터 제조방법. The method of claim 1, wherein the oxygen ion implantation is performed in a multi-level four times. 제 1항에 있어서, 상기 N-폴리를 1500 Å 정도의 두께로 형성함으로 4 V이상의 Vt를 만들기 위해서는 800 Å의 산화막 두께가 필요하므로 산소 이온주입시 130 KeV, 110 KeV, 90 KeV, 70 KeV로 차별화하여 이온 주입을 하여 두껍게 산화될 수 있도록 하는 것을 특징으로 하는 마스크롬 셀 트랜지스터 제조방법. According to claim 1, wherein the N-poly is formed to a thickness of about 1500 kW to form a Vt of 4 V or more, 800 kV oxide film thickness is required to produce 130 KeV, 110 KeV, 90 KeV, 70 KeV in oxygen ion implantation. Method of manufacturing a mask rom cell transistor, characterized in that to be oxidized thickly by implantation by differentiation.
KR1020030051655A 2003-07-25 2003-07-25 METHOD FOR MANUFACTURING MaskROM CELL TRANSISTOR KR101025920B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020030051655A KR101025920B1 (en) 2003-07-25 2003-07-25 METHOD FOR MANUFACTURING MaskROM CELL TRANSISTOR

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020030051655A KR101025920B1 (en) 2003-07-25 2003-07-25 METHOD FOR MANUFACTURING MaskROM CELL TRANSISTOR

Publications (2)

Publication Number Publication Date
KR20050012953A KR20050012953A (en) 2005-02-02
KR101025920B1 true KR101025920B1 (en) 2011-03-30

Family

ID=37224690

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020030051655A KR101025920B1 (en) 2003-07-25 2003-07-25 METHOD FOR MANUFACTURING MaskROM CELL TRANSISTOR

Country Status (1)

Country Link
KR (1) KR101025920B1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970011668B1 (en) * 1993-12-07 1997-07-14 Lg Semicon Co Ltd A mask rom device and a method for fabricating the same
KR19990048490A (en) * 1997-12-10 1999-07-05 구본준 ROM manufacturing method of semiconductor device
KR20010004266A (en) * 1999-06-28 2001-01-15 김영환 Method of forming a self aligned source in a flash EEPROM cell
KR20020018879A (en) * 2000-09-04 2002-03-09 박종섭 Method for manufacturing semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970011668B1 (en) * 1993-12-07 1997-07-14 Lg Semicon Co Ltd A mask rom device and a method for fabricating the same
KR19990048490A (en) * 1997-12-10 1999-07-05 구본준 ROM manufacturing method of semiconductor device
KR20010004266A (en) * 1999-06-28 2001-01-15 김영환 Method of forming a self aligned source in a flash EEPROM cell
KR20020018879A (en) * 2000-09-04 2002-03-09 박종섭 Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
KR20050012953A (en) 2005-02-02

Similar Documents

Publication Publication Date Title
US5943595A (en) Method for manufacturing a semiconductor device having a triple-well structure
KR100277873B1 (en) Manufacturing Method of Semiconductor Device
KR970018223A (en) Manufacturing Method of Semiconductor Integrated Circuit
KR101025920B1 (en) METHOD FOR MANUFACTURING MaskROM CELL TRANSISTOR
US20070114604A1 (en) Double-extension formation using offset spacer
KR20070001732A (en) Method of manufacturing a semiconductor device using gate-through ion implantation
KR100253569B1 (en) Manufacture of semiconductor device
KR20040022373A (en) Semiconductor device and method of manufacturing the same
JPS62265765A (en) Semiconductor device and manufacture thereof
KR100731105B1 (en) Method for manufacturing mos transistor
KR100929422B1 (en) Manufacturing method of semiconductor device
JP2007318073A (en) Method for manufacturing flash memory element
KR20010027157A (en) Method for manufacturing semiconductor device
JPH11121394A (en) Method of manufacturing semiconductor device
KR100214535B1 (en) Method for fabricating ldd mosfet
KR100318274B1 (en) Method of manufacturing semiconductor device
KR100487504B1 (en) A method of forming different gate spacers
KR960009015A (en) Gate electrode formation method of semiconductor device
KR20000027654A (en) Method for fabricating semiconductor devices
KR100811456B1 (en) Manufacturing method of semiconductor device
KR950012717A (en) Semiconductor device manufacturing method
JPS63164313A (en) Manufacture of semiconductor device
KR20030002660A (en) Manufacturing method for semiconductor device
KR20050070252A (en) Method for fabricating semiconductor device
KR20060076369A (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
N231 Notification of change of applicant
A201 Request for examination
E902 Notification of reason for refusal
E90F Notification of reason for final refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20140218

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20150223

Year of fee payment: 5

FPAY Annual fee payment

Payment date: 20160219

Year of fee payment: 6

FPAY Annual fee payment

Payment date: 20170216

Year of fee payment: 7

FPAY Annual fee payment

Payment date: 20180221

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20190218

Year of fee payment: 9

FPAY Annual fee payment

Payment date: 20200218

Year of fee payment: 10