KR101024172B1 - Non volatile memory device and program method thereof - Google Patents

Abstract

PURPOSE: A non volatile memory device and a program method thereof are provided to improve the reliability of a program operation by preventing the threshold voltage of a memory cell from rising. CONSTITUTION: In a non volatile memory device and a program method thereof, a program pulse is raised to a constants step level(S03). A first program operation is performed(S01). The first program operation is performed untie the threshold voltage of at least one memory cell is reached to a target level. It is determined whether threshold voltage of at least one memory cell is reached to the target level or not(S02). If the threshold voltage of at least one memory cell is reached to the target level, the program pulse is raised to a second step level lower than a first step level(S05). A second program operation is performed until the threshold voltage of all selected memory cells is reached to the target level(S06).

Description

Non-volatile memory device and program method thereof

The present invention relates to a nonvolatile memory device and a program method thereof, and more particularly, to a nonvolatile memory device and a program method thereof for narrowing the threshold voltage distribution of programmed cells.

Among the program methods of the nonvolatile memory device, an incremental step pulse program (ISPP) method is described as follows.

A program pulse is applied to the selected word line to increase the threshold voltage of the selected memory cells. In this case, the memory cells to be programmed and the memory cells not to be programmed may be distinguished by discharging or precharging the bit lines. After the program pulse is applied, a verification operation for determining whether the threshold voltages of the selected memory cells has reached the target voltage is performed. If the threshold voltages of all selected memory cells do not reach the target voltage, that is, if at least one memory cell has not reached the target voltage, the program pulse is raised by the level of the first step pulse to perform a program operation. do.

The above-described program operation and verification operation are repeatedly performed until the threshold voltages of all selected memory cells reach the target voltages.

On the other hand, the larger the level of the first step pulse, that is, the larger the program pulse rise rate, the shorter the program operation time. However, since the threshold voltage rise rate of the memory cells also increases, the distribution of threshold voltages of the selected memory cells can be widened. .

An object of the present invention is to provide a nonvolatile memory device and a program method thereof for preventing the threshold voltage distribution of memory cells from increasing.

The program method of a nonvolatile memory device according to the present invention performs a first program operation while raising a program pulse to a constant step level until a threshold voltage of at least one or more of the selected memory cells reaches a target voltage. . If the threshold voltages of at least one memory cell among the selected memory cells reach the target voltage, the second program is raised while raising the program pulse to a step level lower than the step level until all threshold voltages of the selected memory cells reach the target voltage. A method of programming a nonvolatile memory device comprising performing an operation.

In the first program operation, after applying the program pulse, determining whether the threshold voltage of at least one or more of the selected memory cells has reached the target voltage.

In the second program operation, after applying the program pulse, determining whether the threshold voltages of the selected memory cells have reached the target voltage.

A nonvolatile memory device according to the present invention includes a memory cell array including a plurality of memory cell blocks. And a voltage generator configured to generate driving voltages according to the driving signals and the pass signal. And a block switch transferring driving voltages to selected memory cell blocks among the memory cell blocks. Page buffers for inputting and outputting data of memory cell blocks. And a data determination circuit that determines whether to program the selected memory cells with data input to the page buffers and outputs a plurality of verification signals. A nonvolatile memory device includes a pass signal output circuit for generating a pass signal according to verification signals.

The data determination circuit outputs a low verification signal when threshold voltages of selected memory cells do not reach a target voltage during a program operation, and verifies high when threshold voltages of selected memory cells reach a target voltage. Output the signal.

The pass signal output circuit outputs the pass signal high when the threshold voltages of the selected memory cells do not reach the target voltage during the program operation, and the threshold voltage of at least one of the selected memory cells is at the target voltage. When it reaches, the pass signal is output low.

The voltage generator sets the rising voltage of the program pulse to the first step pulse when the pass signal is high, and sets the rising voltage of the program pulse to the second step pulse lower than the first step pulse when the pass signal is low. Set it.

According to the present invention, it is possible to prevent the threshold voltage distribution of the memory cells from increasing, thereby improving the reliability of the program operation.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided for complete information.

1 is a flowchart illustrating a program method according to the present invention.

The program operation is performed by an incremental step pulse program (ISPP) method.

When the program starts, a program pulse is applied to the selected word line to perform a first program operation for raising threshold voltages of the selected memory cells (step S01). In this case, the memory cells to be programmed and the memory cells not to be programmed may be distinguished by discharging or precharging the bit lines. After the program pulse is applied, it is verified whether at least one or more memory cells whose threshold voltage reaches the target voltage among the selected memory cells are verified (step S02). In detail, since the selected memory cells may have different programmed speeds, the time at which the threshold voltage rises may also be different. Therefore, even when the same program pulse is applied, a memory cell that is programmed at a high speed may reach a target voltage faster than other memory cells. In this case, as the number of memory cells having a high operating speed increases, threshold voltages of a plurality of memory cells may simultaneously reach a target voltage.

If none of the memory cells has reached the target voltage, the program pulse is increased by the first step pulse (step S03), and the first program operation is performed again (step S01). Steps S01 through S03 are repeated until at least one of the selected memory cells reaches a target voltage.

If the threshold voltages of at least one memory cell among the selected memory cells reach the target voltage, it may be assumed that the threshold voltages of the selected memory cells are close to the target voltage from this point on.

It is verified whether the threshold voltages of all selected cells have reached the target voltage (step S04). If there are memory cells that do not reach the target voltage among the selected memory cells, the program pulse is increased by the second step pulse lower than the first step pulse (step S05) to perform the second program operation (step S06). That is, if the threshold voltages of at least one or more memory cells of the selected memory cells reach the target voltage, the threshold voltages of the other memory cells may also be considered to have risen to the vicinity of the target voltage. Lower to perform program operation. For example, if the first step pulse is 300 Hz, the second step pulse may be set to 200 Hz, which is lower than the first step pulse. After raising the program pulse by the second step pulse, steps S04 to S06 are repeatedly performed until the threshold voltages of all the selected memory cells reach the target voltage.

Meanwhile, in order to perform the above-described program operation, a nonvolatile memory device which verifies selected memory cells in units of 1 bit and thus lowers a rising rate of a program pulse should be provided.

2 is a block diagram of a nonvolatile memory device according to the present invention.

The nonvolatile memory device according to the present invention includes a controller 100, a voltage generator 110, a block switch 120, a memory cell array 130, a page buffer unit 140, a data determination circuit 150, and a path. And a signal output circuit 160.

The controller 100 outputs various driving signals COM according to the address ADD. The voltage generator 110 transfers the driving voltages to the global word lines GWL according to the driving signals COM and the pass signal PBD_PASS. For example, the driving voltages include a program pulse, a pass voltage, an erase voltage, a read voltage, or a verify voltage.

The block switch 120 transfers the driving voltages to the word lines WL of the selected memory block. The memory cell array 130 includes a plurality of memory cells in which data is stored.

The page buffer unit 140 includes a plurality of page buffers PBs and performs an input / output operation of data through an input / output line IO. Each page buffer may be connected in pairs with two bit lines.

The data determination circuit 150 is connected to the page buffers PB included in the page buffer unit 140 through different data lines DL. In particular, the data determination circuit 150 receives data input to the respective page buffers PB through the data lines DL, determines whether the threshold voltage of the corresponding memory cell reaches the target voltage, and provides a plurality of verification signals. Outputs the PBDs. For example, when the threshold voltage of the corresponding memory cell does not reach the target voltage, a low verify signal PBD is output. When the threshold voltage reaches the target voltage, a high verify signal PBD is output. ) Is output.

The pass signal output circuit 160 outputs the pass signal PBD_PASS according to the verification signals PBD. Specifically, when all of the verification signals PBD are applied low, the pass signal output circuit 160 outputs a high pass signal PBD_PASS. If at least one verification signal of the verification signals PBD is output high, the path signal output circuit 160 outputs a low path signal PBD_PASS.

Referring to FIGS. 2 and 3, the program operation according to the pass signal PBD_PASS will be described.

3 is a view for explaining a program method according to the present invention.

2 and 3, in a program operation, when the pass signal PBD_PASS is high, the voltage generator 110 transfers typical driving voltages to the global word lines GWL. For example, a program pulse Vpgm, a program pass voltage, and a verification voltage Vr required for a program operation are generated, and when the program pulse Vpgm is raised, the program pulse Vpgm is raised by the level of the first step pulse SP1. . That is, when the pass signal PBD_PASS is high, the program operation and the verification operation are performed while raising the program pulse Vpgm by the first step pulse SP1.

However, when the pass signal PBD_PASS transitions low, the threshold voltage may be the case where at least one memory cell exists in the target voltage, and thus the program pulse Vpgm is lower than the first step pulse SP1. The program operation and the verification operation are performed while increasing by the second step pulse SP2.

As described above, since the difference between the threshold voltage and the target voltage is large at the beginning of the program operation, the program operation is performed by increasing the rising rate of the program pulse. However, when at least one memory cell at which the threshold voltage reaches the target voltage is generated, this becomes a state in which the difference between the threshold voltages and the target voltage is reduced, and hence the program operation is performed by decreasing the rising rate of the program pulse.

That is, since the threshold voltage of a cell having a high program operation speed increases as the rate of increase of the program pulse increases, it is possible to suppress the increase of the threshold voltage of cells having a high program operation speed by lowering the upper pulse rate of the program pulse. Accordingly, the threshold voltage distribution of the selected memory cells can be programmed to be narrowed.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a flowchart illustrating a program method according to the present invention.

2 is a block diagram of a nonvolatile memory device according to the present invention.

3 is a view for explaining a program method according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100: control unit 110: voltage generating unit

120: block switch 130: memory cell array

140: page buffer unit 150: data determination circuit

160: pass signal output circuit

Claims (7)

Performing a first program operation while raising a program pulse to a constant step level until the threshold voltage of at least one memory cell among the selected memory cells reaches a target voltage; And When the threshold voltages of at least one memory cell among the selected memory cells reach the target voltage, the program pulse is set to a step level lower than the step level until all threshold voltages of the selected memory cells reach the target voltage. And performing a second program operation while rising. The method of claim 1, And determining whether a threshold voltage of at least one of the selected memory cells reaches the target voltage after applying the program pulse in the first program operation. The method of claim 1, And in the second program operation, after applying the program pulse, determining whether the threshold voltages of the selected memory cells have reached the target voltage. A memory cell array including a plurality of memory cell blocks; A voltage generator configured to generate driving voltages according to the driving signals and the pass signal; A block switch transferring the driving voltages to a selected memory cell block among the memory cell blocks; Page buffers for inputting and outputting data of the memory cell blocks; A data determination circuit that determines whether to program selected memory cells with data input to the page buffers and outputs a plurality of verification signals; And And a pass signal output circuit configured to generate the pass signal according to the verification signals. The method of claim 4, wherein The data determination circuit outputs the verification signal low when the threshold voltages of the selected memory cells do not reach the target voltage during a program operation, and high when the threshold voltages of the selected memory cells reach the target voltage. A nonvolatile memory device for outputting the verification signal of high. The method of claim 4, wherein The pass signal output circuit outputs the pass signal high when all threshold voltages of the selected memory cells do not reach a target voltage during a program operation, and threshold voltages of at least one of the selected memory cells. And outputting the pass signal low when the target voltage is reached. The method of claim 4, wherein The voltage generator sets the rising voltage of the program pulse to the first step pulse when the pass signal is high, and sets the rising voltage of the program pulse to be lower than the first step pulse when the pass signal is low. A nonvolatile memory device configured to set the second step pulse.

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