KR101023127B1 - Thin Film Transistor, The method for Using The Same and Organic Light Emitting Display Device Comprising the TFT - Google Patents

Abstract

The present invention relates to a thin film transistor, a method for manufacturing the same, and an organic light emitting display device having the same, comprising: a substrate including a pixel portion and a peripheral portion; A buffer layer on the substrate; A semiconductor layer on the buffer layer and corresponding to the pixel portion; A gate insulating layer on the semiconductor layer; A gate electrode insulated from the semiconductor layer and positioned on the gate insulating layer; And a source / drain electrode insulated from the gate electrode and electrically connected to the semiconductor layer through a contact hole, wherein a region corresponding to the contact hole of the semiconductor layer is an impurity doped region. A thin film transistor, a manufacturing method thereof, and an organic light emitting display device having the same are provided.

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Description

Thin Film Transistor, The method for Using The Same and Organic Light Emitting Display Device Comprising the TFT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, a method for manufacturing the same, and an organic light emitting display device including the same, wherein the generation of arcs during crystallization by joule heating using a conventional electric field application using a metal for a gate electrode is provided. It provides a way to minimize the defect of the device and improve the production yield.

Generally, there are various heat treatment methods such as furnace annealing using a heat treatment furnace, rapid thermal annealing using radiant heat such as halogen lamps, laser annealing using laser, and heat treatment using joule heating. Do. These heat treatment methods are selected according to the characteristics of the material and process by the temperature range of the heat treatment, the uniformity of the heat treatment temperature, the temperature increase rate, the cooling rate, the purchase price, the maintenance cost. In particular, when a high temperature heat treatment is required or a high speed heat treatment is required in a local region of a material and a specific phase of a process, the heat treatment method that can be selected is extremely limited.

Of the above heat treatment methods, the laser annealing method is capable of rapid heat treatment on the surface of the material, but the material that can be heat-treated is limited because the availability of heat treatment is determined according to the wavelength of the laser and the type of material to be heat-treated. . In particular, when heat-treating a large area, it is necessary to superimpose and scan the line beam type laser, thereby causing problems such as nonuniformity of laser beam intensity and nonuniformity of irradiation dose over time of the laser beam itself. In addition, the cost of the equipment as well as the maintenance costs are very expensive.

The RTA method is widely used in the semiconductor manufacturing process, but is currently applicable only to a 300 mm diameter silicon wafer, and there is still a limit to uniformly heat treating a wider substrate. In addition, the maximum temperature increase rate of the heat treatment is 400 ° C / sec, it can not be used in a process that requires a higher temperature increase rate.

Therefore, many studies have been conducted on a heat treatment method that solves the above problems and can be free from process constraints. Among them, there is a rapid heat treatment method in which a joule is heated by applying an electric field to a conductive layer, and this heat treatment method is characterized by The heat conduction allows for selective rapid heat treatment of the desired material, and much higher heating rates can be expected than the heating rates of the RTA process.

However, in the heat treatment methods using joule heating by applying an electric field as described above, there is a problem in that a defect caused by physical phenomenon such as an arc generated during joule heating cannot be solved.

SUMMARY OF THE INVENTION The present invention provides a thin film transistor comprising a semiconductor layer crystallized by electric field application using an electrode metal used in an element, a method of manufacturing the same, and an organic electroluminescence display device comprising the same, and according to the related art, To solve the arc problem that occurs during the crystallization of the amorphous silicon layer. In addition, the purpose is to simplify the process by reducing the mask.

The present invention relates to a thin film transistor, a method for manufacturing the same, and an organic light emitting display device having the same, comprising: a substrate including a pixel portion and a peripheral portion; A buffer layer on the substrate; A semiconductor layer on the buffer layer and corresponding to the pixel portion; A gate insulating layer on the semiconductor layer; A gate electrode insulated from the semiconductor layer and positioned on the gate insulating layer; And a source / drain electrode insulated from the gate electrode and electrically connected to the semiconductor layer through a contact hole, wherein a region corresponding to the contact hole of the semiconductor layer is an impurity doped region. A thin film transistor, a manufacturing method thereof, and an organic light emitting display device having the same are provided.

In the present invention, when the electrode is formed, an amorphous silicon layer is crystallized into a polysilicon layer by applying an electric field to a thin film for a gate electrode to be used, thereby producing polysilicon layer produced by conventional joule heating. The problem of the arc can be solved. By using the contact hole necessary for crystallization using the mask used for the doping of the semiconductor layer, the process can be simplified, and the overall effect can be reduced and the yield can be improved. have.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms.

(Example)

1A to 1G are views of a thin film transistor according to an embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 including a pixel portion a and a peripheral portion b is prepared, and a buffer layer 110 is formed on the substrate 100. The substrate 100 may be glass, plastic, or the like, and the buffer layer 110 may prevent diffusion of moisture or impurities generated from the substrate 100 or may control heat transfer rate during crystallization, thereby crystallizing the amorphous silicon layer. May be formed to be well formed, and may be formed as a single layer or a plurality of layers thereof by using an insulating film such as a silicon oxide film or a silicon nitride film.

Thereafter, an amorphous silicon layer pattern 120P is formed on the buffer layer 110.

Referring to FIG. 1B, an impurity doping is performed on the amorphous silicon layer pattern 120P by using a first mask A. Referring to FIG. In this case, the doped region 120a of the amorphous silicon layer pattern 120P belongs to a source / drain region in the region when the semiconductor layer is later formed, and the impurity doping may use P-type or N-type impurities.

Referring to FIG. 1C, a gate insulating film 130 is formed over the entire surface of the substrate 100, and the gate insulating film is formed using the same first mask A used when ion doping the amorphous silicon layer pattern 120P. A contact hole 130C is formed in 130. Therefore, the doped region 120a of the amorphous silicon layer pattern 120P is exposed by the contact hole 130C.

Referring to FIG. 1D, the gate electrode metal film 140a is formed over the entire surface of the substrate 100 formed as described above. The gate electrode metal layer 140a may be a single layer of an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd), or may be a multilayer in which an aluminum alloy is laminated on a chromium (Cr) or molybdenum (Mo) alloy. The gate electrode metal layer 140a may have a thickness of a general gate electrode, but is preferably 50 to 200 nm. The reason for this is that when the thickness is smaller than 50 nm, the gate electrode metal film 140a is formed unevenly, so that the heat conduction is not uniform in the amorphous silicon layer, resulting in uneven crystallization. This is because a thickness of 200 nm or less is sufficient to serve as an electrode and is suitable as a thin film element.

Subsequently, the semiconductor layer 120 is formed by crystallizing the amorphous silicon layer pattern 120P into a polysilicon layer (not shown) by applying an electric field to the gate electrode metal layer 140a by joule heating. .

Since the gate electrode metal film 140a is conductive, it is heated when an electric field is applied, and heat of the gate electrode metal film 140a is transferred to the amorphous silicon layer pattern 120P to proceed with crystallization. . At this time, in order to proceed with crystallization preferably, about 100 to 10000V / cm 2 is added for 1 kPa to 1 sec. The reason is that an electric field below 100 V produces Joule heat which is insufficient for crystallization, and an electric field above 10000 V generates a local arc. If the electric field is applied below 1㎲, crystallization is difficult to proceed due to insufficient Joule heating, and if it is applied for more than 1sec, the substrate may be bent or the crystallization defect of the edge due to heat conduction may adversely affect the device. .

In addition, in the present invention, the gate electrode metal layer 140a is in direct contact with the amorphous silicon layer pattern 120P through the contact hole 130c, thereby generating an arc generated when the amorphous silicon layer is crystallized by the conductive heat of the metal layer. It is effective in reducing defects.

Subsequently, referring to FIG. 1E, the gate electrode metal layer 140c is patterned to form the gate electrode 140 positioned in the pixel portion a of the substrate 100 and the metal pattern positioned in the peripheral portion b. 140c). The gate electrode 140 is positioned to correspond to the upper portion of the channel region 120c of the semiconductor layer 120, and the doped semiconductor layer region 120a is the source / drain regions 120s and 120d of the semiconductor layer 120. The metal pattern 140c is then used as an alignment mark.

Afterwards, referring to FIG. 1F, an interlayer insulating layer 150 is positioned over the entire surface of the substrate 100 including the gate electrode 140. The interlayer insulating layer 150 may be a silicon nitride film, a silicon oxide film, or a multilayer thereof.

Then, referring to FIG. 1G, after forming the interlayer insulating layer 150 as described above, the interlayer insulating layer 150 is etched to form source / drain electrodes 160a and 160b connected to the semiconductor layer 120. do.

The source / drain electrodes 160a and 160b may include molybdenum (Mo), chromium (Cr), tungsten (W), molybdenum tungsten (MoW), aluminum (Al), aluminum-neodymium (Al-Nd), and titanium ( Ti, titanium nitride (TiN), copper (Cu), molybdenum alloy (Mo alloy), aluminum alloy (Al alloy), and copper alloy (Cu alloy) may be formed of any one selected from. This completes the thin film transistor according to the embodiment of the present invention.

2 is a cross-sectional view of an organic light emitting display device including a thin film transistor according to an embodiment of the present invention.

Referring to FIG. 2, an insulating film 170 is formed on the entire surface of the substrate 100 including the thin film transistor according to the embodiment of FIGS. 1A to 1G. The insulating film 170 may be any one selected from an inorganic film, a silicon oxide film, a silicon nitride film, or a silicide on glass, or an organic film, polyimide, benzocyclobutene series resin, or acrylate. It may be formed of any one selected from. It may also be formed by a laminated structure of the inorganic film and the organic film.

The insulating layer 170 is etched to form via holes (not shown) that expose the source / drain electrodes 160a and 160b. A first electrode 180 connected to any one of the source / drain electrodes 160a and 160b is formed through the via hole. The first electrode 180 may be formed as an anode or a cathode. When the first electrode 180 is an anode, the anode may be formed of a transparent conductive film made of any one of ITO, IZO, or ITZO, and in the case of a cathode, the cathode may be Mg, Ca, Al, Ag, Ba, or these. It can be formed using an alloy of.

Subsequently, a pixel definition layer 230 having an opening that exposes a portion of the surface of the first electrode 220 is formed on the first electrode 180, and a light emitting layer is formed on the exposed first electrode 180. An organic film layer 190 is formed. The organic layer 190 may further include one or more layers selected from the group consisting of a hole injection layer, a hole transport layer, a hole suppression layer, an electron suppression layer, an electron injection layer and an electron transport layer. Subsequently, a second electrode 195 is formed on the organic layer 190. This completes the organic light emitting display device according to the embodiment of the present invention.

1A to 1G are views of a thin film transistor according to the present invention.

2 is a diagram of an organic light emitting display device according to an exemplary embodiment of the present invention.

Claims (12)

A substrate including a pixel portion and a peripheral portion; A buffer layer on the substrate; A semiconductor layer on the buffer layer and corresponding to the pixel portion; A gate insulating layer on the semiconductor layer; A gate electrode insulated from the semiconductor layer and positioned on the gate insulating layer; And And a source / drain electrode insulated from the gate electrode and electrically connected to the semiconductor layer through the contact hole, wherein a region corresponding to the contact hole of the semiconductor layer is an impurity doped region. , The thickness of the gate electrode is a thin film transistor of 50nm to 200nm. The method of claim 1, The impurity doped region is a thin film transistor, characterized in that it comprises a P-type or N-type impurities. The method of claim 1, The thin film transistor according to claim 1, wherein an alignment mark made of the same material as that of the gate electrode is positioned at the periphery of the substrate. The method of claim 1, The gate electrode is a thin film transistor, characterized in that the single layer or multiple layers made of any one of aluminum (Al), chromium (Cr) -aluminum alloy or molybdenum (Mo) -aluminum alloy. Providing a substrate on which the pixel portion and the peripheral portion are located, Forming a buffer layer on the substrate, Located on the buffer layer, to form an amorphous silicon layer pattern corresponding to the pixel portion, Doping a portion of the amorphous silicon layer pattern using a first mask to form a doped region in the amorphous silicon layer pattern, Forming a gate insulating film on the substrate, Forming a contact hole on the gate insulating layer using a first mask to expose the doped region of the amorphous silicon layer pattern, Forming a metal film for a gate electrode on the substrate; Applying an electric field to the metal film for the gate electrode to crystallize the amorphous silicon layer pattern to form a semiconductor layer, Patterning the gate electrode metal to form a gate electrode positioned in a pixel portion of the substrate and corresponding to the semiconductor layer, An interlayer insulating film is formed on the substrate, And forming a source / drain electrode to which the semiconductor layer is partially connected. The method of claim 5, When patterning the metal film for the electrode, a method of manufacturing a thin film transistor, characterized in that to form a metal pattern on the periphery of the substrate. The method of claim 5, The applying of the electric field to the metal film for the gate electrode is performed after the gate electrode metal film and the amorphous silicon layer pattern is a part in direct contact with each other. The method of claim 5, And a region in which the gate electrode metal film is in contact with the amorphous silicon layer is a doped region of the amorphous silicon layer. A substrate including a pixel portion and a peripheral portion; A buffer layer on the substrate; A semiconductor layer on the buffer layer and corresponding to the pixel portion; A gate insulating layer on the semiconductor layer; A gate electrode insulated from the semiconductor layer and positioned on the gate insulating layer; A source / drain electrode insulated from the gate electrode and electrically connected to the semiconductor layer through a contact hole; An insulating layer covering the source / drain electrodes; And A first electrode, an organic layer, and a second electrode on the insulating layer and electrically connected to the source / drain electrodes, wherein a region corresponding to the contact hole of the semiconductor layer is an impurity doped region. Features, The gate electrode has a thickness of 50nm to 200nm organic light emitting display device. The method of claim 9, And the impurity doped region includes a P-type or an N-type impurity. The method of claim 9, And an alignment mark made of the same material as that of the gate electrode. The method of claim 9, The gate electrode is an organic light emitting display device, characterized in that the single layer or multiple layers made of any one of aluminum (Al), chromium (Cr) -aluminum alloy or molybdenum (Mo) -aluminum alloy.

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