KR101018116B1 - Nitride Semiconductor Device and Manufacturing Method of The Same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nitride semiconductor device and a method of manufacturing the same, and an aspect of the present invention is formed on an n-type nitride semiconductor layer and the n-type nitride semiconductor layer, and propagates from a lower surface of the n-type nitride semiconductor layer to an upper surface thereof. An intermediate layer having a first pit formed at a position corresponding to the dislocation potential, an active layer having a second pit formed on the intermediate layer and formed at a position corresponding to the first pit, and at least a second pit of the active layer. Provided is a nitride semiconductor device including a high resistance region formed to partially fill and a p-type nitride semiconductor layer formed on the active layer.

According to the present invention, a nitride semiconductor element capable of improving luminous efficiency, reliability and process yield can be obtained by blocking the generation of leakage current by concentrating the current by defect regions such as potentials.

Nitride, LEDs, Leakage Current, Feet, High Resistance Area

Description

Nitride semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nitride semiconductor device and a method of manufacturing the same. In particular, a nitride semiconductor light emitting device capable of improving luminous efficiency, reliability, and process yield by blocking the generation of leakage current by concentrating current by defect regions such as potentials. An element and a method of manufacturing the same.

In general, nitride semiconductors are widely used in green or blue light emitting diodes (LEDs) or laser diodes (LDs), which are provided as light sources in full-color displays, image scanners, various signal systems, and optical communication devices. Such a nitride semiconductor device can be provided as a light emitting device having an active layer emitting a variety of light, including blue and green using the recombination principle of electrons and holes.

After such a nitride light emitting device (LED) has been developed, many technological advances have been made, and the range of its use has been expanded, and thus, many studies have been conducted as general lighting and electric light sources. In particular, in the past, nitride light emitting devices have been mainly used as components applied to mobile products of low current / low power, but recently, their application ranges are gradually expanded to high current / high power fields.

1 is a side sectional view showing a general nitride semiconductor device. Referring to FIG. 1, a conventional nitride semiconductor device includes a sapphire substrate 10, an n-type nitride semiconductor layer 11, an active layer 12, and a p-type nitride semiconductor layer 13. Not shown separately. In this case, the potential D propagates in the n-type nitride semiconductor layer 11 due to the lattice constant difference from the sapphire substrate 10, and the active layer 12 corresponding to the position corresponding to the potential D is transferred to the n-type nitride semiconductor layer 11. The defect area 14 is formed.

In the defect region 14, the recombination efficiency of the carrier is significantly low, which corresponds to the non-luminescent coupling region 15 when viewed from the top. In addition, when a current is injected in such a state, the carrier is concentrated in the defect area 14 to generate a leakage current, resulting in a decrease in luminous efficiency. Accordingly, there is a need in the art for a method of improving the luminous efficiency and reliability by minimizing the influence of the potential D propagated therein.

The present invention is to solve the problems of the prior art, a nitride semiconductor device that can improve the luminous efficiency, reliability and process yield by blocking the generation of leakage current by concentrating the current by the defect region such as potential. The purpose is to provide. Another object of the present invention is to provide a manufacturing method which can easily obtain such a nitride semiconductor element.

In order to realize the above technical problem, an aspect of the present invention,

an intermediate layer having an n-type nitride semiconductor layer, a first pit formed on the n-type nitride semiconductor layer and formed at a position corresponding to a potential propagated from a lower surface of the n-type nitride semiconductor layer to an upper surface thereof; An active layer having a second pit formed at a position corresponding to the first pit, a high resistance region formed to at least partially fill the second pit of the active layer, and a p-type nitride semiconductor layer formed on the active layer Provided is a nitride semiconductor device.

In one embodiment of the present invention, the intermediate layer may be made of undoped GaN.

In one embodiment of the present invention, the size of the first pit on the upper surface of the intermediate layer may be 10 ~ 500nm.

In one embodiment of the present invention, the size of the second pit on the top surface of the active layer may be 10 ~ 200nm.

In one embodiment of the present invention, the first and second pits may have an inverted pyramid shape.

In one embodiment of the present invention, the second pit may be formed to a depth corresponding to a length at least greater than half the thickness of the active layer.

In one embodiment of the present invention, the second pit may be formed to extend through the active layer to the intermediate layer.

In one embodiment of the present invention, the high resistance region is formed in a range that does not fill all of the second pit, and the p-type nitride semiconductor layer is formed to fill the region except the high resistance region in the second pit. Can be.

In one embodiment of the present invention, the high resistance region may be formed of an undoped nitride semiconductor. Alternatively, the high resistance region may be made of SiC.

Another aspect of the invention,

Forming an n-type nitride semiconductor layer on the substrate, and an intermediate layer having a first pit formed on the n-type nitride semiconductor layer at a position corresponding to a potential propagated from a lower surface of the n-type nitride semiconductor layer to an upper surface thereof; Forming an active layer on the intermediate layer, etching a region corresponding to the position corresponding to the first pit in the active layer to form a second pit, and forming a second pit of the active layer It provides a nitride semiconductor device manufacturing method comprising the step of forming a high resistance region to fill at least a portion and the p-type nitride semiconductor layer on the active layer.

In one embodiment of the present invention, the first pit may be spontaneously formed during the growth of the intermediate layer. To this end, the growth temperature of the intermediate layer may be to 750 ~ 900 ℃.

In an embodiment of the present disclosure, the forming of the active layer may be performed such that a groove is formed at a position corresponding to the first pit in the active layer.

In an embodiment of the present disclosure, etching the position corresponding to the first pit in the active layer to form the second pit may be performed by in-situ etching. In this case, the in-situ etching may be performed in a gas atmosphere including one gas selected from the group consisting of H ₂ , N ₂ and NH ₃ .

According to the present invention, a nitride semiconductor element capable of improving luminous efficiency, reliability and process yield can be obtained by blocking the generation of leakage current by concentrating the current by defect regions such as potentials. In addition, according to the present invention, such a nitride semiconductor element can be easily manufactured.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. In addition, embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings are the same elements.

2 to 5 are process cross-sectional views illustrating a method of manufacturing a nitride semiconductor device according to one embodiment of the present invention.

First, as shown in FIG. 2, the n-type nitride semiconductor layer 102 and the intermediate layer 103 are formed on the nitride single crystal growth substrate 101, and the intermediate layer 103 has a first pit P1. To form. The substrate 101 is provided as a substrate for nitride single crystal growth, and in general, a sapphire substrate may be used. Sapphire substrates are hexagonal-Rhombo R3c symmetric crystals with lattice constants in the c-axis and a-axis directions of 13.001 Å and 4.758 각각, respectively, C (0001) plane, A (1120) plane, and R ( 1102) surface and the like. In this case, the C plane is mainly used as a nitride growth substrate because the C surface is relatively easy to grow and stable at high temperatures. Of course, therefore the decision of SiC, GaN, ZnO, MgAl ₂ O _4, MgO, LiAlO ₂ and LiGaO ₂ substrate or the like is also a nitride semiconductor single crystal use is possible and, furthermore, is grown on the substrate 101 made of the type It is also possible to grow a buffer layer for quality improvement, for example, an undoped GaN layer.

The n-type nitride semiconductor layer 102 is an n-type having an Al _x In _y Ga _(1-xy) N composition formula, where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and 0 ≦ x + y ≦ 1. Impurities may be made of a semiconductor material doped, and typically, GaN, AlGaN, InGaN. In the n-type nitride semiconductor layer 102, there is a potential D propagated from a lower surface to an upper surface. When the substrate 101 is made of a material having a different lattice constant from the substrate 101, the potential D density may increase. Can be. As described above, this potential D may be the cause of the non-luminescent coupling region and the current leakage path.

The intermediate layer 103 is intended to more effectively perform the selective etching of the active layer, as will be described later, it may be made of undoped GaN. In this case, when undoped, the semiconductor layer may be defined as not intentionally doped. On the other hand, when doped at a low concentration, the intermediate layer 103 may be doped with n-type impurities such as Si, where the low doping concentration is in the range of about 5 × 10 ¹⁶ to 5 × 10 ¹⁷ / cm 3. Can be.

The first pit P1 of the intermediate layer 103 is formed in a region corresponding to the potential D, and may be spontaneously formed during the growth of the intermediate layer 103. That is, when growing at a high temperature at a relatively high temperature of about 750 to 900 ° C., a V-shaped first pit P1 may be formed in a region where a defect is formed in the intermediate layer 103 such as a dislocation D. have. As such, the first pit P1 is naturally formed during the growth of the intermediate layer 103, so that the pit forming process does not need to be performed separately, but the present invention is not limited thereto. The etching process may be performed to form the first pit P1. In this case, the first pit P1 may have an inverted pyramid shape, and the size d1 may be about 10 to 500 nm. Here, the size d1 of the first pit P1 corresponds to the size on the upper surface of the intermediate layer 103, as shown in FIG. 2.

Next, as shown in FIG. 3, the active layer 104 is grown on the intermediate layer 103, but a groove is formed in a region corresponding to the first pit P1 to facilitate a subsequent etching process. Can be. The active layer 104 emits light having a predetermined energy by recombination of electrons and holes. Although not shown in detail, the active layer 104 has a multi-quantum well (MQW) structure in which quantum barrier layers and quantum well layers are alternately stacked. Can be.

Next, as shown in FIG. 4, the groove region of the active layer 104 is etched to form a second pit P2. In this case, a region corresponding to the potential D of the n-type nitride semiconductor layer 101 can be easily etched by the groove of the first pit P1 and the active layer 104. The second pit P2 may have an inverted pyramid shape like the first pit P1, and the size d2 may be about 10 to 200 nm. In this case, the second pit P2 corresponds to a space for forming a high-resistance material that prevents concentration of carriers, and in order to exert its function, the second pit P2 has a depth corresponding to a length greater than half the thickness of the active layer 103. Can be formed. In some cases, as shown in FIG. 4, it may be extended by coalescing with the first pit P1 of the intermediate layer 103, and further, passing through the intermediate layer 103 to the n-type nitride semiconductor layer 102. It may be extended (see FIG. 6). Meanwhile, in the case of the present etching step, the growth process of the nitride semiconductor may be continuously performed in an in-situ process. For this purpose, a gas such as H ₂ , N ₂ , NH ₃ , or the like may be used in the reaction chamber. It can be made to be the atmosphere of the combination gas of. This in-situ process eliminates the need to move the growing epi structure out of the reaction chamber, thereby increasing the efficiency of the process.

Next, as shown in FIG. 5, the second pit P2 is filled with a high resistance material to form a high resistance region 105, and then a p-type nitride semiconductor layer 106 is formed thereon. . After the formation of the p-type nitride semiconductor layer 106, n-type and p-type electrodes may be formed to complete the nitride semiconductor device, one example of which is illustrated in FIG. 6. The high resistance region 105 is an undoped nitride semiconductor, specifically, an undoped Al _x In _y Ga _(1-xy) N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), or alternatively, may be made of a material having a relatively high resistance such as SiC. However, considering that the active layer 104 is formed inside, it is most preferable to form the high resistance region 105 using the undoped nitride semiconductor of the same material. In this case, the n-type nitride semiconductor layer 102 ), The active layer 104 and the like can be used.

As the high resistance region 105 is formed inside the active layer 104, an effect of spreading a current around the high resistance region 105 is generated. In particular, the high resistance region 105 corresponds to the potential D. The formation of the leakage current can be suppressed by being formed at such a position. That is, in the present embodiment, instead of suppressing the occurrence of the conventional non-luminous coupling region, it is formed as a high resistance region, thereby increasing the ratio of carriers contributing to light emission, thereby improving luminous efficiency, and at the same time obtaining a current dispersion effect. To make it possible.

Meanwhile, in the present embodiment, an example in which the high resistance region 105 fills all of the second pits P2 of the active layer 104 has been described. However, as shown in FIG. It may be formed to fill only a portion of the second pit (P2) or the first pit (P1), and then, as shown in Figure 8, the p-type nitride semiconductor layer 106 is formed in the high resistance region 105 Less filled areas can be filled. By having the shape of the high resistance region 105 and the p-type nitride semiconductor layer 106 shown in Figs. 7 and 8, the lateral dispersion effect of the current can be further improved.

The p-type nitride semiconductor layer 106 formed on the active layer 104 has a composition formula of Al _x In _y Ga _(1-xy) N (where 0 ≦ x ≦ 1, 0, like the n-type nitride semiconductor layer 102). P-type impurities having ≦ y ≦ 1 and 0 ≦ x + y ≦ 1) may be formed of a semiconductor material doped with GaN, AlGaN, InGaN. On the other hand, in the present embodiment, the growth method of the nitride semiconductor layers may use a process such as MOCVD, HVPE and the like known in the art.

6 is a cross-sectional view showing a nitride semiconductor device manufactured by a manufacturing method according to an embodiment of the present invention. Referring to FIG. 6, the nitride semiconductor device 200 includes a substrate 201, an n-type nitride semiconductor layer 202, an intermediate layer 203, an active layer 204, and a p-type nitride semiconductor layer 206. The high resistance region 205 is formed to fill the pit structure of the active layer 204. The nitride semiconductor device 200 may be manufactured by the manufacturing method described above, and the high resistance region 205 extends to the n-type nitride semiconductor layer 202. Accordingly, in the nitride semiconductor device 200, as the region corresponding to the non-emissive coupling region is changed to the high resistance region 205, the current dispersion effect and the reliability may be improved. An n-type electrode 207a may be formed on an exposed surface of the n-type nitride semiconductor layer 202, and a p-type electrode 207b may be formed on an upper surface of the p-type nitride semiconductor layer 206. Although not shown, an ohmic contact layer made of a transparent electrode material or the like may be formed between the p-type nitride semiconductor layer 206 and the p-type electrode 207b.

In the present embodiment, the n-type and p-type electrodes 207a and 207b are exemplified in the horizontal nitride semiconductor device structure in which the n-type and p-type electrodes are disposed to face the same direction. It will be readily understood by one skilled in the art that the sapphire substrate can be applied to the case).

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is defined by the appended claims. Therefore, it will be apparent to those skilled in the art that various forms of substitution, modification, and alteration are possible without departing from the technical spirit of the present invention described in the claims, and the appended claims. Will belong to the technical spirit described in.

1 is a side sectional view showing a general nitride semiconductor device.

2 to 5 are process cross-sectional views illustrating a method of manufacturing a nitride semiconductor device according to one embodiment of the present invention.

6 is a cross-sectional view showing a nitride semiconductor device manufactured by a manufacturing method according to an embodiment of the present invention.

7 and 8 illustrate one step for describing a method of manufacturing the nitride semiconductor device according to the modified embodiment of the embodiment described with reference to FIGS. 2 to 5.

<Description of the symbols for the main parts of the drawings>

101: substrate 102: n-type nitride semiconductor layer

103: intermediate layer 104: active layer

105: high resistance region 106: p-type nitride semiconductor layer

207a and 207b: n-type and p-type electrodes

Claims (16)

an n-type nitride semiconductor layer; An intermediate layer formed on the n-type nitride semiconductor layer and having a first pit formed at a position corresponding to a potential propagated from a lower surface of the n-type nitride semiconductor layer to an upper surface thereof; An active layer formed on the intermediate layer and having a second pit formed at a position corresponding to the first pit; A high resistance region formed to at least partially fill the second pit of the active layer; And A p-type nitride semiconductor layer formed on the active layer; A nitride semiconductor device comprising a. The method of claim 1, The intermediate layer is a nitride semiconductor device, characterized in that made of undoped GaN or n-GaN. The method of claim 1, The width of the uppermost part of the first pit on the upper surface of the intermediate layer is 10 to 500nm, characterized in that the nitride semiconductor device. The method of claim 1, The width of the uppermost part of the second pit on the upper surface of the active layer is 10 to 200nm, characterized in that the nitride semiconductor device. The method of claim 1, And the first and second pits have an inverted pyramid shape. The method of claim 1, And the second pit is formed to a depth corresponding to a length at least greater than half the thickness of the active layer. The method of claim 1, And the second pit extends through the active layer to the intermediate layer. The method of claim 1, The high resistance region is formed in a range that does not fill the second pit, the p-type nitride semiconductor layer is formed to fill the region except the high resistance region in the second pit. The method of claim 1, And the high resistance region is formed of an undoped nitride semiconductor. The method of claim 1, The high resistance region is a nitride semiconductor device, characterized in that made of SiC. Forming an n-type nitride semiconductor layer on the substrate; Forming an intermediate layer on the n-type nitride semiconductor layer, the intermediate layer having a first pit formed at a position corresponding to a potential propagated from a lower surface of the n-type nitride semiconductor layer to an upper surface thereof; Forming an active layer on the intermediate layer; Etching a region corresponding to the position corresponding to the first pit in the active layer to form a second pit; Forming a high resistance region to at least partially fill the second pit of the active layer; And Forming a p-type nitride semiconductor layer on the active layer; Nitride semiconductor device manufacturing method comprising a. The method of claim 11, The first pit is spontaneously formed during the growth of the intermediate layer manufacturing method of the nitride semiconductor device. The method of claim 12, The growth temperature of the intermediate layer is a nitride semiconductor device manufacturing method, characterized in that 750 ~ 900 ℃. The method of claim 11, And forming the active layer so that a groove is formed at a position corresponding to the first pit in the active layer. The method of claim 11, Etching the position corresponding to the first pit in the active layer to form a second pit is performed by in-situ etching. The method of claim 15, And said in-situ etching is performed in a gas atmosphere comprising one gas selected from the group consisting of H ₂ , N ₂ and NH ₃ .

Images