KR101016958B1 - Multi Port Phase Change Memory Device - Google Patents

Abstract

The present invention relates to a phase change memory cell structure, wherein a multi-port phase change memory device according to the present invention comprises at least two word lines and a bit line; Two or more switching elements connected to the word line and the bit line; And a phase change material commonly connected to the switching elements to form one memory cell, wherein the switching elements are controlled by an operation control command corresponding to each port.

Multi-Port, Phase Change Memory, NMOS Transistors, Diodes

Description

Multi Port Phase Change Memory Device

1 is a view showing a state change of a phase change material constituting a conventional phase change memory cell

FIG. 2 is a graph of phase change characteristics according to time versus temperature of the phase change material shown in FIG. 1.

FIG. 3 is a diagram illustrating waveforms of current pulses for changing the phase change memory cell of FIG. 1 to first and second resistance states. FIG.

4 is a block diagram of a conventional phase change memory device.

FIG. 5 shows in detail the cell array in the apparatus according to FIG. 4; FIG.

6 is a diagram illustrating a cell configuration of a dual port phase change memory according to an exemplary embodiment of the present invention.

FIG. 7 is a diagram illustrating a cell array including a set of cells in FIG. 6.

8 is a cell diagram illustrating a multi-port phase change memory according to another embodiment of the present invention.

9 is a cell diagram illustrating a dual port phase change memory in accordance with still another embodiment of the present invention.

10 is a cell diagram of a multi-port phase change memorization showing another embodiment of the present invention.

The present invention relates to a memory device, and more particularly to a phase change memory cell structure.

Typically, by setting a phase change material to one of two physical states, data can be stored in a phase change memory cell comprised of a phase change material. For example, the first physical state of the phase change material may comprise a high resistance state and the second physical state may comprise a low resistance state. Here, when the high resistance state represents binary 1, the low resistance state may represent binary 0.

When a phase change memory device including a memory cell array having a plurality of phase change memory cells is employed in the electronic system, even when power supply to the phase change memory device is interrupted, Stored data is not lost due to the nature of the phase change material. That is, the phase change memory device is a nonvolatile memory unlike a DRAM. Moreover, high speed operation and low power consumption characteristics are another advantage of the phase change memory device.

1 shows a cross-sectional view of a phase change material.

The phase change material has a structure in which the phase change material 4 is positioned between the upper electrode 2 and the lower electrode 6. The phase change material 4 has a resistance value that is changed by changing a phase into a crystalline or amorphous state according to temperature and heating time. That is, it becomes a phase change resistor (PCR) element. The PCR may be composed of AgInSbTe, GexSbyTez and the like.

When the access transistor NT is connected to the phase change material, one phase change memory cell may be configured. The gate of the access transistor NT may be connected to a word line WL forming a row of a memory cell array, and one end of the variable resistor PCR forms a bit line BL of a column of a memory cell array. It can be connected with. The variable resistor R is connected to the bit line, but may be connected between the source terminal of the access transistor NT and the reference voltage line GND.

When one access transistor NT is connected to the variable resistor R made of the phase change material, one phase change memory cell may be configured. The gate of the access transistor NT may be connected to a word line WL forming a row of a memory cell array, and one end of the variable resistor R forms a bit line BL forming a column of a memory cell array. It can be connected with.

On the other hand, the variable resistor R is connected to a bit line, but when the case is different, the variable resistor R may be connected between the source terminal of the access transistor NT and the reference voltage line GND.

FIG. 2 shows the phase change characteristics with time versus temperature of the phase change material (PCR) shown in FIG. In the figure, the horizontal axis represents time and the vertical axis represents temperature (T). The amorphous state of the phase change material (PCR) is achieved by heating the phase change material (PCR) above the melting point (Tm: melting temperature) and then rapidly cooling it. In addition, the crystallization state, as shown along the graph reference numerals (22, 20, 24), and after cooling the phase change material (GST) above the crystallization temperature (Tx: crystallization temperature) for a predetermined time, Is achieved by

In the phase change characteristic graphs of FIG. 2, the waveforms of the current pulses to be applied for amorphous and crystallization can be considered, which is shown in FIG. 3.

In the figure, the horizontal axis represents time and the vertical axis represents current I. In comparing the intensities of the currents, the level of the reset current pulse G1 is higher than the level of the set current pulse G2. When comparing the application time of the current, the application time of the set current pulse G2 is relatively longer than the application time of the reset current pulse G1. The reset current pulse G1 and the set current pulse G2 of FIG. 3 mean a write current to be applied to the phase change memory cell in order to store binary 1 or binary 0 in the write operation mode. As a result, the phase change material is set or reset by a joule heating generated according to the magnitude of the current and the application time of the current.

4 is a block diagram illustrating a write operation of a conventional phase change memory device. Referring to the drawings, the row (X) address buffers 110_1 and 110_2, the pre decoder 120, the main decoder 140, the data input buffer 111, the write driver 130, the column (Y) path and the column (Y) The wiring relationship composed of the decoder 150 and the phase change memory cell array 160 is shown. The circuit blocks in the apparatus of FIG. 4 are very similar to the circuit functional blocks of a conventional DRAM. However, due to the characteristics of the phase change material (PCR) in the phase change memory cell array 160, the write driver 130 and the phase change memory cell array 160 in FIG. 4 may be configured in detail with corresponding blocks of the DRAM. And in terms of operation.

Assuming that the write data DATA is stored in a phase change memory cell connected between the first word line WLi and the first bit line BLi in the memory cell array 160 of FIG. 4, the main decoder 140 The first word line WLi is activated by a row decoding operation. On the other hand, the first bit line BLi is selected by the column path and the column decoding operation of the column decoder 150. Meanwhile, the write data DATA applied through the input terminal DIN of the data input buffer 111 is provided to the write driver 130. When the write data DATA is logic 1, the write driver 130 applies the reset current pulse G1 shown in FIG. 3 to the section data line SDL by the pulse width of the reset control pulse RESET_C0N_PULSE. It is applied as a write current. When the reset current pulse G1 is applied to the first bit line BLi, the phase change material PCR of the selected phase change memory cell is reset. As a result, since the reset memory cell has a high resistance state, it can function as a memory cell storing data 1.

Meanwhile, when the write data DATA is logic 0, the write driver 130 sets the set current pulse G2 as shown in FIG. 3 by the pulse width of the set control pulse SET_CON_PULSE. It is applied to (SDL) as a write current. When the set current pulse G1 is applied to the first bit line BLi, the phase change material PCR of the selected phase change memory cell is set. As a result, the set memory cell has a relatively low resistance state, and thus functions as a memory cell storing data zero.

5 illustrates the structure of the cell array 160 of the phase change memory device of FIG. 4.

As illustrated, in the conventional phase change memory device, only one switching element D is connected to one phase change material PCR. That is, one electrode of the phase change material PCR is connected to the bit line, the other electrode is connected to the P type of the PN diode, and the N type of the PN diode is connected to the word line.

 In such a conventional memory cell structure, it is impossible to configure a dual port or a multi port by connecting one phase change material to one bit line and a word line.

Therefore, it is impossible to simultaneously access the data of the memory cell using two interfaces, and there is a problem in that the data cannot be used efficiently.

An object of the present invention is to provide a phase change memory cell structure capable of a multi-port configuration.

In addition, an object of the present invention is to provide a phase change memory cell capable of performing write and read operations by independently controlling each port using a plurality of ports.

Another object of the present invention is to provide a phase change memory cell capable of performing write and read operations, which are different operations using a plurality of ports.

A multi-port phase change memory device according to the present invention includes two or more word lines and bit lines; Two or more switching elements connected to the word line and the bit line; And a phase change material commonly connected to the switching elements to form one memory cell, wherein the switching elements are controlled by an operation control command corresponding to each port.

The switching elements are characterized in that the other switching element is turned off when one is on.

Preferably, the switching element is an NMOS transistor, a gate terminal of the NMOS transistor is connected to a word line, a drain terminal is connected to a bit line, and a source terminal is connected to one side of the phase change material.

The word line and the bit line are preferably provided equal to the number of ports.

A power supply line or a ground voltage line may be connected to the other side of the phase change material.

In addition, the multi-port phase change memory device according to the present invention includes at least two word lines and bit lines; At least two switching elements comprising a diode pair connected to the word line and the bit line; And a phase change material commonly connected to the switching elements to form one memory cell, wherein the switching elements are controlled by an operation control command corresponding to each port.

The switching elements are turned off when one is on.

The diode pair includes a first diode having an anode connected to the bit line and a cathode connected to the phase change material; And a second diode having an anode connected to the phase change material and a cathode connected to the word line.

The number of word lines and bit lines is preferably equal to the number of ports.

In addition, the multi-port phase change memory device according to the present invention includes: a first word line and a first bit line connected to the first port and crossing each other at right angles; A second word line and a second bit line connected to the second port and crossing each other at right angles; First and second diodes connected to the first bit line and the first word line, respectively; Third and fourth diodes connected to the second bit line and the second word line, respectively; And a phase change material connected to the first and third diodes to form a first storage node and connected to the second and fourth diodes to form a second storage node. Do.

Here, it is preferable that the anode of the first diode is connected to the first bit line and the cathode is connected to the first storage node.

Here, the cathode of the second diode is preferably connected to the first word line and the anode is connected to the second storage node.

Here, the anode of the third diode is preferably connected to the second bit line and the anode is connected to the first storage node.

Here, the cathode of the fourth diode is preferably connected to the second word line and the anode is connected to the second storage line.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 6 illustrates a cell configuration of a dual port phase change memory according to an embodiment of the present invention.

The memory cell according to the present exemplary embodiment includes two NMOS transistors T_P1 and T_P2 and one phase change material 10 driven by two word lines.

The first word line WL_P1 and the first bit line BL_P1 are connected to the first port (not shown), and the second word line WL_P2 and the second bit line BL_P2 are connected to the second port (not shown). Connected.

The gate of the first NMOS transistor T_P1 is connected to a first word line WL_P1 controlled by a first port (not shown). A drain terminal of the first NMOS transistor T_P1 is connected to a first bit line BL_P1 and one electrode of a phase change material 10 is connected to a source terminal of the first NMOS transistor T_P1 so that a node is stored. Node, SN).

The gate of the second NMOS transistor T_P2 is connected to a second word line WL_P2 controlled by a second port (not shown). A drain terminal of the second NMOS transistor T_P2 is connected to the second bit line BL_P2 and one electrode of the phase change material PCR is connected to a source terminal.

That is, one electrode of the phase change material is commonly connected to the source terminals of the first and second NMOS transistors to form a storage node, and the other electrode is connected to the source line. The main function of the source line is to supply a ground voltage in an active operation, and in a precharge operation, it may be grounded or floating according to a circuit configuration and an operation method, and may be high ( high) voltage may be supplied. That is, the source line may be a control line and may vary depending on the architecture of the cell array. The source line may be connected to a power supply voltage VDD line or may be connected to a ground voltage VSS line.

With this configuration, it is possible to control one data cell independently using two word lines.

For example, when the first port is used, the first word line WL_P1 is controlled to turn on the first NMOS transistor T_P1, and data input / output is performed through the first word line BL_P1. In this case, the second NMOS transistor T_P2 maintains the off state. On the contrary, when the second port is used, the second NMOS transistor is turned on and data is input / output through the second bit line BL_P1.

With the above configuration, two transistors can be independently controlled by two word lines, and corresponding bit lines can be selected. Therefore, one phase change memory cell can be independently controlled by two processors.

FIG. 7 is a diagram illustrating a cell array including cells as shown in FIG. 6.

It can be seen that a plurality of word lines and bit lines are arranged orthogonally, and the cells shown in FIG. 6 form a cell array.

The bit lines BL0_P1 and / BL0_P1 of the first port are connected to the first sense amplifier unit 20, and the bit lines BL0_P2 and / BL0_P2 of the second port are connected to the second sense amplifier unit 30. do. That is, when the first port is used, the word lines WL0_P1 and WL1_P1 are driven, the NMOS transistor T_P1 is turned on, and the first sense amplifier unit 20 is operated. When the second port is used, The word lines WL0_P2 and WL1_P2 are driven, the NMOS transistor T_P2 is turned on, and the second sense amplifier unit 30 is operated. The sense amplifier units 20 and 30 are each independently controlled by dual ports.

8 illustrates a multi-port cell structure according to another embodiment of the present invention.

The memory cell according to the present exemplary embodiment includes four NMOS transistors T_P1, T_P2, T_P3, and T_P4 driven by four word lines WL_P1, WL_P2, WL_P3, and WL_P4 and one phase change material PCR. .

A gate of the first NMOS transistor T_P1 is connected to a first word line WL_P1 controlled by a first port (not shown), and a drain terminal of the first NMOS transistor T_P1 is connected to a first bit line BL_P1. ), And one electrode of the phase change material PCR is connected to a source terminal of the first NMOS transistor T_P1 to form a node.

In addition, a gate of the second NMOS transistor T_P2 is connected to a second word line WL_P1 controlled by a second port (not shown), and a drain terminal of the first NMOS transistor T_P2 is connected to a second bit line. One electrode of a phase change material PCR is connected to a source terminal of the second NMOS transistor T_P2 to form a node.

Similarly, the third NMOS transistor T_P3 and the fourth NMOS transistor T_P4 also have gates connected to word lines WL_P3 and WL_P4, drain terminals connected to bit lines BL_P3 and BL_P4, and source stages of phase change. It is connected to one electrode of the material 10.

With the above configuration, four transistors can be independently controlled by four word lines, and corresponding bit lines can be selected. Therefore, one phase change memory cell can be independently controlled by four processors.

FIG. 9 illustrates a memory cell structure when a PN diode is used instead of an NMOS transistor as a switching device according to another embodiment of the present invention.

As shown, the phase change memory cell is composed of four diodes D1_P1, D1_P2, D2_P1, and D2_P2 and one phase change material PCR.

The first word line WL_P1 and the first bit line BL_P1 are connected to the first port, and the second word line WL_P2 and the second bit line BL_P2 are connected to the second port.

The cathode of the first diode D1_P1 and the second diode D1_P2 is connected to one electrode of the phase change material PCR so that a first storage node SN1 is formed, and the anode has a first bit line BL_P1. ) And the second bit line BL_P2, respectively.

An anode of the third diode D2_P1 and the fourth diode D2_P2 is connected to the other electrode of the phase change material PCR to form a second storage node SN2, and the cathodes of the first word line WL_P1 are respectively. ) And the second word line WL_P2.

By the above configuration, the memory cell data may be independently controlled through two processors by selectively driving the first word line WL_P1 and the second word line WL_P2. That is, when a low voltage is applied to the first word line, a high voltage is applied to the second word line so that the third diode D2_P1 is turned on and the fourth diode D2_P2 is turned off, thereby providing cell data through two processors. Can be controlled independently.

FIG. 10 illustrates a multi-port phase change memory cell structure including eight diodes D1_P1, D1_P2, D1_P3, D1_P4, D2_P1, D2_P2, D2_P3, and D2_P4 and one phase change material (PCR). It is shown.

A first word line WL_P1 and a first bit line BL_P1 at a first port, a second word line WL_P2 and a second bit line BL_P2 at a second port, and a third word line WL_P3 at a third port. ), A third bit line BL_P3 and a fourth port are connected to a fourth word line WL_P4 and a first bit line BL_P4.

The cathode of the first diode D1_P1, the second diode D1_P2, the third diode D1_P3, and the fourth diode D1_P4 is connected to one electrode of the phase change material PCR so that the first storage node SN1 is connected. ) Is formed, and the anodes of the diodes D1_P1, D1_P2, D1_P3, and D1_P4 are connected to bit lines BL_P1, BL_P2, BL_P3, and BL_P4 corresponding to the respective ports. The anodes of the fifth diode D2_P1, the sixth diode D2_P2, the seventh diode D2_P3, and the eighth diode D2_P4 are connected to the other electrode of the phase change material PCR to connect the second storage node SN2. ) Is formed and the anode is connected to word lines WL_P1, WL_P2, WL_P3, and WL_P4 corresponding to the respective ports.

By the above configuration, the memory cell data is selectively driven by selectively driving the first word line WL_P1, the second word line WL_P2, the third word line WL_P3, and the fourth word line WL_P4. Can be controlled independently. That is, when a low voltage is applied to the first word line, a high voltage is applied to the remaining word lines so that only the fifth diode D2_P1 is turned on and the sixth to eighth diodes D2_P2, D2P_3, and D3_P4 are turned off. Cell processors can be controlled independently through four processors.

As described above, according to the present invention, a multi-port phase change memory cell can be implemented.

In addition, according to the present invention, write and read operations may be performed by independently controlling each port using a plurality of ports.

Accordingly, according to the present invention, the write and read operations, which are different operations using the plurality of ports, may be performed to improve the access performance of the memory cell.

Claims (19)

Two or more word lines and bit lines; Two or more switching elements connected to the word line and the bit line; And Phase change material commonly connected to the switching elements; is provided to form a memory cell, And the switching elements are controlled by an operation control command corresponding to each port. The method of claim 1, And the switching elements are turned off when one of the switching elements is on. The method of claim 1, The switching element is an NMOS transistor, And a gate terminal of the NMOS transistor is connected to a word line, a drain terminal is connected to a bit line, and a source terminal is connected to one side of the phase change material. The method of claim 1, And the word lines and the bit lines are equal to the number of ports. The method of claim 3, wherein A multi-port phase change memory device, characterized in that a power supply line or a ground voltage line is connected to the other side of the phase change material. A first wordline and a first bitline coupled to the first port; A second word line and a second bit line connected to the second port; A first MOS transistor and a second MOS transistor driven by the first word line and the second word line; And And a phase change material having one side connected to a source terminal of the first and second MOS transistors to form a single cell. The method of claim 6, And a gate terminal of the first MOS transistor is connected to the first word line, and a drain terminal of the first MOS transistor is connected to the first bit line. The method of claim 6, And a gate terminal of the second MOS transistor is connected to the second word line, and a drain terminal of the second MOS transistor is connected to the second bit line. The method of claim 6, And the first and second MOS transistors are NMOS transistors. The method of claim 6, The other port of the phase change material, characterized in that the power voltage line or ground voltage line is connected. Two or more word lines and bit lines; At least two switching elements comprising a diode pair connected to the word line and the bit line; And Phase change material commonly connected to the switching elements; is provided to form a memory cell, And the switching elements are controlled by an operation control command corresponding to each port. The method of claim 11, And the switching elements are turned off when one of the switching elements is on. The method of claim 11, The diode pair includes a first diode having an anode connected to the bit line and a cathode connected to the phase change material; And And a cathode connected to a phase change material and a cathode connected to the word line. The method of claim 11, And the number of word lines and bit lines is the same as the number of ports. A first wordline and a first bitline coupled to the first port; A second word line and a second bit line connected to the second port; First and second diodes connected to the first bit line and the first word line, respectively; Third and fourth diodes connected to the second bit line and a second word line, respectively; And A phase change material connected to the first and third diodes to form a first storage node, and connected to the second and fourth diodes to form a second storage node; Multi-port phase change memory device. The method of claim 15, And the anode of the first diode is connected to the first bit line and the cathode of the first diode is connected to the first storage node. The method of claim 15, And the cathode of the second diode is connected to the first word line and the anode is connected to the second storage node. The method of claim 15, And the anode of the third diode is connected to the second bit line and the anode is connected to the first storage node. The method of claim 15, And the cathode of the fourth diode is connected to the second word line and the anode is connected to the second storage line.

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