KR101015488B1 - Tester - Google Patents

Abstract

A bad count memory for storing the number of bad cells for each memory bank and for each block, a bad count register for storing the number of bad cells detected in the test target block for each memory bank, and some pages in the test target block from each memory bank. A memory reader that sequentially reads the data, a detector that detects defective cells in each page based on a result of comparing the data read from each page by the memory reader with an expected value, and a page where the defective cells are detected. A bad count unit for increasing the value of the bad count register corresponding to the memory bank included by the number of detected bad cells, and a bad cell stored in the bad count register corresponding to the memory bank which has finished detecting the bad of each page in the block to be tested. Number of bad count memory in the corresponding test of the corresponding memory bank A test apparatus including a writing unit for writing in a storage area corresponding to an upper block is provided.

Test Units, Memory Banks, Bad Cells, Repair Processing

Description

Test device {TESTER}

The present invention relates to a test apparatus. In particular, the present invention relates to a test apparatus for testing a memory under test having a plurality of memory banks.

Recently, the spread of flash memory is in progress. A semiconductor memory such as a flash memory has a memory cell array including a plurality of memory cells that store one bit of data. It is difficult to manufacture all the memory cells in good condition, and the memory cell array includes defective memory cells (bad cells) in part. Here, in the semiconductor memory, extra memory cells (extra cells) for the purpose of replacing the defective cells are provided in advance, so that the yield can be improved.

The process of replacing a defective cell with a spare cell is called a memory repair (or redundancy), and is performed during the test of the semiconductor memory. In the memory repair, first, the test apparatus detects where a defective cell is included in the memory cell array. Next, the test apparatus calculates a solution for determining how to replace the detected defective cell with the spare cell. The test apparatus feeds back the calculated relief solution to the semiconductor memory.

In addition, a flash memory of a plurality of bank types having a plurality of memory cell arrays is known. Flash banks in the form of a plurality of banks have a plurality of input / output buffers corresponding to the respective memory cell arrays, and read or write can be performed in parallel with the plurality of memory cell arrays. Therefore, the flash memory in the form of a plurality of banks can write and read data of a plurality of banks (that is, data of a plurality of pages) in parallel. In other words, the multi-bank type flash memory can increase the data transfer amount, thereby speeding up the read and write.

[Problems to Solve Invention]

However, in the test of flash memory in the form of a multi-bank, it has been difficult for the test apparatus to detect the number of defective cells at a high rate per bank and block by block while using parallel read and write for multiple pages, which is an advantage of the multi-bank form. .

Here, an object of this invention is to provide the test apparatus which can solve the said subject. This object is achieved by a combination of the features described in the independent claims in the claims. The dependent claims also define further advantageous specific examples of the invention.

[Means for solving the problem]

In order to solve the above problems, according to a first aspect of the present invention, there is provided a test apparatus for testing a memory under test having a plurality of memory banks, comprising: a bad count memory for storing the number of defective cells for each memory bank and for each block; Each memory bank includes a bad count register for storing the number of defective cells detected in the block to be tested, a memory reader for sequentially reading some pages in the block to be tested from each memory bank, and a memory reader. A detection unit for detecting a defective cell in each page based on a result of comparing the data read from the page with the expected value, and a value of the defective count register corresponding to the memory bank including the page in which the defective cell is detected. A defect counting unit that increases by a number and detects defects of each page in the block to be tested; A test apparatus including a writing unit for writing the number of defective cells stored in the defective count register in correspondence with the completed memory bank in a storage area corresponding to the test target block of the memory bank in the defective count memory.

According to the second aspect of the present invention, in a test apparatus for testing a memory under test having a plurality of memory banks, a defective count memory for storing the number of defective cells for each memory bank and for each block, and a part of each memory bank. A memory reader that sequentially reads the pages one by one, a detector that detects the defective cells in each page based on a result of comparing the data read from each page by the memory reader with an expected value, and sequentially detected each page The bad count unit that counts the number of bad cells, and the number of bad cells stored in the bad count memory for the memory banks and blocks corresponding to the page sequentially for each page, are as many as the bad cells counted by the bad count unit. A test apparatus including an update unit for updating to an increased value is provided.

In addition, the above summary of the invention does not enumerate all of the necessary features of the present invention, and subcombinations of these groups of features may also be inventions.

1 shows a configuration of a test apparatus 10 according to an embodiment of the present invention together with a memory under test 500.

2 shows an example of the configuration of the memory under test 500.

3 shows an example of the logic configuration of the memory bank 502 of the memory under test 500 and the logic configuration of the pattern generator 18.

4 shows an operation flow of a read test of the test apparatus 10 according to the embodiment of the present invention.

FIG. 5 shows a data reading procedure of the test apparatus 10 according to the present embodiment when the flow shown in FIG. 4 is executed.

FIG. 6 shows the configuration of the test apparatus 10 according to the first modification of the embodiment of the present invention together with the memory under test 500.

7 shows a logic configuration of the pattern generator 18 according to the first modification and an example of the logic configuration of the memory bank 502 of the memory under test 500.

8 shows the configuration of the test apparatus 10 according to the second modification of the embodiment of the present invention together with the memory under test 500.

9 shows the configuration of the test apparatus 10 according to the third modification of the embodiment of the present invention together with the memory under test 500.

[Description of the code]

10 test device

12 bad count memory

14 memory reader

16 bad cell count detection circuit

18 pattern generator

20 bad count register

22 detector

24 bad count

28 entry

30 bad cell registers

32 comparator

34 bit adder

36 multiplexer

38 increments

48 Address Conversion Section

50 selector

60 update departments

64 update processing unit

500 Test Memory

502 memory bank

512 IO terminal

514 control terminal

516 RY / BY jack

522 status registers

524 address register

526 command register

528 input and output control circuit

530 motion logic controller

532 control circuit

540 memory cell array

542 column address decoder

544 Row Address Decoder

546 data registers

548 amplifier

EMBODIMENT OF THE INVENTION Hereinafter, although this invention is demonstrated through embodiment of invention, the following embodiment does not limit invention contained in a claim, and all the combination of the characteristics demonstrated in embodiment is essential for the solution of this invention. Is not limited.

1 shows the configuration of a test apparatus 10 according to the present embodiment together with a memory under test 500. The test apparatus 10 tests the memory under test 500 having a plurality of memory banks 502. The memory under test 500 may be, for example, a NAND type flash memory having a plurality of memory banks 502. More specifically, the test apparatus 10 detects the number of defective cells included in the memory under test 500 for each memory bank 502 and for each block. The number of defective cells for each block detected is used as an example for calculation processing of a remedy for memory repair for each memory bank 502.

The test apparatus 10 includes a bad count memory 12, a memory reading unit 14, a bad cell number detection circuit 16, and a pattern generator 18. The defective count memory 12 stores the number of defective cells included in the memory under test 500 every memory bank 502 and every block.

The memory reading unit 14 sequentially reads some pages in the block to be tested from each memory bank 502. As an example, the memory reading unit 14 may sequentially read out data stored in the test target block of each memory bank 502 one page at a time. The pattern generator 18 outputs the expected value of the data read by the memory reader 14, the address of the block to be tested in the memory under test 500, and a control signal for the defective cell number detection circuit 16.

The defective cell number detection circuit 16 detects the number of defective cells included in the test target block based on the data of the test target block read by the memory reader 14 and returns the detection result to the bad count memory 12. Fill in The defective cell number detection circuit 16 includes a defective count register 20, a detection unit 22, a defective counting unit 24, and a writing unit 28.

The bad count register 20 stores the number of bad cells detected in the block under test for each memory bank 502. As an example, the defective count register 20 may include a plurality of defective cell registers 30 that correspond one-to-one to the plurality of memory banks 502. The plurality of bad cell registers 30 stores the number of bad cells detected by the block under test in the corresponding memory bank 502. The plurality of defective cell registers 30 are, for example, based on a control signal from the pattern generator 18 or the like prior to detection of the defective cells in the block under test (for example, the first page of the block under test). Before reading), the number of defective cells to be stored may be reset to an initial value (for example, 0).

The detection unit 22 detects defective cells in each page based on a result of comparing the data read out from each page by the memory reading unit 14 with the expected value. The detection part 22 may include the comparator 32 and the bit adder 34 as an example. The comparator 32 compares the read data read from each page by the memory reader 14 with the expected value generated by the pattern generator 18 bit by bit. The bit adder 34 adds bits in which the read data and the expected value did not coincide (i.e., bad bits) in the IO direction. The bit adder 34 then outputs the addition result as the number of defective cells in the page.

The defective count unit 24 increases the value of the defective count register 20 corresponding to the memory bank 502 including the page in which the defective cells are detected by the number of detected defective cells. As an example, the failure count unit 24 may include a plurality of increment units 38 that correspond to the multiplexer 36 and the plurality of memory banks 502 one-to-one. The multiplexer 36 selects the incrementer 38 corresponding to the memory bank 502 including the page where the defective cell is detected, for example, based on the control signal from the pattern generator 18 or the like. The multiplexer 36 then outputs the detection result of the defective cell in the page by the detector 22 to the selected incrementer 38. The increasing unit 38 selected by the multiplexer 36 increases the value stored in the corresponding defective cell register 30 by the number of defective cells in the corresponding page detected by the detecting unit 22.

The writing unit 28 stores the number of defective cells stored in the defective count register 20 in correspondence with the memory bank 502 which has completed the failure detection of each page in the block to be tested. It writes in the memory area corresponding to the said test object block of (502). The writing unit 28 may include, for example, an address conversion unit 48 and a selector 50.

The address conversion unit 48 outputs an address designating a storage area corresponding to the test target block of the memory bank 502 in which the failure detection of each page in the test target block in the bad count memory 12 is completed. As an example, the address conversion unit 48 may convert the address of the test target block in the memory under test 500 output by the pattern generator 18 into a corresponding address in the defective count memory 12. The selector 50 selects the defective cell register 30 corresponding to the memory bank 502 which has finished detecting the failure of each page in the block to be tested. The selector 50 writes the number of defective cells stored in the selected defective cell register 30 to a storage area in the defective count memory 12 designated by the address conversion section 48.

2 shows an example of the configuration of the memory under test 500. The memory under test 500 is, for example, a plurality of memory banks 502, a status register 522, an address register 524, a command register 526, an input / output control circuit 528, and an operation. The logic controller 530 and the control circuit 532 are provided.

Each of the plurality of memory banks 502 includes a memory cell array 540, a column address decoder 542, a row address decoder 544, a data register 546, and an amplifier 548. The memory cell array 540 is a set of memory cells that store data in units of 1 bit. The column address decoder 542 specifies an address in the column direction of the memory cell array 540 based on the address stored in the address register 524. The row address decoder 544 specifies an address in the row direction of the memory cell array 540 based on the address stored in the address register 524. The data register 546 input / output data unit (for example, 8 bits) by the IO terminal 512 to write data to be written to the memory cell array 540 and read data read from the memory cell array 540. To be temporarily stored.

The amplifier 548 writes the write data stored in the data register 546 to the memory cells designated by the column address decoder 542 and the row address decoder 544 in the memory cell array 540 when a write command is given. do. Further, when a read command is given, the amplifier 548 reads data from the memory cells designated by the column address decoder 542 and the row address decoder 544 in the memory cell array 540, and reads the data register as read data. It is stored in 546.

The status register 522 stores status information indicating an operating state of the memory under test 500. The address register 524 stores an address indicating a write destination of write data and an address indicating a read source of read data. The command register 526 stores an operation command for instructing an operation on the memory under test 500.

The input / output control circuit 528 stores write data input from the outside through the IO terminal 512 in the data register 546 of the memory bank 502 at the time of writing. The input / output control circuit 528 outputs read data read from the data register 546 of the memory bank 502 to the outside through the IO terminal 512 at the time of reading. The input / output control circuit 528 stores an address input from the outside through the IO terminal 512 in the address register 524. The input / output control circuit 528 stores an operation command input from the outside through the IO terminal 512 in the command register 526. The input / output control circuit 528 outputs the status stored in the status register 522 to the outside via the IO terminal 512.

The operation logic controller 530 supplies each control command input from the outside through the control terminal 514 to the input / output control circuit 528 and the control circuit 532. The control circuit 532 controls each operation of the plurality of memory banks 502 by outputting a write command, a read command, and the like in accordance with the operation command and the control command. In addition, the control circuit 532 outputs an RY / BY signal to the outside through the RY / BY terminal 516 that the memory under test 500 indicates a ready state or a busy state.

In the memory under test 500 described above, a read command and an address are given from the outside via the IO terminal 512 at the time of reading. The memory under test 500 outputs data stored at a given address to the outside via the IO terminal 512 in units of pages. In addition, when a read command is given to read data written to two pages in the same memory bank 502, the memory under test 500 outputs the data of the previous page and a predetermined read margin time (e.g., For example, the data of the next page is output after about 25 microseconds). However, when the memory under test 500 is given a read command to read data written to two pages in different memory banks 502, the memory under test 500 outputs the data of the previous page, and the predetermined memory is output. The data of the next page can be output before the read margin period of.

In addition, the memory under test 500 is given a write command, write data and an address from the outside via the IO terminal 512 at the time of writing. The memory under test 500 writes write data in units of pages for a given address. In addition, when a write command to write data is given for two pages in the same memory bank 502, the memory under test 500 inputs data of the previous page to give a predetermined write margin period (e.g., After about 100μ seconds, input the data of the next page. However, when the memory under test 500 is given a write command to write data for two pages of different memory banks 502, the memory under test 500 inputs the data of the previous page, and the predetermined data is input. The data of the next page can be input before the write margin period (for example, about 100 microseconds) elapses.

3 shows an example of the logic configuration of the memory bank 502 of the memory under test 500 and the logic configuration of the pattern generator 18. Each of the plurality of memory banks 502 included in the memory under test 500 includes a plurality of blocks having a plurality of pages.

Each of the plurality of blocks may be assigned a unique block number. As an example, the memory bank 502 may include 2048 blocks to which block numbers of blocks 0 to 2047 are assigned. In addition, the plurality of memory banks 502 may include a plurality of blocks assigned the same block number or may include a plurality of blocks assigned different block numbers. For example, the first memory bank 502-1 has a plurality of blocks with even block numbers, and the second memory bank 502-2 has a plurality of blocks with odd block numbers. You may also do it.

A page is a unit of writing and reading data. Each of the plurality of pages may be given a page number indicating a position in the block. Each of the plurality of blocks may have 64 pages to which page 0 to page 63 can be given as an example.

In addition, each page includes a plurality of columns. The number of columns in a page is the same for all pages. A plurality of columns can be given column numbers that specify each. Column numbers are common across all pages of every block. Each of the plurality of pages may include, for example, 2048 columns to which columns 0 to 2047 can be assigned.

One column in one page contains a predetermined number of memory cells. The plurality of memory cells included in one column correspond one-to-one to each of the plurality of IO terminals 512. One column in one page may include eight memory cells as an example.

Furthermore, the memory bank 502 of the memory under test 500 includes a plurality of repair blocks and a plurality of repair columns. The repair block is used instead of the block containing the defective cell. The repair block has substantially the same structure as the block, and can be replaced with any one block by the memory repair.

The repair column is used in place of the column containing the defective cell. The repair column is configured to include memory cells corresponding to columns of the same position for all pages of all blocks. The repair column can be replaced by a memory repairer in a batch with one column at the same position for every page of every block.

The defective count memory 12 is provided with a plurality of memory regions divided for each of the plurality of memory banks 502 and the plurality of blocks of the memory under test 500. Each of the plurality of storage areas of the defective count memory 12 stores the number of defective cells included in the corresponding block of the corresponding memory bank 502. Thus, when the test apparatus 10 has completed the tests for all the blocks of the memory under test 500, the bad count memory 12 determines the number of bad cells for each of the plurality of memory banks 502 and for each block. Remember

4 shows an operation flow of a read test of the test apparatus 10 according to the present embodiment. First, the test apparatus 10 sequentially selects one block in each of the plurality of memory banks 502. The test apparatus 10 executes the processing from step S1002 to step S1010 described below as the block to be tested in each of the plurality of memory banks 502 (S1001 and S1011). Next, the bad count register 20 resets each of the number of bad cells stored in each memory bank 502 to an initial value (for example, 0) (S1002).

Next, the test apparatus 10 sequentially selects the pages in the block to be tested one by one and executes the processing of step S1008 from step S1004 below for the selected pages (S1003, S1009). As an example, the test apparatus 10 may select pages one by one in ascending order from page 0 in the block to be tested.

Next, the test apparatus 10 sequentially selects the memory banks 502 one by one, and executes the processing of the following steps S1005 and S1007 for the selected memory bank 502 (S1004 and S1008). Initially, the memory reading unit 14 reads out data written in the page selected in step S1003 in the test object block selected in step S1001 in the selected memory bank 502 (S1005). Subsequently, the detection unit 22 compares the data read in step S1005 with the expected value, and detects a defective cell in the page based on the comparison result (S1006). Subsequently, the bad counting unit 24 increases the value of the storage area for the selected memory bank 502 in the bad count register 20 by the number of bad cells detected by the detecting unit 22 (S1007). When the test apparatus 10 finishes executing the processing of step S1007 for step S1005 for all the memory banks 502, the processing moves to step S1009 (S1008).

The test apparatus 10 moves the processing to step S1010 when all the pages in the test target block of each memory bank 502 have finished executing the processing of step S1008 from step S1004. Next, the writing unit 28 tests each of the number of defective cells of the plurality of memory banks 502 stored in the defective count register 20 of the corresponding memory bank 502 in the defective count memory 12. The data is written in the storage area corresponding to the target block (S1010). Then, when the test apparatus 10 finishes the execution of the processes from the above steps S1002 to S1010 for all the blocks, the reading test is terminated (S1011).

FIG. 5 shows a data reading procedure of the test apparatus 10 according to the present embodiment when the flow shown in FIG. 4 is executed. By reading the data by the flow shown in FIG. 4, the test apparatus 10 can read the data by changing the memory bank 502 for each page. For example, when the memory under test 500 includes the first memory bank 502-1 and the second memory bank 502-2, the test apparatus 10 may be configured as the first memory bank 502-1. Page 0 → page 0 of second memory bank 502-2 → page 1 of first memory bank 502-1 → page 1 of second memory bank 502-2 →. → page 63 of the first memory bank 502-1 → page 63 of the second memory bank 502-2 can read data from the memory under test 500. Thereby, according to the test apparatus 10, since data can be read out in parallel from the some memory bank 502, the detection period of a defective cell can be shortened.

Further, the test apparatus 10 includes a fail count register 20 for storing the number of defective cells detected in the block to be tested in each memory bank 502. For example, the failure count register 20 may include a first failure cell register 30-1 corresponding to the first memory bank 502-1 and a second failure corresponding to the second memory bank 502-2. The cell register 30-2 is included. Thereby, according to the test apparatus 10, even if data is read out in parallel from the some memory bank 502, the defective cell detected from the some memory bank 502 can be stored separately. As described above, according to the test apparatus 10, the number of defective cells can be detected at high speed for each bank and each block from the memory under test 500 having a plurality of banks.

In addition, instead of reading the data by changing the memory bank 502 for each page, the test apparatus 10 may read the data by changing the memory bank 502 for every part of the page (every number of pages). First of all, when the memory under test 500 is a flash memory, the test apparatus 10 can shorten the detection period by changing the memory bank 502 for each page to read data.

FIG. 6: shows the structure of the test apparatus 10 which concerns on the 1st modified example of this embodiment with the memory under test 500. FIG. 7 shows a logic configuration of the pattern generator 18 according to the first modification and an example of the logic configuration of the memory bank 502 of the memory under test 500. Since the test apparatus 10 which concerns on this modification is employ | adopted substantially the same structure and function as the member of the same code | symbol shown in FIG. 1, it abbreviate | omits description except the following difference.

As shown in FIG. 7, the defective count memory 12 according to the present modification includes the number of defective cells per IO terminal 512, per memory bank 502, and per block in the memory bank 502. Remember In addition, in the test apparatus 10 according to the present modification, instead of one defective cell number detection circuit 16 as shown in FIG. 6, each of the IO terminals 512 of the memory under test 500 is used. And a plurality of defective cell number detection circuits 16 corresponding to the plurality of defective cells. As an example, the test apparatus 10 may include the first defective cell number detection circuit 16-1 to the eighth defective cell number detection circuit 16-8.

The detection unit 22 of each of the plurality of defective cell number detection circuits 16 includes one bit output from the corresponding IO terminal 512 among the data read from the memory 500 under test by the memory reading unit 14. Input data of. The detector 22 compares the one-bit data output from the corresponding IO terminal 512 with the expected value to be output from the corresponding IO terminal 512. The detection unit 22 then detects the defective cells in each page based on the comparison result.

In addition, the writing unit 28 included in each of the plurality of defective cell number detection circuits 16 is stored in the defective count register 20 in correspondence with the memory bank 502 which has completed the failure detection of each page in the block to be tested. The number of defective cells is written into a predetermined storage area in the defective count memory 12. In this case, each writing unit 28 writes in the storage area corresponding to the corresponding IO terminal 512 and in the storage area corresponding to the corresponding block under test of the memory bank 502.

According to the test apparatus 10 according to the present modified example, the defective cells detected from each of the plurality of memory banks 502 can be detected for each IO terminal 512 and for each block separately. Therefore, the number of defective cells calculated for each block calculated by the test apparatus 10 according to the present modification is determined by the remedy in the memory repair for the memory under test 500 having a repair block for each IO terminal. It can be used for calculation.

8 shows the configuration of the test apparatus 10 according to the second modification of the present embodiment together with the memory under test 500. Since the test apparatus 10 which concerns on this modification is employ | adopted substantially the same structure and function as the member of the same code | symbol shown in FIG. 1, it abbreviate | omits description except the following difference.

The defective cell number detection circuit 16 according to the present modification includes an update unit 60 in place of the defective count register 20 and the write unit 28. The defective counting unit 24 according to the present modification counts the number of defective cells detected by the detecting unit 22 sequentially for each page.

The update unit 60 includes an address conversion unit 48 and an update processing unit 64. The update processing unit 64 sequentially counts the number of defective cells stored in the defective count memory 12 in the memory bank 502 and the blocks corresponding to the pages sequentially by page. Update to the value increased by the number of cells. Thereby, according to the test apparatus 10, the memory area in the defective count memory 12 can be used, and the number of defective cells can be counted.

In addition, the bad count unit 24 reads the number of bad cells stored in the bad count memory 12 for the memory bank 502 and the block corresponding to the target page for counting the number of bad cells as an example. The number of defective cells may be counted as an initial value using the number of defective cells read out. In this case, the update processing unit 64 in the update unit 60 overwrites the defective count memory 12 with the number of defective cells counted for the target page.

In addition, the defective counting unit 24 may count the number of defective cells of the target page by setting the initial value to zero. In this case, the update processing unit 64 of the update unit 60 reads out the number of bad cells stored for the memory bank 502 and the block corresponding to the target page from the bad count memory 12, and the bad count unit 24 The number of defective cells counted by "

9 shows the configuration of the test apparatus 10 according to the third modification of the present embodiment together with the memory under test 500. Since the test apparatus 10 which concerns on this modification adopts the structure and function substantially the same as the member of the same code | symbol shown in FIG. 8, description is abbreviate | omitted except a difference hereafter.

The defective cell number detection circuit 16 according to the present modification includes the detection unit 22, the first defective count unit 24-1, the second defective count unit 24-2, and the update unit 60. Has The first failure counting unit 24-1 and the second failure counting unit 24-2 alternately count the number of defective cells detected by the detection unit 22 for each page.

The update processing unit 64 of the update unit 60 stores the pages that have already been counted by the first bad count unit 24-1 in the memory banks 502 and blocks corresponding to the pages. On the other hand, update processing is performed to update the number of defective cells stored in the defective count memory 12 to a value increased by the number of defective cells counted for the page by the first defective count unit 24-1. Further, the second defective counting unit 24-2 is in parallel with the updating process of the number of defective cells counted by the first defective counting unit 24-1 by the updating processing unit 64 of the updating unit 60. The number of defective cells detected for the next page is counted.

Similarly, the update processing unit 64 of the update unit 60 performs a memory bank 502 corresponding to the page for a page that has already been counted by the second bad count unit 24-2. ) And update the number of defective cells stored in the defective count memory 12 with respect to the block to a value increased by the number of defective cells counted for the page by the second defective counting unit 24-2. Perform the process. Further, the first failure counting unit 24-1 performs the update processing of the number of defective cells counted by the second failure counting unit 24-2 by the update processing unit 64 of the updating unit 60. The number of defective cells detected for the next page is counted.

According to the defective cell number detection circuit 16 according to the present modified example, even when a predetermined time or more is required for the update processing by the updater 60, data is continuously read from the memory under test 500. I can ship it. Thus, according to the test apparatus 10 according to the present modification, the number of defective cells can be detected at high speed for each bank and each block from the memory under test 500 having a plurality of banks.

As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range of description in the said embodiment. It is apparent to those skilled in the art that various changes or improvements can be added to the above embodiments. It is evident from the description of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

Claims (5)

A test apparatus for testing a memory under test having a plurality of memory banks, A bad count memory for storing the number of bad cells per memory bank and per block; A bad count register for storing the number of bad cells detected in the block to be tested for each memory bank; A memory reading unit which sequentially reads some pages in the block to be tested from each memory bank in sequence; A detection unit for detecting defective cells in each page based on a result of comparing data read from each page by the memory reading unit with an expected value; A bad count unit for increasing a value of the bad count register corresponding to a memory bank including a page where bad cells are detected by the number of detected bad cells; And The number of defective cells stored in the defective count register corresponding to the memory banks that have completed the failure detection of each page in the block to be tested is written into the storage area corresponding to the corresponding block to be tested of the corresponding memory bank in the defective count memory. Writing unit; Test device comprising a. A test apparatus for testing a memory under test having a plurality of memory banks, A defective count memory for storing the number of defective cells per memory bank and every block; A memory reader for sequentially reading some pages from each memory bank; A detection unit for detecting defective cells in each page based on a result of comparing data read from each page by the memory reading unit with an expected value; A defective counting unit for counting the number of defective cells sequentially detected for each page; And An updating unit which sequentially updates the number of defective cells stored in the defective count memory with respect to the memory banks and blocks corresponding to the corresponding pages for each page to the value increased by the number of defective cells counted by the defective counting unit; Test device comprising a. The method of claim 2, The bad count unit reads the number of bad cells stored in the bad count memory for the memory bank and block corresponding to the target page for counting the number of bad cells, and sets the number of bad cells as an initial value. Count the numbers, The updating unit overwrites the defective count memory with the number of defective cells counted for a target page. tester. The method of claim 2, The defective counting unit counts the number of defective cells of the target page with an initial value of 0, The updating unit reads the number of defective cells stored for the memory bank and the block corresponding to the target page from the defective count memory, adds the number of the defective cells counted by the defective counting unit, and writes them to the defective count memory. Reverted, tester. The method of claim 2, A first defective count unit and a second defective count unit; The updating unit may be configured to determine the number of defective cells stored in the defective count memory for a memory bank and a block corresponding to the corresponding page for a page that has already been counted by the first defective counter. An update process for updating to a value increased by the number of defective cells counted for the page by the defective counting unit, The second defective counting unit counts the number of defective cells detected for the next page in parallel with the update processing by the updating unit. tester.

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