KR101014771B1 - Apparatus and method for processing high speed signal - Google Patents

Abstract

PURPOSE: An apparatus and a method for processing a high speed signal are provided to efficiency process high speed signal by changing processing speed according to the outside and inside of a programmable logic device. CONSTITUTION: A high speed signal processing apparatus generates sampling data by sampling an analog signal(710) The high speed signal processing apparatus processes sampling data in order to make the transfer rate of sampling data less than a first-transfer rate. The high speed signal processing apparatus processes sampling data in order to enhance the transfer rate of sampling data over a second transfer rate(720) The high speed signal processing apparatus changes the outputted sampling data into an analog signal(730).

Description

Apparatus and method for processing high speed signal

The present invention relates to a high speed signal, and more particularly, to a method for processing a high speed signal.

The conventional high speed signal processing apparatus converts a given analog signal into digital data, processes the converted digital data by a programmable logic device (PLD) in a predetermined manner, and outputs the processed digital data.

Where a given analog signal is a high speed signal, there are many limitations in processing the digital data at a high speed within the high speed signal processing apparatus outside the programmable logic device, but at the same time in the high speed signal processing device.

A first technical problem to be achieved by at least one embodiment of the present invention is to provide a high speed signal processing apparatus capable of efficiently processing a high speed signal by processing at a high speed outside the programmable logic device (PLD) and lowering the processing speed inside the programmable logic device (PLD). To provide.

A second technical problem to be achieved by at least one embodiment of the present invention is to provide a high speed signal processing method capable of efficiently processing a high speed signal by processing at a high speed outside the programmable logic device (PLD) and lowering the processing speed inside the programmable logic device (PLD). To provide.

In order to achieve the first object, the high-speed signal processing apparatus according to at least one embodiment of the present invention comprises an analog-to-digital converter for sampling the analog signal to generate sampling data; The sampling data is processed and stored so that the transmission rate of the sampling data is lower than the first rate, the stored sampling data is read, and the read sampling rate is increased so that the transmission rate of the read sampling data is higher than the second rate. A programmable logic device that processes and outputs data; And a digital analog converter for converting the output sampling data into an analog signal.

The programmable logic device may include: a first dual data rate processor (first DDR) for processing the sampling data such that the transmission rate of the sampling data is lowered below the first rate; A memory for storing sampling data processed by the first dual data rate processor; And a second dual data rate processor configured to process the read sampling data so that the transmission rate of the read sampling data read and stored is higher than a second speed.

The first dual data rate processor is configured to receive and add the sampling data on each of the rising and falling edges of a predetermined clock and to transfer the added result at the next rising edge of the clock, and the memory stores the first dual data rate. Store the sampling data transmitted from the processing unit.

In this case, the second dual data rate processor receives the read sampling data and transmits the half at the rising edge of the predetermined clock and the other half at the falling edge.

Here, each of the first dual data rate processing unit and the second dual data rate processing unit may be implemented in multiple stages.

The method of claim 1, wherein the analog-to-digital converter comprises a demux for demuxing the sampling data.

Here, the digital analog converter muxes the sampling data and converts the muxed result into the analog signal.

According to at least one embodiment of the present invention, a high speed signal processing method includes: (a) sampling an analog signal to generate sampling data; (b) process and store the sampled data so that the transfer rate of the sampled data is lower than the first rate, read the stored sampled data, and increase the transfer rate of the read sampled data above the second rate. Processing and outputting the read sampling data; And (c) converting the output sampling data into an analog signal.

Here, the step (b) may include (b1) processing the sampling data such that the transmission rate of the sampling data is lowered below the first rate; (b2) storing the sampling data processed by step (b1); And (b3) processing the read sampling data such that the stored sampling data is read and the transfer rate of the read sampling data becomes higher than a second speed.

Here, the step (b1) receives and adds the sampling data at each of the rising and falling edges of the predetermined clock and transmits the added result at the next rising edge of the clock, and the step (b2) is performed in the step (b1). Stores the sampling data sent from.

Here, the step (b3) receives the read sampling data and transmits the half on the rising edge of the predetermined clock and the other half on the falling edge.

Here, step (a) demuxes the sampling data and outputs the demuxed result.

Here, the step (c) muxes the sampling data and converts the muxed result into the analog signal.

The high speed signal processing apparatus and method according to at least one embodiment of the present invention may process the high speed signal efficiently by lowering the processing speed inside the programmable logic device while processing at a high speed outside the programmable logic device (PLD).

1 is a reference diagram for explaining a function of a high speed signal processing apparatus according to at least one embodiment of the present invention.
2 is a block diagram illustrating a high speed signal processing apparatus according to at least one embodiment of the present invention.
FIG. 3 is a first reference diagram for describing an operation of the programmable logic device illustrated in FIG. 2.
FIG. 4 is a second reference diagram for describing an operation of the programmable logic device illustrated in FIG. 2.
5 is a timing diagram for describing an operation of the first dual data rate processor 310 illustrated in FIGS. 3 and 4.
6 is a timing diagram for describing an operation of the second dual data rate processor 320 illustrated in FIGS. 3 and 4.
7 is a flowchart illustrating a high speed signal processing method according to at least one embodiment of the present invention.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that illustrate preferred embodiments of the present invention and the accompanying drawings.

Hereinafter, a high speed signal processing apparatus and method according to at least one embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a reference diagram for explaining a function of a high speed signal processing apparatus according to at least one embodiment of the present invention. As shown in FIG. 1, PA means pulse amplitude and NBW means bandwidth of noise.

As shown in FIG. 1, the high speed signal processing apparatus according to at least one embodiment of the present invention may perform a time delay as a time modulation for a given analog signal (110), and perform a frequency shift as a frequency modulation. 120 may be performed, and frequency shift and noise addition may be performed as frequency modulation (130).

FIG. 2 is a block diagram illustrating a high speed signal processing apparatus according to at least one embodiment of the present invention, which includes an analog-to-digital converter (ADC) 210 and 220 and a programmable logic device (PLD) ( 232), digital-to-analog converter (DAC) (234, 244), balun (216, 226, 240, 250), differential amplifiers (218, 228, 242, 252), divider (230, 254).

In the present specification, a radio frequency (RF) signal includes an in-phase (I) signal and a quadrature (Q) signal, and the differential amplifier 218 receives an I signal of RF and the differential amplifier 228 receives a Q signal of RF. In response, the differential amplifier 242 outputs an I signal of RF and the differential amplifier 252 outputs a Q signal of RF.

The analog-to-digital converter (ADC) 210 samples the analog signal (I signal) to generate sampling data. In this specification, for convenience of description, it is assumed that the sampling clock fs of the analog-to-digital converter 210 is 2.56 GHz.

The analog-to-digital converter 210 may include a demux 214 for demuxing sampling data. That is, the ADC 212 samples the analog signal (I signal) to generate sampling data, and the demux 214 (assuming 1: 4 DEMUX in this specification for convenience of description) is one-fourth of the sampling rate. Send it. Since the sampling clock fs is assumed to be 2.56 GHz, the speed at which the demux 214 transfers to the programmable logic device 232 to be described later is 640 MHz.

The number of bits of one sample generated by the analog-to-digital converter 210 is assumed to be 4 bits for convenience of explanation. Accordingly, one bit string transmitted to the programmable logic device 232 described later by the demux 214 is 16 bits.

The sampling clock fs input to the analog-digital converter 210 is a clock input from a balun (BALunce to UNbalance) 216, which is a clock input of the balun 216 from the divider 230.

The analog signal input to the analog-digital converter 210 is an RF signal output from the differential amplifier 218.

As shown in FIG. 2, the ADC DCLK refers to a clock given from the analog-to-digital converter 210 to the programmable logic device 232, and the programmable logic device 232 collects sampling data using the DCLK. For convenience of explanation, DCLK is fs / 8, or 320 MHz.

Unlike the analog-to-digital converter 210, the balun 216, and the differential amplifier 218 described above operating on an I signal, the analog-to-digital converter 220, the balun 226, and the differential amplifier 228 are different. Is different in that it operates with respect to the Q signal, the operation of the analog-to-digital converter 220, the balun 226, the differential amplifier 228 is analog-to-digital converter 210, the balun 216, the differential amplifier ( 218).

The programmable logic device (PLD) 232 processes and stores the sampling data so that the transfer rate of the sampled data is lower than the first rate, reads the stored sampled data, and transfers the read rate of the sampled data to the second rate. The read sampling data is processed so as to be higher than above to generate reconstructed data and output the reconstructed data. Here, each of the first speed and the second speed is a preset value and is a setting. The time modulation, frequency modulation, and the like mentioned above with reference to FIG. 1 are performed by the programmable logic device 232.

The digital analog converter (DAC) 234 converts sampling data input from the programmable logic device 232 into an analog signal (I signal). As previously assumed, the recovery clock of the digital-to-analog converter 234 is 2.56 GHz.

The digital analog converter 234 may include a mux 236 for muxing the sampling data and converting the muxed result into an analog signal. In other words, the mux 236 (assuming 4: 1 MUX for convenience of explanation herein) transmits data at a quarter of the reconstruction rate, and the DAC 238 converts the transmitted sampling data into an analog signal. . Since the recovery clock is assumed to be 2.56 GHz, the speed of the programmable logic device 232 to the digital-to-analog converter 234 is 640 MHz.

The number of bits of one sample in the digital-to-analog converter 234 is assumed to be 6 bits for convenience of description below. Accordingly, one bit string transmitted by the programmable logic device 232 to the digital-to-analog converter 234 is 24 bits.

The recovery clock input to the digital-to-analog converter 234 is a clock input from the balun 234, which is a clock received by the balun 234 from the divider 254.

The digital analog converter 234 outputs the converted analog signal to the differential amplifier 242, and the differential amplifier 242 outputs an RF signal (I signal).

As shown in FIG. 2, the DAC DCLK refers to a clock provided from the digital analog converter 234 to the programmable logic device 232, and the programmable logic device 232 converts the restored data to the digital analog converter 234 using DCLK. To pass). At this time, DCLK is fs / 8, that is, 320 MHz.

Unlike the above-described digital analog converter 234, the balun 240, and the differential amplifier 242 operate on the I signal, the digital analog converter 244, the balun 250, the differential amplifier 252 The operation of the digital analog converter 234, the balun 240, and the differential amplifier 242 is only different from that of operating the Q signal. The operation of the digital analog converter 244, the balun 250, and the differential amplifier 252 is different. Same as the operation contents of).

3 is a first reference diagram for describing an operation of the programmable logic device illustrated in FIG. 2, and FIG. 4 is a second reference diagram for explaining an operation of the programmable logic device illustrated in FIG. 2. Specifically, FIG. 3 is a reference diagram for describing a time modulation operation of a programmable logic device, and FIG. 4 is a reference diagram for explaining a frequency modulation operation of a programmable logic device.

The first double data rate processor (first double data rate) 310 processes the sampled data such that the transfer rate of the sampled data input to the programmable logic device 232 is lower than the first rate.

The sampling data processed by the first dual data rate processor 310 is amplitude data, and the phase converter 312 converts the amplitude data into phase data.

A memory (SIME: Signal Memory) 314 stores sampling data as the converted phase data.

The phase modulator 316 reads sampling data from the memory 314 and modulates the phase of the read sampling data.

The sampling data output from the phase modulator 316 is phase data, and the amplitude converter 318 converts the phase data into amplitude data and outputs sampling data as amplitude data.

The second dual data rate processing unit 320 reads the sampled data so that the transfer rate of the sampling data input from the phase modulator 316 (finally, the sampling data read from the memory 314) becomes higher than the second rate. To generate the restored data and output it.

The SIME controller 322 controls the operation of the memory 314.

The serial communication control unit 324 issues commands to control the operation of the programmable logic device 232.

The operation state information storage unit 326 stores state information of the programmable logic device 232, and the serial communication control unit 324 operates according to the state information.

The bit controller 328 checks whether the serial communication controller 324 operates normally.

The modulation control register 330 interprets the command of the serial communication controller 324 and controls the operation of the time modulator 332 or the frequency modulator 334 accordingly.

The time modulator 332 performs time modulation, and the frequency modulator 334 performs frequency modulation.

The frequency modulator 334 receives the phase correction information from the phase corrector 336 and transfers the phase correction information to the phase modulator 316. Here, the phase correction is performed irrespective of the frequency modulation, and such phase correction information is joined to the sampling data by the phase modulator 316 through the frequency modulator 334.

In FIG. 3 and FIG. 4, ⓐ means a flow of sampling data.

In FIG. 3, ⓑ means the flow of a control signal during time modulation, and accordingly, the SIME controller 322 controls the memory 314 to perform a time delay.

In FIG. 4, ⓒ means the flow of control signals during frequency modulation, and ⓓ in FIG. 4 means the flow of phase correction information.

5 is a timing diagram for describing an operation of the first dual data rate processor 310 illustrated in FIGS. 3 and 4.

The first dual data rate processor (first DDR) 310 receives sampling data at each of a rising edge and a falling edge of a predetermined clock, adds them to each other, and adds the added result to the clock. Transmit on the next rising edge. The sampling data stored in the memory 314 is sampling data transmitted from the first dual data rate processing unit 310 (more precisely, the result of phase shifting the transmitted sampling data).

FIG. 5A means a sampling clock fs, and FIG. 5B means a DCLK given by the analog-to-digital converter 210 to the programmable logic device (PLD) 232. (c) refers to a bit string that the analog-to-digital converter 210 provides to the programmable logic device (PLD) 232. As described above, one bit string is composed of 16 bits in FIG.

FIG. 5D illustrates sampling data (FIG. 5C) of the first dual data rate processor (first DDR) 310 at each of the rising and falling edges of the predetermined clock (FIG. 5B). Are added to each other and the added result is transmitted on the next rising edge of the clock (Fig. 5 (b)), showing the transmission waveform at this time.

FIG. 5F illustrates that the first dual data rate processing unit (first DDR) 310 samples sampling data on each of the rising and falling edges of the predetermined clock (FIG. 5E). Are added to each other and the added result is transmitted on the next rising edge of the clock (Fig. 5 (e)), showing the transmission waveform at this time.

5D and 5E illustrate internal signals of the first dual data rate processing unit (first DDR) 310, and FIG. 5C illustrates a first dual data rate processing unit (first DDR) 310. ) Shows sampling data (I signal, one bit string consisting of 16 bits), and FIG. 5F shows sampling data I finally outputted by the first dual data rate processing unit (first DDR) 310. Signal, one bit string consists of 64 bits).

After converting the waveform of FIG. 5 (c) to the waveform of (d) of FIG. 5 through one DDR, the number of data bits is doubled and the transmission speed is 1/2 times. The waveform of (d) is converted from the waveform of (f) to the waveform of (f) of FIG. As such, the first dual data rate processor (first DDR) 310 may be implemented in multiple stages.

FIG. 5 is only illustrated for the I signal for convenience of description, and the Q signal may also be represented as a timing diagram as shown in FIG. 5.

6 is a timing diagram for describing an operation of the second dual data rate processor 320 illustrated in FIGS. 3 and 4.

FIG. 6 (a) shows the result of dividing the DCLK given to the programmable logic device 232 by the digital-to-analog converter 234 by 90 degrees, dividing the result by 2, and then shifting the output by 270 degrees. Has a frequency. This is a signal inside the second dual data rate processor 320.

6B illustrates sampling data input to the second dual data rate processing unit (second DDR) 320. As shown in (f) of FIG. 5, the frequency of the sampling data is 160 MHz.

The second dual data rate processor (second DDR) 320 reads sampling data read from the memory 314 (more strictly, a result of performing phase modulation and amplitude conversion on the read sampling data) (Fig. 6). (B)) to transmit half (1/2) on the rising edge of the predetermined clock (Fig. 6 (a)) and the other half (1/2) on the falling edge (Fig. 6 (d)). ).

Similarly, the second dual data rate processing unit (second DDR) 320 receives sampling data (Fig. 6 (d)) and half (1/2) at the rising edge of the predetermined clock (Fig. 6 (c)). Transmit and transmit the other half (1/2) on the falling edge (Fig. 6 (f)).

6 (b) is converted from waveform (b) of FIG. 6 to waveform (d) of FIG. 6, and in this process, the number of data bits is 1/2 times and the transmission speed is doubled. The waveform of (d) was converted from the waveform of (f) to the waveform of (f) of FIG. As such, the second dual data rate processor (second DDR) 320 may be implemented in multiple stages.

6 (g) means a clock given to the digital-to-analog converter 234 in the balloon 240.

FIG. 6 is shown only for the I signal for convenience of description, and the Q signal may also be represented as a timing diagram as shown in FIG. 6.

7 is a flowchart illustrating a high speed signal processing method according to at least one embodiment of the present invention.

The high speed signal processing apparatus according to at least one embodiment of the present invention generates sampling data by sampling an analog signal (operation 710).

After operation 710, the high speed signal processing apparatus according to at least one embodiment of the present invention processes and stores the sampling data so that the transmission rate of the sampling data is lower than the first speed, reads the stored sampling data, The read sampling data is processed and output so that the transfer rate of the read sampling data becomes higher than the second speed (step 720).

After operation 720, the high speed signal processing apparatus according to at least one embodiment of the present invention converts the output sampling data into an analog signal (operation 730).

So far, the present invention has been described with reference to the preferred embodiments. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

Claims (13)

An analog-digital converter configured to sample the analog signal and generate sampling data;
The sampling data is processed and stored so that the transmission rate of the sampling data representing the transmission rate with respect to the number of bits of the sampling data is lower than the first rate, the stored sampling data is read, and the transmission rate of the read sampling data A programmable logic device that processes and outputs the read sampling data such that the read rate is higher than or equal to a second speed; And
A digital analog converter for converting the output sampling data into an analog signal
The programmable logic device includes: a first dual data rate processor configured to process the sampling data such that a transmission rate of the sampling data is lowered below a first rate; A memory for storing sampling data processed by the first dual data rate processor; And a second dual data rate processor configured to process the read sampling data such that the stored sampling data is read and the transfer rate of the read sampling data becomes higher than a second rate, wherein the first dual data rate processor is fixed. And receiving and adding the sampling data on each of the rising and falling edges of the clock and transmitting the added result at the next rising edge of the clock. delete delete The method according to claim 1,
The second dual data rate processing unit receives the read sampling data and transmits half at the rising edge of the predetermined clock and transmits the other half at the falling edge. The method according to claim 1,
Each of the first dual data rate processing unit and the second dual data rate processing unit is implemented in multiple stages. The apparatus of claim 1, wherein the analog-to-digital converter comprises a demux for demuxing the sampling data. The high speed signal processing apparatus of claim 1, wherein the digital analog converter muxes the sampling data and converts the muxed result into the analog signal. (a) sampling the analog signal to generate sampling data;
(b) processing and storing the sampling data so that the transmission rate of the sampling data representing the transmission rate with respect to the number of bits of the sampling data is lower than the first rate, reading the stored sampling data, and reading the sampling data Processing and outputting the read sampling data so that the transmission rate of the signal becomes higher than the second rate; And
(c) converting the output sampling data into an analog signal
Wherein (b) comprises: (b1) processing the sampling data such that the transmission rate of the sampling data is lowered below the first rate; (b2) storing the sampling data processed by step (b1); And (b3) processing the read sampling data such that the stored sampling data is read and the transfer rate of the read sampling data becomes higher than a second speed, wherein step (b1) includes rising edges of a predetermined clock. And receiving and adding the sampling data at each of the falling edges and the falling edges, and transmitting the added result at the next rising edge of the clock. delete delete The method of claim 8,
The step (b3) is a high-speed signal processing method, characterized in that for receiving the read sampling data and transmitting half on the rising edge of the predetermined clock and the other half on the falling edge. The method of claim 8, wherein the step (a) demuxes the sampling data and outputs a demuxed result. The method of claim 8, wherein step (c) muxes the sampling data and converts the muxed result into the analog signal.

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