KR101009675B1 - Line On Glass Type Liquid Crystal Display Device - Google Patents

Abstract

The present invention relates to a line-on-glass type liquid crystal display device having an ESD protection pattern on the upper part of the LOG wiring, which has a strong structure against external ESD. The thin film transistor and the pixel electrode are disposed in the pixel area defined by the gate wiring and the data wiring. And an LOG display for supplying signals of external drive integrated circuits, which are formed in a line-on-glass manner to the image display area, to be provided on the outside of the image display area, and overlapped on the LOG wiring. It is characterized by including the ESD prevention pattern.

LOG wiring, ESD prevention pattern

Description

Line On Glass Type Liquid Crystal Display Device

1 is a plan view of a line-on glass liquid crystal display device according to the prior art.

FIG. 2 is a sectional view taken along line II ′ of FIG. 1. FIG.

3 is a plan view of a line-on glass liquid crystal display device according to the present invention;

4A to 4C are cross-sectional views of a process taken along the line II-II ′ of FIG. 3.

* Explanation of symbols on the main parts of the drawings

152: image display area 152: non-display area

161: gate wiring 162: data wiring

163: gate pad 164: data pad

170: gate drive IC 180: data drive IC

181: gate TCP 182: data TCP

190: data PCB 195: LOG wiring

196: Signal transmission line 198: ESD prevention pattern

199: dummy line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD), and more particularly, to a line on glass type liquid crystal display device having a structure resistant to electrostatic discharge (ESD).

Liquid crystal display devices have a high contrast ratio, are suitable for gray scale display and moving image display, and have low power consumption.

The liquid crystal display device includes a color filter array substrate having a color filter layer for implementing colors, a TFT array substrate opposed to the color filter array substrate, a liquid crystal layer encapsulated between the two substrates, and the TFT array substrate. It is composed of a driving circuit section for driving to display an image by various external signals.

The TFT array substrate may include a gate line and a data line for transmitting various signals to each pixel defined by crossing perpendicularly to each other, a thin film transistor (TFT) for selectively applying a signal to the pixel electrode, and a unit. A storage capacitor is formed to keep the charge state until the pixel region is next addressed.

The driving circuit unit includes a gate drive for driving the gate wires, a data drive for driving the data wires, a timing controller for controlling the gate drive and the data drive, and various types of liquid crystal display devices. It is provided with a power supply for supplying the driving voltages.                         

The timing controller controls driving timing of the gate drive and the data drive and supplies pixel data signals to the data drive, and the power supply unit uses the input power to supply a common voltage (Vcom) required by the liquid crystal display device. ), And drive voltages such as a gate high voltage Vgh and a gate low voltage Vgl.

The gate drive sequentially supplies the scanning signals to the gate lines to sequentially drive each pixel by one line, and the data drive applies the pixels to each of the data lines whenever a scanning signal is supplied to any one of the gate lines. Supply the voltage signal.

Accordingly, the liquid crystal display device displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

At this time, the data drive and the gate drive are integrated into a plurality of integrated circuits (ICs).

As described above, each of the integrated data drive IC and the gate drive IC may be mounted on a tape carrier package (TCP) and connected to a liquid crystal panel according to a method of packaging the liquid crystal display device. There is a chip on glass (COG) method in which a drive IC is directly mounted on a TFT array substrate.

Specifically, the drive ICs connected to the liquid crystal panel in a TAP manner through TCP supply control signals and DC voltages input from the outside through signal lines mounted on a printed circuit board (PCB) connected to TCP. Receive.                         

The drive ICs mounted on the liquid crystal panel in the COG method are connected to the line on glass method in which the signal lines are mounted on the lower glass substrate, and receive control signals and driving voltages from the timing controller and the power supply unit.

Recently, even when the drive ICs are connected to the liquid crystal panel by the TAB method, the liquid crystal display device is further thinned by adopting the LOG method and removing the PCB. In particular, the gate PCB is removed by forming the signal lines connected to the gate drive ICs requiring relatively few signal lines on the glass substrate in a LOG method. That is, the TAB gate drive ICs are connected in series through signal lines mounted on the lower glass substrate of the liquid crystal panel and simultaneously receive control signals and driving voltage signals.

Hereinafter, the TFT array substrate structure of the liquid crystal display device by the LOG method will be described in detail.

1 is a plan view of a line-on glass liquid crystal display device according to the prior art, and FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

As shown in FIG. 1, the liquid crystal display device in which the gate PCB is removed by using the LOG signal signals has a plurality of data connected between the liquid crystal panel 50 and the liquid crystal panel 50 and the data PCB 84. A plurality of gate TCP 81 connected to the TCP 82, the other side of the liquid crystal panel 50, a data drive IC 80 mounted on each of the data TCP 82, and a gate TCP 81 respectively. The gate drive IC 81 is mounted.

In this case, the liquid crystal panel 50 is divided into an image display area 52 inside the dotted line and an non-display area 54 outside the dotted line.

A plurality of gate wirings 61 and data wirings 62 are formed in the image display area 52. The gate wirings 61 and the data wirings 62 intersect to define pixel regions.

A thin film transistor (TFT) is formed at a portion where the gate line 61 and the data line 62 cross each other, and a thin film transistor (TFT) is formed in each pixel area and is connected to the drain electrode 62b of each thin film transistor through a passivation layer. The pixel electrode 10 is formed, and an image is displayed by switching each of the thin film transistors. At this time, the thin film transistor is composed of a gate electrode 61a, a gate insulating film 13, a semiconductor layer 14, and source / drain electrodes 62a and 62b (see Fig. 2).

Next, in the non-display area 54, gate pads and data pads 63 and 64 extending from the gate wiring 61 and the data wiring 62 are formed, and the gate pads and the data pads 63 and 64 are formed. One end is connected to the gate drive IC 70 and the data drive IC 80, respectively.

The gate drive IC 70 and the data drive IC 80 are connected to an external data PCB 90. In this case, the data drive IC 80 is connected to the data PCB 90 through the TAP method, and the gate drive IC 70 is connected to the data PCB 90 by the LOG wiring 95. The data PCB 190 is provided with a plurality of devices such as integrated circuits on a substrate to supply various signals for driving the liquid crystal display.                         

The LOG wiring 95 is supplied from a power supply unit such as a gate low voltage signal VGL, a gate high voltage signal VGH, a common voltage VCOM, a power signal VCC, and a ground voltage signal GND. It is composed of signal lines for supplying gate control signals supplied from a timing controller, such as DC voltage signals, a gate enable signal GOE, a gate shift clock signal GSC, and a gate start pulse GSP.

In particular, the LOG wiring 95 is formed directly on the substrate 11, as shown in FIG. 2, and is formed at the same time as the gate electrode 61a of the image display area. Various signals flowing through the LOG wiring 95 are transmitted to all the gate drive ICs 70 through the signal transmission line 96 of the gate TCP 81.

However, the liquid crystal display device according to the related art as described above has a problem that it is vulnerable to ESD.

That is, as shown in FIG. 2, when the ESD is applied to the non-display area, the flicker phenomenon of flickering of the image is generated due to the influence on the gate control signal and the gate power signals transmitted through the LOG wiring 95.

The ESD is injected into the outside and is induced in the aluminum top case surrounding the non-display area, which may adversely affect the LOG wiring at an undesired moment.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a line-on-glass type liquid crystal display device having a strong structure against external ESD by overlapping the ESD prevention pattern on the upper part of the LOG wiring.

The line-on-glass type liquid crystal display device of the present invention for achieving the above object is an image display region having a thin film transistor and a pixel electrode in a pixel region defined by a gate wiring and a data wiring, and an outer portion of the image display region. It is formed in a line-on-glass manner and comprises a LOG wiring for supplying signals of external drive integrated circuits required for driving to the image display area, and an ESD protection pattern overlapping the upper portion of the LOG wiring.

That is, the liquid crystal display according to the present invention is provided by a line on glass method in which a LOG wiring is provided on a substrate to transmit various gate power signals and gate control signals to a gate drive IC through the LOG wiring. It characterized in that it further comprises an ESD prevention pattern.

In other words, the ESD protection pattern is overlapped on top of the LOG wiring to prevent ESD from being applied directly to the LOG wiring.

The ESD protection pattern is connected to a power supply of the data PCB so that the ground voltage GND flows, and the ESD protection patterns provided between the gate TCPs are connected to each other by a dummy line of the gate TCP.

Since the ESD prevention pattern is formed at the same time as the data line of the image display area, no additional process is required.

Hereinafter, a line on glass type liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.                     

3 is a plan view of a line-on glass liquid crystal display device according to the present invention, and FIGS. 4A to 4C are cross-sectional views of the process on the line II-II 'of FIG. 3.

The TFT array substrate 150 on which the thin film transistor is formed is divided into an image display area 152 and a non-display area 154, as shown in FIG. 3, and transmits an image signal to the image display area 152. A data line 162, a gate line 161 perpendicular to the data line 162 to define each pixel, and a scanning signal, and an intersection point of the gate line 161 and the data line 162. And a thin film transistor (TFT) formed at the gate electrode, a gate insulating film, a semiconductor layer, and a source / drain electrode, and a pixel electrode 110 connected to the thin film transistor with a protective film therebetween.

In the non-display area 154, gate pads and data pads 163 and 164 extending from the gate line 161 and the data line 162 are formed, respectively. The gate pads and the data pads 163 and 164 are formed. One end of the Ns) is connected to the gate drive IC 170 and the data drive IC 180 attached to the TFT array substrate 150, respectively. That is, the gate pad 163 is connected to the gate drive IC 170, and the data pad 164 is connected to the data drive IC 180.

In this case, the data drive IC 180 is connected to the data PCB 190 through the data TCP 182, and the gate drive IC 170 is connected to the data PCB 190 through the LOG wiring 195. Various signals are received from the data PCB 190.

At this time, the LOG wiring 195 is formed at the same time as the gate wiring 161 of the image display area, and the ESD protection pattern 198 overlaps the insulating film between the LOG wiring 195. Here, the ESD prevention pattern 198 is provided to block the direct application of ESD to the LOG wiring 195, and serves as a lightning rod.

The ESD prevention pattern 198 is provided on the same layer as the data line 162 of the image display area, and is disposed between the gate TCPs 181 on which the LOG line 195 is formed. In order to allow the GND voltage to flow through the ESD prevention pattern 198, the ESD protection pattern 198 is connected to the power supply of the data PCB 190 and the dummy line 199 of the gate TCP 181 is used as a medium for ESD protection of the gate pad region. The pattern 198 is connected.

Then, the ESD is blocked by the ESD prevention pattern so that damage is not applied to the LOG wiring through which various gate control signals and gate power signals flow.

In addition, since the GND voltage must flow through the ESD protection pattern 198, the ESD protection pattern 198 must be formed of a conductive material.

For reference, the LOG wiring 195 transfers gate signals to the gate drive IC 170 through the signal transmission line 196 of the gate TCP 181. Since the LOG wiring 195 is provided on the same layer as the gate wiring 161 of the image display area, the insulating film provided between the LOG wiring 195 and the ESD protection pattern 198 becomes a gate insulating film.

Hereinafter, the method of manufacturing the liquid crystal display device will be described in detail.

First, as shown in FIG. 4A, metals such as aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), and molybdenum-tungsten (MoW) having a low specific resistance on the thin film array substrate 111 may be used. After the deposition, the gate patterns 161, the gate electrodes 161a, the gate pads 163 of FIG. 3, and the LOG wirings 195 are formed.

The LOG wiring 195 is a gate power source supplied from a power supply such as a gate low voltage signal VGL, a gate high voltage signal VGH, a common voltage VCOM, a power signal VCC, and a ground voltage signal GND. And a plurality of signal lines for supplying gate control signals supplied from the timing controller, such as signals, a gate enable signal GOE, a gate shift clock signal GSC, and a gate start pulse GSP.

Next, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface including the gate wiring 161 by PECVD to form a gate insulating layer 113, and an amorphous surface is formed on the entire surface including the gate insulating layer. Silicon (a-Si: H) is deposited at a high temperature and then patterned to form a semiconductor layer 114 on the gate insulating layer 113 over the gate electrode 161a.

4B, copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), and molybdenum-tungsten (MoW) are formed on the entire surface including the semiconductor layer 114. After depositing a metal, such as a metal, and patterning, a plurality of data lines 162, source / drain electrodes 162a and 162b, data pads 164 of FIG. 3, and an ESD protection pattern 198 are formed.

In this case, the data line 162 crosses the gate line 161 to define a unit pixel, and the source / drain electrodes 162a and 162b are formed at both ends of the semiconductor layer 114, respectively. The ESD protection pattern 198 is formed so that the LOG wiring 195 can be completely overlapped.

Next, as illustrated in FIG. 4C, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface including the source / drain electrodes 162a and 162b, or BCB (Benzocyclobutene) and acrylic system. A protective film 116 is formed by applying an organic insulating material such as a material, and a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited and patterned on the protective film to form the protective film 116. The pixel electrode 110 penetrates and is connected to the drain electrode 162b.

Finally, the gate drive IC 170 and the data drive IC 180 are attached to the ends of the gate pad 163 and the data pad 164 in a TAP manner, and then the gate drive IC 170 and the data drive IC 180 are attached. ) Is connected to the data PCB 190. At this time, the gate drive IC 170 is connected to the data PCB 190 by the LOG wiring 195. At the same time, the ESD protection pattern 198 is connected to the data PCB 190, and the ESD protection pattern 198 between the gate TCP 181 is connected through the dummy line 199 of the gate drive IC 170. . Therefore, the GND voltage of the data PCB 190 flows to the ESD prevention pattern 198 and the dummy line 199 of the gate TCP 181.

As described above, after the thin film transistor array substrate is completed, an ESD of ± 1.5 mA is applied to the non-display area to check whether the damage is caused by the ESD.                     

At this time, since the ESD is blocked by the ESD prevention pattern of the non-display area, no damage is caused to the LOG wiring and flicker does not occur in the image display area.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

The line-on glass liquid crystal display device of the present invention as described above has the following effects.

First, it prevents external ESD from damaging the LOG wiring by overlapping the ESD prevention pattern on the upper part of the LOG wiring, so that it does not affect the various gate control signals and gate power signals flowing in the LOG wiring, so that the image quality is not defective such as flicker. Should be maintained.

In addition, since it can be formed at the same time as the ESD protection pattern data wiring, it is possible to prevent the failure by the ESD without adding a process.

Claims (11)

An image display region in which a thin film transistor and a pixel electrode are provided in a pixel region defined by a gate wiring and a data wiring on a substrate; A LOG wiring formed on the outside of the image display area in a line on glass manner to supply signals of external drive integrated circuits required for driving to the image display area; And an ESD protection pattern formed on the same layer as the data line so as to overlap the upper portion of the LOG line. The method of claim 1, A line on glass type liquid crystal display device, wherein a ground voltage GND flows through the ESD prevention pattern. The method of claim 1, The ESD protection pattern is connected to the power supply of the external drive integrated circuit line-on glass type liquid crystal display device. The method of claim 1, And a gate drive IC connected to the gate wiring end is connected to the external drive integrated circuits by a LOG wiring. The method of claim 1, And the gate drive IC is mounted on the substrate by a gate TCP. The method of claim 5, The ESD protection pattern between the gate TCP is connected by a dummy line of the gate TCP. delete The method of claim 1, And the LOG wiring is provided on the same layer as the gate wiring. The method of claim 1, And an insulating film provided between the LOG wiring and the ESD protection pattern. The method of claim 1, And the external drive integrated circuits are formed on a PCB substrate. The method of claim 1, And a data drive IC connected to an end of the data line is connected to the external drive integrated circuits.

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