KR101007371B1 - Reading non-volatile storage with efficient control of non-selected word lines - Google Patents
Reading non-volatile storage with efficient control of non-selected word lines Download PDFInfo
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- KR101007371B1 KR101007371B1 KR1020087017367A KR20087017367A KR101007371B1 KR 101007371 B1 KR101007371 B1 KR 101007371B1 KR 1020087017367 A KR1020087017367 A KR 1020087017367A KR 20087017367 A KR20087017367 A KR 20087017367A KR 101007371 B1 KR101007371 B1 KR 101007371B1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3481—Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
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Abstract
The present invention includes the steps of maintaining a control gate voltage of an unselected non-volatile storage element at an intermediate voltage; Changing the control gate voltage of the non-selected non-volatile storage element from the intermediate voltage to a read enable voltage from selected non-volatile elements of the group of non-volatile storage elements (eg, NAND string). Processing data (including verifying during programming). The control gate voltage of the selected non-volatile storage element is increased from the standby voltage (different from the intermediate voltage) to the read comparison voltage. While the control gate voltage of the selected non-volatile storage element is the read comparison voltage and the control gate voltage of the non-selected non-volatile storage element is the read enable voltage, Detect information about
Description
The technology described herein relates to non-volatile memory.
Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cell phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most famous non-volatile semiconductor memories.
EEPROMs and flash memories utilize floating gates that reside on a semiconductor substrate and are isolated from channel regions within the semiconductor substrate. This floating gate is located between the source and drain regions. The control gate is provided above this floating gate and is isolated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge held by the floating gate. That is, the minimum value of the voltage that must be applied to the control gate for the transistor to turn on to allow conduction between the source and drain of the transistor is controlled by the level of charge at the floating gate.
When programming a flash memory device, such as an EEPROM device or a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. As electrons accumulate in the floating gate, the floating gate is negatively charged and the threshold voltage of the memory cell increases so that the memory cell is in the programmed state. For more information on programming, see US Patent No. 6,859,397 and No. 6,917,542, which are hereby incorporated by reference in their entirety.
Typically, the program voltage applied to the control gate is applied in a series of pulses. The amplitude of these pulses increases from pulse to pulse by a predetermined step size. In periods between the pulses, verification of the operations is performed. That is, the programming level of each memory cell programmed in parallel is read between the respective programming pulses to determine if the programming level is equal to or greater than the verify level at which the memory cell is to be programmed. One means of verifying programming is to test the conduction between the source and drain of a memory cell at a particular comparison point.
Conduction refers to the "on" state of the device corresponding to the flow of current through the channel of the device. The " off " state indicates that no current flows in the channel between the source and drain. Typically, flash memory cells are conducted when the voltage applied to the control gate is greater than the threshold voltage and not when the voltage applied to the control gate is less than the threshold voltage. By setting the threshold voltage of the memory cell to an appropriate value, the memory cell can be made to conduct or not conduct current for a given set of applied voltages. Thus, by determining whether the memory cell conducts current at a given set of voltages, the state of the memory cell can be determined.
Flash memory cells are erased by increasing the p-well to an erase voltage (eg, 20V) and grounding the word lines of the selected block (or other unit) of memory cells. Source and bit lines are floating. Erase may be performed throughout the memory array, in separate blocks, or in other units of the cell. Electrons move from the floating gate to the p-well region and the threshold voltage becomes negative.
Some flash memory systems use a group of memory cells in an array configured such that a set of bit lines and word lines can be used to address a particular memory cell. In one example, memory cells are grouped into a set of NAND strings. Each NAND string includes a plurality of transistors in series between two selected gates (drain side select gate SGD and source side select gate SGS). In reading and verifying typical operations of a NAND flash memory, the select gates (SGD and SGS) increase to approximately 3V and the unselected word lines increase to a read pass (or enable) voltage (e.g. 5V) so that the transistors It acts as a pass gate. The selected word line is connected to a comparison voltage, where the level of the comparison voltage is specified for each read or verify operation to determine whether the threshold voltage of the associated memory cell has reached that level. The source and p-well are at zero volts. The selected bit lines are precharged to a level of, for example, 0.7V. If the threshold voltage is higher than the verify or read level applied to the selected word line, the potential level of the bit line involved remains at a high level due to the non-conductive memory cell. On the other hand, when the threshold voltage is lower than the verify level or the read level, the potential level of the associated bit line is reduced to a level lower than, for example, 0.5V due to the conductive memory cell. The state of the memory cell is detected by a sense amplifier connected to the bit line.
Typically, word lines are at zero volts between read operations and between program and verify operations. Unselected word lines increase to the read pass voltage at the same time as the selected word line increases to the read comparison voltage. The read pass voltage is generally much greater than the read compare voltage, and the word lines are in close proximity to each other and are quite long, so when the selected word line increases to the read compare voltage (as well as the unselected word lines increase to the read pass voltage) Coupling noise may appear in the selected word line. This coupling initially increases the voltage of the selected word line, but the increased voltage will disappear over time, thus the selected word line stabilizes to the originally intended read comparison voltage. To avoid errors, some systems may need to delay the read process to wait for the selected word line to settle to the intended read compare voltage. This wait slows down the read process and / or the verify process.
One suggestion to improve the coupling problem described above is to slow the ramp-up of the read pass voltage of unselected word lines. However, this solution slows down the readout process and the verification process.
Another solution is to reduce the capacitive coupling of word lines. However, to reduce capacitive coupling of word lines, it is necessary to use more expensive materials or increase die size to increase the space between word lines.
Another solution is to maintain word lines at the read pass voltage between read operations and between program and verify operations. As such, unselected word lines do not need to be ramped up during the read process. The problem with this approach is that changing the word lines from another voltage to a read pass voltage during the programming process (or other process) charge pump to sink a large amount of current to draw the word lines to the read pass voltage. Or another circuit. For example, during the program-verify process, the word lines must change from a boosting voltage (eg 10V) to a read pass voltage (eg approximately 5V). Some charge pumps and other circuits typically found in today's flash memory devices are unable to efficiently sink the current to bring the voltage down to any particular voltage except the standby voltage. New circuits for more complex sequences and voltage detection controls need to be added, which will require additional space in the device as such.
The technology described herein relates to a system for reading data (including verifying during programming) from one or more selected non-volatile storage elements of a group of non-volatile storage elements (eg, a NAND string). The system maintains an intermediate voltage as the control gate voltage of the non-selected non-volatile storage element, and reads the control gate voltage of the non-selected non-volatile storage element from the intermediate voltage. Subsequently change to enable voltage). The control gate voltage of the selected non-volatile storage element increases from the standby voltage (different from the intermediate voltage) to the read comparison voltage. The selected non-volatile storage while the control gate voltage of the selected non-volatile storage element has the read comparison voltage value and the control gate voltage of the non-selected non-volatile storage element has the read enable voltage value. The state of the device is sensed to determine information about the data stored within the selected non-volatile storage device.
One embodiment includes maintaining an intermediate voltage as a control gate voltage of an unselected non-volatile storage element; Changing a control gate voltage of the non-selected non-volatile storage element from the intermediate voltage to a read enable voltage; While the control gate voltage of the non-selected non-volatile storage element is at the read enable voltage, maintaining the read voltage as the control gate voltage of the selected non-volatile storage element; And sensing information about data stored in the selected non-volatile storage device in response to the read voltage that is the control gate voltage of the selected non-volatile storage device.
One embodiment includes increasing a control gate voltage of an unselected non-volatile storage element from an intermediate voltage to a read enable voltage; Increasing the control gate voltage of the selected non-volatile storage element from the standby voltage to the read voltage while increasing the control gate voltage of the non-selected non-volatile storage element from the intermediate voltage to the read enable voltage; And sensing information about data stored in the selected non-volatile storage device in response to the read voltage.
In one exemplary implementation, a non-volatile storage system includes a plurality of non-volatile storage elements, word lines in communication with the plurality of non-volatile storage elements, the plurality of non-volatile storage elements and a plurality of non-volatile storage elements. Bit lines in communication, and one or more management circuits in communication with the plurality of non-volatile storage elements. The one or more management circuits maintain an intermediate voltage at unselected word lines, change the unselected word lines from the intermediate voltage to a read enable voltage, and wherein the unselected word lines are at the read enable voltage. Maintains a read voltage at a selected word line while having a value, and senses information about data stored in a selected non-volatile storage element coupled to the selected word line in response to the read voltage of the selected word line.
1 shows a view from above of a NAND string.
2 is an equivalent circuit diagram for a NAND string.
3 shows a cross section for a NAND string.
4 is a block diagram of one embodiment of a non-volatile memory system.
5 is a block diagram of one embodiment of a non-volatile memory system.
6 is a block diagram of one embodiment of a sense amplifier and latches.
7 is a block diagram of one embodiment of a charge pump and switching circuits.
8 shows an exemplary set of threshold voltage distributions.
9 is a flow chart describing one embodiment of a process for programming a non-volatile memory.
10 is a signal diagram illustrating a portion of one embodiment of a programming process.
11 is a flow chart describing one embodiment of a process for reading a non-volatile memory.
12 is a signal diagram illustrating one embodiment of a process used when reading non-volatile memory.
One example of a non-volatile memory system suitable for implementing the present invention uses a NAND flash memory structure, which includes arranging multiple transistors in series between two select gates. These series transistors and select gates are referred to as a NAND string. 1 is a view from above showing one NAND string. The NAND string shown in FIGS. 1 and 2 includes four
3 provides a cross section for the NAND string described above. As shown in FIG. 3, transistors of the NAND string are formed in the p-
Although FIGS. 1-3 illustrate four memory cells in a NAND string, the use of these four transistors is provided merely as an example. The NAND string used in the techniques described herein may have fewer or more than four memory cells. For example, some NAND strings include eight memory cells, sixteen memory cells, thirty-two memory cells, sixty-four memory cells, and the like. The discussion herein is not limited to any particular number of memory cells in a NAND string.
Each memory cell stores data represented in analog or digital form. When storing one bit of digital data, the range of possible threshold voltages of the memory cell can be divided into two ranges, which are assigned to logical data "1" and "0". In one example of a NAND flash memory, the threshold voltage is negative after the memory cell is erased, which is defined as the logic value "1". The threshold voltage is a positive value after a program operation, which is defined as a logic value "0". When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell turns on and indicates a logic value of 1 being stored. When the threshold voltage is positive and a read operation is attempted by applying zero volts to the control gate, the memory cell is not turned on, indicating that logic zero has been stored.
The memory cell can also store multiple states (known as multi-state memory cells), thereby storing multiple bits of digital data. In the case of storing multiple states of data, the threshold voltage window is divided into several states. For example, if four states are used, there will be four threshold voltage ranges assigned with data values of "11", "10", "01", "00". In one example of a NAND-type memory, the threshold voltage after an erase operation has a negative value, which is defined as "11". Positive threshold voltages are used for the states of "10", "01", and "00". In some implementations, data values (e.g., logic states) are assigned to threshold voltages using a gray code assignment scheme, which is only one bit if the threshold voltage of the floating gate is incorrectly shifted to a neighboring physical state. This is to be affected. The specific relationship between the data programmed into the memory cell and the threshold voltage ranges of the cell depends on the data encoding scheme adopted for the memory cells. For example, US Pat. No. 6,222,762, filed on 2003, 6, 13, and U.S. Pat. 10 / 461,244, "Tracking Cells For A Memory System," all of which are incorporated herein by reference in their entirety, these patents describe various data encoding schemes for multi-state flash memory cells.
Suitable examples of NAND-type flash memories and their operation are provided in the following US patent / patent applications, all of which are incorporated herein by reference in their entirety. The US patent / US patent application is as follows: U.S. Pat. No. 5,570,315, U.S. Pat. No. 5,774,397, U.S. Pat. No. 6,046,935, U.S. Pat. No. 5,386,422, U.S. Pat. No. 6,456,528, U.S. Pat. Application Ser. No. 09 / 893,277 (Publication No. US2003 / 0002348). Other types of flash memory may also be used, such as EEPROM and other types of non-volatile memory.
Another type of memory cell useful in flash EEPROM systems utilizes non-conductive insulating materials instead of conductive floating gates that store charge in a non-volatile manner. Such cells are described in Chan et al., "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device", IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95. A triple insulation layer formed of silicon oxide, silicon nitride, silicon oxide ("ONO") is sandwiched between the conductive control gate and the surface of the semiconductor substrate over the memory cell channel. The cell is programmed by injecting electrons into the nitride from the cell channel, where the electrons are trapped and stored within a limited area. This stored charge causes the threshold voltage of the channel portion of the cell to change in a detectable manner. The cell can be erased by injecting hot holes into the nitride. Nozaki et al., "A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application", IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, also describes a similar cell in a split-gate structure in which a doped polysilicon gate extends over a portion of a memory cell channel to form an individual select transistor. The above two articles are hereby incorporated by reference in their entirety. The programming techniques mentioned in Section 1.2 of "Nonvolatile Semiconductor Memory Technology", IEEE Press, 1998, published by William D. Brown and Joe E. Brewer, are incorporated herein by reference, and apply to insulated charge-trapping devices. It is described in that section wherever possible.
4 is a block diagram of one embodiment of a flash memory system that may implement the techniques described herein. The
The data stored in the memory cells is read by the
Command data for controlling the flash memory device is input to the
The
One example memory system comprises a
In some implementations, some of the components of FIG. 4 can be combined. In various designs, one or more components (alone or in combination) of FIG. 4 may be considered as one management circuit, unlike
In one embodiment,
Referring to FIG. 5, an exemplary structure of a
During one embodiment of a read operation and a programming operation, 4256 memory cells are selected simultaneously. The selected memory cells have the same word line and the same kind of bit line (eg even bit lines or odd bit lines). Therefore, 532 bytes of data can be read or programmed simultaneously. This 532 bytes of data being read or programmed simultaneously form one logical page. Therefore, one block can store at least eight logical pages (four word lines with odd and even pages, respectively). When each memory cell stores two bits of data (eg multi-state memory cells), each of these two bits is stored in a different page, and one block stores sixteen logical pages. Other sized blocks and pages may also be used in the present invention. In addition, architectures other than those of FIGS. 4 and 5 may also be used to implement the present invention. For example, in one embodiment the bit lines are not divided into odd bit lines and even bit lines in order to have all bit lines programmed and read simultaneously (or not programmed, read simultaneously).
Memory cells are erased by increasing the p-well to an erase voltage (eg 20V) and grounding the word lines of the selected block. Source and bit lines are plotted. Erasing may be performed on the entire memory array, or on individual blocks, or another unit of cells. Electrons move from the floating gate to the p-well region and the threshold voltage is negative (in one embodiment).
During a read or verify operation, the state of the memory cell is detected by a sense amplifier connected to the bit line. FIG. 6 shows a portion of the
The memory system is provided with an external power supply, commonly referred to as Vcc. In some embodiments, Vcc has a value between 2.7 and 3.6 volts. The memory system may receive a ground signal (approximately 0 volts), commonly referred to as Vss. Some memory systems produce an internal power supply referred to as Vdd. All or some of the memory system components will use Vdd as the power source. In one embodiment, Vdd is a regulated and stabilized version of Vcc, adjusted to 2.7 volts regardless of whether Vcc has various values. In other embodiments, other values for Vdd may also be used. In some embodiments, the memory system does not have an internal power supply Vdd. Therefore, Vcc can be used internally as a power supply by the components of the memory system.
During operation of the memory system, various voltage levels will be applied to the word lines. To generate these various voltage levels, a charge pump can be used. In one embodiment, the charge pump will generate various voltages from Vdd. In other embodiments, Vcc or other signals may be provided as input to the charge pump.
7 is a block diagram illustrating one embodiment of a charge pump and selection circuit. The
7 shows two outputs Vpgm and Vcgr of the
Figure 8 illustrates the threshold voltage distribution of the memory cell array when each memory cell stores two bits of data. 8 illustrates a first threshold voltage distribution E for erased memory cells. Three threshold voltage distributions A, B, C for programmed memory cells are also shown. In one embodiment, the threshold voltages of the E distribution have negative values and the threshold voltages of the A, B, and C distributions have positive values.
Each individual threshold voltage in FIG. 8 corresponds to predetermined values of the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends on the data encoding scheme adopted for the cells. One example assigns "11" to threshold voltage range E (state E), assigns "10" to threshold voltage range A (state A), and assigns "00" to threshold voltage range B (state B). &Quot; 01 " is assigned to the threshold voltage range C (state C). However, in other embodiments, other schemes may be used.
8 also shows three read reference voltages Vra, Vrb, Vrc. By testing whether the threshold voltage of a given memory cell is lower or higher than Vra, Vrb, Vrc, the system can determine what state the memory cell is in. For example, if the memory cell is turned on when Vra, Vrb, Vrc are applied to the control gate of the memory cell, the memory cell is in state E. If Vrb, Vrc are applied to the control gate of the memory cell, the memory cell is turned on, but if Vra is applied to the control gate, the memory cell is in state A if it is not turned on. If Vrc is applied to the control gate of the memory cell, the memory cell is turned on. If Vra or Vrb is applied to the control gate, the memory cell is in state B if Va or Vrb is not turned on. If Vra or Vrb or Vrc is applied to the control gate of the memory cell but the memory cell is not turned on, the memory cell is in state C.
8 also shows three verify reference voltages Vva, Vvb, Vvc. When programming memory cells to state A, the system tests whether such memory cells have a threshold voltage greater than or equal to Vva. The memory cell programmed in state A will continue to be programmed until its threshold voltage is above Vva. When programming memory cells to state B, the system tests whether such memory cells have a threshold voltage greater than or equal to Vvb. A memory cell programmed in state B will continue to be programmed until its threshold voltage is above Vvb. When programming memory cells to state C, the system tests whether such memory cells have a threshold voltage greater than or equal to Vvc. The memory cell programmed in state C will continue to be programmed until its threshold voltage is above Vvc.
In one embodiment, as known as full sequence programming, memory cells may be programmed directly from erased state E to programmed state A, B, or C. For example, the memory cells to be programmed must first be erased so that they are all in the erased state E. While some memory cells are programmed from state E to state A, other memory cells are programmed from state E to state B and / or from state E to state C.
8 also illustrates an example of a two-pass technique for programming a multi-state memory cell that stores data for two different pages, a lower page and an upper page. Four states are shown. State E (11), state A (10), state B (00), state C (01). In state E, both pages store "1". In state A, the lower page stores "0" and the upper page stores "1". In state B, both pages store "0". In state C, the lower page stores "1" and the upper page stores "0". Although certain bit patterns are assigned to each of the states, other ways of bit patterns may be assigned. In the first programming pass, the threshold voltage level of the memory cell is determined by the bit to be programmed into the lower logical page. If the bit is a logic "1", the threshold voltage will not change because the threshold voltage is already in the proper state as a result of the previously erased. However, if the bit to be programmed is a logic value " 0 ", then the cell's threshold voltage increases to state A as shown by
In the second programming pass, the threshold voltage level of the cell is determined by the bit to be programmed into the upper logical page. If the upper logical page bit will store the logical value "1", then no programming occurs because the cell will be in state E or state A, depending on the programming of the lower page bit, where states E and A are values of "1". Carries a higher page bit with When the upper page bit becomes the logic value "0", the threshold voltage is shifted. If the resultant cell of the first pass remains in the erased state E, in the second step the cell is programmed to increase the threshold voltage as shown by
In one embodiment, the system may be configured to perform recording the full sequence when enough data is written to fill the entire page. If not enough data has been recorded to fill the entire page, the programming process may program the lower page with the received data. When subsequent data is received, the system will program the upper page. In another embodiment, the system may begin writing in the mode of programming the lower page and full sequence programming if sufficient data is subsequently received to fill the memory cells of the entire word lines (or most word lines). You can switch to the mode. A detailed description of such an embodiment is described in U.S. Patent Application No. 11 / 013,125. The invention of this application is named "Pipelined Programming of Non-Volatile Memories Using Early Data", and the inventors are Sergy Anatolievich Gorobets and Yan Li, which are hereby incorporated by reference in their entirety.
The techniques described herein may be used with other programming designs other than those described above. Some examples of additional suitable program designs are described in US Pat. US Patent Application No. 6,657,891, entitled "Compensating for Coupling During Read Operation of Non-Volatile Memory," and the inventor, Jiam Chen, filed April 4, 2005. It can be found at 11 / 099,133. The patent / patent application is hereby incorporated by reference in its entirety.
9 is a flow chart describing one embodiment of a high level programming process. A request to program the data may be received at the controller, state machine, or other device. In response to such a request, data (one or more information bits) may be written to the
In
In
In
In
FIG. 10 is a signal diagram illustrating the operation of the selected word line WL_sel and the unselected word line WL_unsel during one iteration of
After the setup phase, the system enters the program phase. In the program phase, the unselected word lines WL_unsel voltage increase to Vpass, which may be approximately 10 volts. The selected word line WL-sel voltage is increased to the program voltage Vpgm. In one embodiment, program voltage Vpgm consists of a set of program pulses, each pulse increasing in amplitude by a step size (e.g., 0.2V-0.4V) per pulse. In one embodiment, the initial voltage level of Vpgm is 12 volts. Other values can also be used for Vpgm. 10 shows a single program pulse during the program phase. When the program pulse is completed, the selected word line voltage WL_sel and the unselected word lines voltage WL_unsel fall to low voltages. The unselected word lines voltage WL_unsel drops to Vdd and the selected word line voltage WL_sel drops to Vss.
After the program phase, the system performs the verify phase. In the verify phase, the selected word line increases from Vss to Vcgv. Vcgv (comparative voltage used during the verification process) is selected based on the target threshold voltage distribution, in which a particular memory cell is programmed to this target threshold voltage distribution. As described above, the unselected word lines voltage WL_unsel increases to Vread. While the unselected word lines voltage WL_unsel has a value of Vread and the selected word line voltage WL_sel has a value of Vcgv, an appropriate bit line is precharged, provided with a path to be discharged, and sensed by a sense amplifier. do. Based on which bit line is discharged, it is determined whether the threshold voltage of the memory cell being verified has reached the level of Vcgv. After sensing, the selected word line voltage WL_sel is lowered to Vss and the unselected word lines voltage WL_unsel are lowered to Vdd. In the recovery phase (after the verification phase), the unselected word lines voltage WL_unsel drops to Vss. Further details of the verification step will be described later in describing the reading process. In one embodiment, the read process is used to perform verification for programming.
Charge pumps are typically good for charging, but not good for discharge in that they are not designed to sink large currents. If it is necessary to sink a large current, a discharge circuit is usually needed. In the technique described herein to maintain unselected word lines at Vdd prior to Vpass, a discharge circuit is necessary because the circuit for adjusting and maintaining Vdd is designed to supply large currents to many components of the memory system. Not. Therefore, a large amount of current can be efficiently sinked. The capacitance of Vdd is greater than the word line capacitances so that Vdd can absorb the amount of change in word lines without a significant change in its voltage. For example, the capacitances of unselected word lines tend to have values of several hundred pico-farads (eg 300 pF), while the capacitance of Vdd tends to range from tens to hundreds of nanofarads (eg 100 nF).
11 is a flow chart describing one embodiment of a process for reading data. The process of FIG. 11 may be performed in response to a data read request. In
If the memory cell being read is a binary memory cell, steps 708-712 are performed once for a particular Vcgr (or Vcgv). In one embodiment, Vcgr is equal to zero volts for binary memory cells. In embodiments where the memory cells are multi-state memory cells, the read process needs to test for multiple read comparison points as described above. Therefore, steps 708-712 need to be performed a number of times for each read comparison point. In
12 is a timing diagram illustrating various signals during the process of FIG. 11. Figure 12 shows a standby phase, a setup phase, a precharging / discharging phase, a restoration phase and a subsequent standby phase. The illustrated signals include the control gate voltage SGD of the drain side select gate, the word line voltage WL_unsel of the unselected word lines, the word line voltage WL_sel of the selected word line, and the control gate voltage of the source side select gate ( SGS), the voltage BL_sel of the bit line selected for programming, and the source line voltage Source.
The first standby phase occurs before time t0, in which all the signals shown have a value of Vss. The setup phase starts at time t0 and continues to t2. At time t1, unselected word lines increase to Vdd. The precharging / charging step starts at time t3 and continues to time t7. At time t3, the unselected word lines WL_unsel increase from Vdd to Vread and the selected word lines increase from Vss to Vcgr. Due to the capacitive coupling between the unselected word lines and the selected word line, the voltage of the selected word line initially increases to a value higher than Vcgr. Over time (between t3 and t4), the voltage WL_sel of the selected word line drops to Vcgr and stabilizes. At time t4, the selected bit line is precharged. At time t5, the source side select gate is turned on by increasing SGS to Vdd. This provides a path for discharging the charge on the bit line. If the threshold voltage of the memory cell selected for reading is greater than Vcgr, the selected memory cell will not be turned on and the bit line will not be discharged as shown in
If there are multiple reads (eg multi-state memory cell), the operation continues from time t7 to t2. If there are no multiple reads, a reconstruction step occurs between times t7 and t8. At time t7, SGD will decrease to Vss, the voltage WL_sel of unselected word lines will drop to Vss, SGS will drop to Vss, and the bit line voltage will disappear completely to Vss. At time t8, the system enters standby mode, where all signals shown in FIG. 12 have a value of Vss.
The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the scope of the invention. Many modifications and variations are possible in light of the above teaching. The described embodiments are chosen to best illustrate the principles of the present invention and the practical application of the invention, and those skilled in the art can best utilize the present invention through various embodiments and with various modifications to suit particular applications. It is available. The scope of the invention is defined by the appended claims.
Claims (24)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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US11/305,588 US7545675B2 (en) | 2005-12-16 | 2005-12-16 | Reading non-volatile storage with efficient setup |
US11/305,588 | 2005-12-16 | ||
US11/303,193 | 2005-12-16 | ||
US11/303,193 US7369437B2 (en) | 2005-12-16 | 2005-12-16 | System for reading non-volatile storage with efficient setup |
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KR101007371B1 true KR101007371B1 (en) | 2011-01-13 |
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JP (1) | JP4820879B2 (en) |
KR (1) | KR101007371B1 (en) |
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JP2010129125A (en) * | 2008-11-27 | 2010-06-10 | Toshiba Corp | Multivalue nonvolatile semiconductor memory |
JP7171949B2 (en) | 2019-11-14 | 2022-11-15 | 長江存儲科技有限責任公司 | Memory device that can reduce program failure and its erasing method |
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US20050213385A1 (en) * | 2004-03-29 | 2005-09-29 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
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KR100562506B1 (en) * | 2003-12-01 | 2006-03-21 | 삼성전자주식회사 | Flash memory device and programming method thereof |
JP4791812B2 (en) * | 2005-12-07 | 2011-10-12 | 株式会社東芝 | Nonvolatile semiconductor device |
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JP4820879B2 (en) | 2011-11-24 |
EP1964129A1 (en) | 2008-09-03 |
TW200737204A (en) | 2007-10-01 |
JP2009520310A (en) | 2009-05-21 |
TW201027538A (en) | 2010-07-16 |
TWI334142B (en) | 2010-12-01 |
WO2007078611A1 (en) | 2007-07-12 |
KR20080089401A (en) | 2008-10-06 |
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