KR101003212B1 - Nonvolatile memory device and method for program therof - Google Patents

Abstract

PURPOSE: A nonvolatile memory device and a method for program thereof are provided to improve a program fail due to an interference effect by dividing each page in operation of a bit program. CONSTITUTION: A plurality of memory cells stores program data in operation of an upper and lower bit program. A first flag cell stores the size information of a divided group in a plurality of memory cells. The second flag cell stores the number of N divided groups. A plurality of memory cells form one page.

Description

Nonvolatile memory device and method for programming thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a programming method thereof, and more particularly, to a method of programming a nonvolatile memory device capable of improving an interference effect by performing two or more NOP operations.

Among nonvolatile memory devices, flash memory devices are currently being used as a large data storage medium. In order to meet the demand for high-capacity memory devices and the high integration, it is possible to selectively store more than 2 bits of data in one memory cell in order to increase the data storage capacity at a smaller chip size. A multi-level cell structure has been proposed.

Multi-level cells, unlike single level cells (SLCs), in which one memory cell has two states of program / erase, have one memory cell and have four or more bits. Data can be represented, enabling more than twice the memory capacity as compared to single-level cells.

Multi-level cells typically have more than one threshold voltage. And, it has two or more data storage states corresponding thereto. Recent multi-level cells typically have four data storage states of '11', '10', '00' and '01'. The four data states are defined as threshold voltage distributions. That is, when the threshold voltage of the multi-level cell corresponds to any one of the four threshold voltage voltage distributions defined above, two bits of data corresponding thereto are stored in the memory cell. Separated by bits. In this case, the upper data bit is defined as MSB and the lower bit is defined as LSB. In the above description, taking '10' out of four data storage states '11', '10', '00', and '01' as an example, '1' is an MSB corresponding to an upper data bit, and '0' is a lower level. LSB corresponding to the data bit. Therefore, when the LSB is programmed in '11', it becomes '10'. The MSB program operation detects the LSB program result and makes the MSB program according to the result. If '1' is detected by the LSB, the data storage state is '11' and if the MSB program is operated here, it is '01'. In addition, if '0' is detected by the LSB, the data storage state is '10', so when the MSB program operates, the value is '00'.

However, since a multilevel cell has a larger number of threshold voltage distributions than a single level cell, a sufficient read margin of each threshold voltage distribution is required. Among the elements that change the threshold voltage, interference between adjacent cells is mostly present in the memory. As the integration degree of the device increases, the threshold voltage change caused by the interference may increase, thereby degrading the device characteristics.

The technical problem to be achieved by the present invention is to divide and program each page into a first region to an Nth region during a low bit program operation of a nonvolatile memory device having a multi-level cell, The present invention provides a nonvolatile memory device and a program method thereof capable of improving program fail due to an interference effect by storing a number of divided programs and a divided size of a first region to an Nth region and then performing a higher bit program operation. .

A nonvolatile memory device according to an embodiment of the present invention divides a plurality of memory cells capable of storing program data during a lower bit program operation and an upper bit program operation, and divides the plurality of memory cells into N groups during a program operation. A first flag cell for storing the size information of the divided group, and a second flag cell for storing the divided N group number information.

The plurality of memory cells constitute one page.

The first flag cell divides the page into the N groups and stores size information of each divided group.

The second flag cell stores the number of groups in which the page is divided.

Information stored in the first flag cell and the second flag cell is read before the upper bit program operation to set an area of the upper bit program operation.

According to at least one example embodiment of the inventive concepts, a method of programming a nonvolatile memory device may include providing a memory cell page including first to Nth memory cell groups and first and second flag cells. Sequentially selecting N memory cell groups to sequentially perform lower bit program operations, storing size information of the first to Nth memory cell groups in the first flag cell, and performing the second flag cell Storing group number information of the first to Nth memory cell groups in the memory module; and sequentially performing upper bit program operations of the first to Nth memory cell groups using data stored in the first and second flag cells. Including the step of carrying out.

The first to N-th memory cell groups divide and set the memory cell page in response to size information included in a program command input during the low bit program operation.

According to an embodiment of the present invention, during a low bit program operation of a nonvolatile memory device having a multi-bit cell, the program is divided into a first area and a second area, and a divided program of an upper bit program operation is performed. After storing the number of times and the divided sizes of the first region and the second region, the higher bit program operation may be performed to improve program fail due to an interference effect.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1 is a block diagram illustrating a page structure of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, a nonvolatile memory device is configured to include a plurality of pages including a plurality of memory cells. In this case, each page may be divided into a first area and a second area by using a number of partial program (NOP) method during a program operation. In an embodiment of the present invention, the first and second areas, that is, each page is divided into two areas, but the present invention is not limited thereto, and the number of partial program (NOP) methods may be increased by dividing the page into two or more areas. . Each page uses a first flag cell that stores the program size of a page to which area of the page is divided into a number of partial program (NOP) method, and a number of partial program (NOP) methods. And a second flag cell for storing whether or not it is stored.

2 is a flowchart illustrating a program method of a nonvolatile memory device according to an embodiment of the present invention.

3A to 3D are threshold voltage distribution diagrams of a first region and a second region for describing a method of programming a nonvolatile memory device according to an embodiment of the present invention.

A method of programming a nonvolatile memory device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2 and 3A to 3D as follows.

In the initial state of the nonvolatile memory device, all memory cells of one page are erased.

First, when the first lower bit program command is applied, the size of the first area of the target page to perform a program operation is set in response to the size information included in the first lower bit program command. Subsequently, the low bit program LSB operation of the memory cells included in the first region of the target page set by the first low bit program command is performed. As shown in 3a, there may be two threshold voltage distributions, an initial state in which the lower bit is "1" and a program state in which the lower bit is "0".

In this case, the memory cells included in the second region do not perform a program operation.

Thereafter, when the second lower bit program command is applied, the size of the second area of the target page to perform a program operation is set in response to the size information included in the second lower bit program command. The size of the second area sets an area in the remaining areas except for the first area of the target page. Thereafter, the low bit program operation LSB of the memory cells included in the second region of the target page set in response to the second low bit program command is performed. As shown in FIG. 3B, two threshold voltage distributions may be provided, an initial state in which the lower bit is “1” and a program state in which the lower bit is “0”. At this time, since the memory cells included in the first region are the lower bit program (LSB) operation rather than the upper bit program (MSB) method, the re-program operation does not proceed.

In an embodiment of the present invention, since two times of number of partial program (NOP) schemes are used, the first and second lower bit program operations are performed by dividing into first and second regions, and two or more times of NOP are performed. In the case of using the partial program), the size of the target page is divided into first to Nth regions to perform a lower bit program operation.

Thereafter, the first flag cell stores data having information on which region of the page a subsequent higher bit program (MSB) operation is performed (230). That is, the upper bit program (MSB) operation The size data of the first area to be implemented is stored in the first flag cell.

Subsequently, the MSB operation subsequent to the second flag cell stores data on the number of partial program (NOP) method several times in the second flag cell.

Thereafter, the first upper bit program (MSB) operation of the memory cells of the first region is performed by using the data of the first flag cell and the data of the second flag cell. As shown in FIG. 3C, the threshold voltage distribution may have four threshold voltage distributions in which the program bit is “11” and the program bits are “01”, “10”, and “00”. In this case, the memory cells included in the second region do not perform a program operation.

Thereafter, the second upper bit program (MSB) operation of the memory cells of the second area is performed using the data of the first flag cell and the data of the second flag cell. (260) The upper bit program (MSB) operation is performed. As shown in FIG. 3C, the threshold voltage distribution may have four threshold voltage distributions in which the program bit is “11” and the program bits are “01”, “10”, and “00”. In this case, the memory cells included in the first region do not perform a program operation.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a block diagram illustrating a page structure of a nonvolatile memory device according to an embodiment of the present invention.

2 is a flowchart illustrating a program method of a nonvolatile memory device according to an embodiment of the present invention.

3A to 3D are threshold voltage distribution diagrams of a first region and a second region for describing a method of programming a nonvolatile memory device according to an embodiment of the present invention.

Claims (9)

A plurality of memory cells capable of storing program data during lower bit program operations and upper bit program operations; A first flag cell for dividing the plurality of memory cells into N groups and storing size information of the divided groups during a program operation; And And a second flag cell configured to store the divided N group number information. The method of claim 1, And a plurality of memory cells constitute one page. The method of claim 2, And the first flag cell divides the page into the N groups and stores size information of each divided group. The method of claim 2, And the second flag cell stores the number of groups in which the page is divided. The method of claim 1, And information stored in the first flag cell and the second flag cell is read before the upper bit program operation to set an area of the upper bit program operation. Providing a memory device including a plurality of page groups composed of a plurality of memory cells, first and second flag cells; Dividing each of the plurality of page groups to select a first region to perform a first lower bit program operation; Performing a second lower bit program operation by selecting a second area by dividing the remaining areas except the first area of each of the plurality of page groups; Storing size information of the first and second regions in the first flag cell of each of the plurality of page groups; Storing page division number information in second flag cells of each of the plurality of page groups; And And performing first and second higher bit program operations on the first region and the second region by using data stored in the first and second flag cells. The method of claim 6, And the first and second lower bit program operations are performed by a lower bit program command including information for setting the first region and the second region. Providing a memory cell page comprising first to Nth memory cell groups and first and second flag cells; Sequentially selecting the first to Nth memory cell groups to sequentially perform lower bit program operations; Storing size information of the first to Nth memory cell groups in the first flag cell; Storing group number information of the first to Nth memory cell groups in the second flag cell; And And sequentially performing upper bit program operations of the first to Nth memory cell groups using data stored in the first and second flag cells. The method of claim 8, The first to N th memory cell groups divide and set the memory cell page in response to size information included in a program command input during the low bit program operation.

Images