KR101002102B1 - Method of testing Semiconductor Device - Google Patents

Abstract

A test method for a semiconductor device is disclosed. The removal power pin count is set to provide the same conditions and power application environment as the test process that substantially checks the inherent function of the semiconductor device. Setting the number of removed power pins determines the final number of power pins that can be provided in normal operation. The final number of power pins refers to the minimum number of power pins that are connected for the semiconductor device to function normally. The power pin number reaches the state where the timing margin is removed from the operation of the semiconductor device. Then, a delay test pattern is applied that can be used in the scan mode of the test. If it is determined that the delay test pattern is bad, the period of the delay test pattern is increased. The increase in the period of the delay test pattern has the effect of counteracting the effect of increasing the number of switching in the delay test pattern, or ground bounce due to excessive current required per unit time, so that the overkill in which a normal semiconductor device is determined to be defective. Prevent the phenomenon.

Semiconductor Test, Scan Test, Test Pattern

Description

Method of testing semiconductor device

The present invention relates to a test method for a semiconductor device, and more particularly, to a test method for interrupting power supply to a power pin inside a chip and setting an optimal test condition.

The test process for the semiconductor device is performed after the semiconductor manufacturing process or the packaging process. In other words, whether the device formed after the circuit and the wiring are implemented on the wafer performs the correct function is confirmed by the test process. The test process, which is usually performed before the packaging process and performed in the wafer state, is referred to as electric die sorting (EDS). In addition, a test is performed to determine whether the device performs normal operation even after the packaging is performed.

As line widths are reduced in the manufacturing process of semiconductor devices and complex functions are implemented on one chip, a test cell is implemented by implementing scan cells in predetermined areas of the chip rather than directly testing the unique functions of the chip. These scan cells are placed between the core or functional block and the input / output pads that are responsible for the device's unique functions.

Typically the scan cells are connected in series to form a scan chain. This scan chain has a shift register or the like therein for continuous transfer of test patterns. During the test, a test pattern is applied to the input pin, and the output value at the output pin is compared with the expected value, and finally, whether the device is defective is determined.

In these scan design based tests (scan test), it is important to consider overkill and underkill.

Overkill refers to a case in which a substantially normal semiconductor device is determined to be defective, and underkill refers to a case in which a substantially bad semiconductor device is determined to be normal. Overkill or underkill is a typical phenomenon that causes only problems of judgment in the test process, but only the aspect of the judgment in the test process.

Typically, the cause of the overkill is due to the switching operation on the circuit provided in the scan cell. In other words, when the number of times of switching of the circuit under test increases according to the test pattern, the current supplied to the scan cell increases. If the current supplied in the test is larger than the current supplied during the normal operation of the semiconductor chip, the ground level is not set constantly and pulsating ground bounce occurs. Therefore, an overkill for determining that the semiconductor chip normally operating in the mounting environment is defective during the test is generated.

In order to prevent such an overkill phenomenon, a method of reducing an existing testing operation speed is used in a test apparatus. That is, a method of reducing the signal transition by reducing the operation speed of the test pattern is used. In this case, the number of times the circuit in the scan cell is switched per unit time is reduced, thus reducing the current supplied. By reducing the supply current, unwanted phenomena such as ground bounce are minimized. However, the operating speed of the test pattern causes a problem of not sufficiently covering the operating speed in a normal use environment. As a result, in the mounting environment, an underkill that judges a defective semiconductor element as normal occurs.

An object of the present invention for solving the above problems is to provide a test method of a semiconductor device using a method of determining the optimal number of power pins, and the clock period of the test pattern suitable for the selected number of power pins.

The present invention for achieving the above object, the step of applying a reference test pattern to the semiconductor device to set the number of removal power pins in the normal operation to determine the final number of power pins; And setting a period of the delay test pattern corresponding to the number of the removed power pins by applying a delay test pattern to the semiconductor device.

According to the present invention described above, by applying a reference test pattern to the semiconductor device to determine the minimum number of power pins that can be connected during subsequent tests. This creates the harshest environment the semiconductor device can withstand during normal operation. Then, a current is supplied to the semiconductor device according to the determined number of power pins, and a delay test pattern is applied. In the application of the delay test pattern, the period of the test pattern applied to increase the overkill phenomenon is increased. This mitigates ground bouncing based on the number of power pins, enabling the optimal delay test pattern to be set. This provides a normal operating environment externally to the semiconductor device on which the inspection process is performed, and provides an effect of performing a functional test in a scan test as if the semiconductor device is in actual operation.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

1 is a flow chart illustrating a semiconductor device test method according to a preferred embodiment of the present invention.

Referring to FIG. 1, first, a reference test pattern is applied to a semiconductor device (S100). The reference test pattern may be a function test pattern for testing a unique function of the semiconductor device. Therefore, the reference test pattern is a test pattern for determining whether the functional blocks of the semiconductor device that perform its own function. While the functional test pattern is applied, the functional test pattern is applied to the functional blocks of the semiconductor device. In addition, the functional blocks perform a switching operation according to the functional test pattern.

The reference test pattern described above may be a test pattern other than the functional test pattern. That is, any pattern can be used as long as the pattern can cause the same or similar switching frequency as the functional test pattern. In addition, when the test device is applied with a functional test pattern, the pattern is applied to the functional blocks of the device, and switching occurs. However, the switching may be a scan cell provided in the semiconductor device. That is, if a predetermined pattern is applied to the scan cells and the number of switching is the same or similar to the function test pattern, this may be applied. In addition, it will be apparent to those skilled in the art that the reference test pattern is set differently according to the difference in the type of semiconductor device.

First, the removal power pin number Nrm is set to zero before applying the reference test pattern to the semiconductor device. Further, the increase time of the period of the delay test pattern is also set to zero. The test pattern is supplied from test equipment or synchronized with a clock generated inside a semiconductor device. Therefore, in practice, the period of the delay test pattern can be interpreted to be the same as the clock period.

First, when the reference test pattern is first supplied to the semiconductor device, all power pins to the semiconductor device are supplied with power. The power pin includes a power pin for supplying a positive power supply voltage (called Vdd among those skilled in the art), a negative power supply voltage (called Vss), and a power pin for supplying a ground power source. In addition, the power pin may be interpreted as a power pad formed on a chip of a semiconductor device.

The reference test pattern is supplied and it is determined whether the semiconductor device in which the test is performed is normal (S110).

If it is determined that normal operation, the number Nrm of the removed power pin is increased by one (S120). If it is determined that the normal operation is at the supply of the original reference test pattern, it can be seen that the semiconductor device under test is a substantially normal product. In addition, the semiconductor element which is determined to be defective in the supply of the first reference test pattern is determined as the final defective and no further testing is performed.

The increase operation of the number of removal power pins Nrm in accordance with the supply of the reference test pattern and the normal determination proceeds until the semiconductor element is determined to be defective according to the reference test pattern.

As a result, the above-described operation is to supply the reference test pattern to the semiconductor device until the first failure occurs, and the removal power pin number Nrm is increased by one for each event determined to be normal. That is, for each event determined to be normal by the reference test pattern, one test pin of the semiconductor device is cut off from the power supply. The meaning of this operation is clarified by FIG.

2 is a circuit diagram illustrating a power pin removal operation according to a preferred embodiment of the present invention.

Referring to FIG. 2, the semiconductor device on which the test is performed is composed of a PMOS transistor and an NMOS transistor. However, the circuit diagram shown in FIG. 2 is an equivalent circuit modeling an inverter connected to a PMOS transistor and an NMOS transistor. In addition, the circuit diagram illustrated in FIG. 2 illustrates a part of a switching device included in a semiconductor device, and includes a switching device provided in a functional block and a switching device provided in a scan cell.

The NMOS and PMOS transistors shown in FIG. 2 are transistors having ideal characteristics. In addition, the actual PMOS transistor has inductance and capacitance components for each terminal. However, it is applied as a model suitable to express the change of the current amount according to the switching operation. Thus, the inductance components Lp and Lg are provided between the positive power supply voltage Vdd and the ground level GND, and the capacitor impedance components Cp and Cn are present between the source and drain terminals of the transistor.

If the switching element is connected to a plurality of power pins, the inductor is modeled as a structure in which a plurality of inductors are arranged in parallel at the connection portion between the switching element and the power pin. In addition, when the number of removal power pins Nrm is increased until the failure of the semiconductor device occurs as described in the present embodiment, the inductance Lp or Lg seen by the transistor increases. An increase in inductance Lp or Lg results in an increase in the voltage applied to inductance Lp or Lg in the switching operation.

For example, the inductance Lg seen from the source terminal of the NMOS transistor having ideal characteristics in FIG. 2 increases as the number of removal power pins Nrm increases. This is because the voltage applied to the inductor is proportional to the inductance and proportional to the amount of change in the amount of current. Accordingly, the voltage applied to the source terminal of the NMOS transistor in the switching operation increases, and the voltage pulsates according to the change in the amount of current. This indicates an increase in ground bounce in the switching operation.

As a result, the operation of applying the reference test pattern to the semiconductor device in the above-described process and increasing the number of removing power pins Nrm until the semiconductor device is determined to be defective is to increase the ground bounce due to the switching operation of the scan cell. This is to set up a harsh situation when the semiconductor device starts normal operation.

In other words, increasing the number of removal power pins Nrm increases the ground bouncing of the semiconductor device and determines the minimum number of connected power pins that can maintain normal operation. In addition, the ground bounce by artificially removing the number of power pins to artificially cover the behavior when the semiconductor device is used in the mounting environment.

Therefore, when a failure of the semiconductor device occurs due to the input of the reference test pattern, the number of removed power pins Nrm is decreased to set a new number of removed power pins Nrm. This reproduces a situation where the number of connected power pins is the minimum in the case determined to be normal. The new removal power pin number Nrm, which is reduced by one from the removal power pin number Nrm, determines the final power pin number. That is, the final power pin number indicates the number of power pins connected to an external power source among the power pins of the semiconductor device. As a result, the final power pin number is the total power pin of the semiconductor device minus the number of power pins to be disconnected from the external power source.

Referring back to FIG. 1, the final power pin number is determined by subtracting 1 from the number Nrm of the removed power pins, and a delay test pattern is applied to the semiconductor device (S200). That is, according to the determined final number of power pins, only the corresponding power pins are applied with a delay test pattern for the semiconductor device connected to the power source.

In addition, the delay test pattern is a test pattern applied to the semiconductor device in the scan mode. Preferably, the delay test pattern is a scan test pattern in which scan cells are sequentially connected to a scan chain. The scan test pattern is provided to determine whether the semiconductor device is normal by determining whether the scan cells provided in the semiconductor design operate properly, rather than confirming the inherent function of the functional block of the semiconductor device.

Subsequently, it is checked whether the semiconductor device operates normally according to the application of the delay test pattern (S210).

If it is determined that the failure is caused by the application of the delay test pattern, the delay test pattern is increased by the period increase time Tdw (S220).

The period increase time Tdw, which is increased per test, may be set differently according to the type of semiconductor device to be tested. That is, it may be set differently according to electrical characteristics such as an operating speed of the semiconductor device under test.

For example, when the operation speed of the semiconductor element is relatively fast, the period increase time Tdw is set short. On the other hand, when the operation speed of the semiconductor element is relatively slow, the period increase time Tdw is set long.

Subsequently, the delay test pattern having the increased period is applied to the semiconductor price, and it is checked whether the semiconductor device is normally operated (S230). If it is determined to be defective, the period of the reset delay test pattern is increased again and applied to the semiconductor device. The above operation is repeated until the semiconductor element is determined to be normal.

In the delay test pattern, the increase in period has the following meaning.

Increasing the period of the delay test pattern causes a reduction in the number of switching of the switching element per unit time. When the number of switching decreases, the current supplied to the scan cell to which the test pattern is applied decreases. That is, the delay of the signal in the semiconductor device caused by the effect of many instantaneous currents that are excessively required in the delay test can be offset by increasing the cycle time.

That is, when the semiconductor device is supplied with a current higher than the current supplied at the time of the reference test pattern by applying the delay test pattern, the application of such excessive current may cause an overkill phenomenon in which a normal semiconductor device is judged as defective due to various factors. Cause Excessive current supply causes overkill phenomena such as destruction of device characteristics due to supply of more current than normal operation, and malfunction of scan cells due to excessive supply of current. To reduce this overkill, the period of the scan pattern is increased to compensate for the additional delay caused by excessive current.

As described above, in the present invention, first, the optimum condition of the number Nrm of the removed power pins is set in the state of applying the reference test pattern. The reference test pattern represents a test pattern in a normal operation, and the switching operation generated in the test pattern is set equal to or similar to the number of switching occurring in the normal operation. This allows you to verify that the circuit performs its original function.

The number of removed power pins Nrm is increased by 1 until the semiconductor device is judged to be defective, and finally, the minimum number of power pins connected to the power source power when determined to be normal is determined. This is a state where the most severe situation is set in the same environment as the switching when the mounting environment or the semiconductor element performs its original operation. In other words, when the number of removal power pins Nrm is increased, the phenomenon of ground bounce is increased to set the harshest environment in which the semiconductor device can operate normally.

Then, the delay test pattern is applied, and the period of the delay test pattern is gradually increased according to whether the semiconductor device is defective. The delay test pattern determines whether there is a delay time generated in a scan cell of the semiconductor device, rather than a function test function of determining whether the circuit of the semiconductor device is inherently functional. That is, after a test signal is applied in a situation in which a certain level of output is expected, a time elapsed until a specific level of output occurs, and it is determined whether the measured elapsed time meets the specifications of the corresponding semiconductor device. do.

If a failure occurs, this means that the applied delay test pattern requires more switching operation on the semiconductor device than the reference test pattern. Thus, through the set Nrm, the delay test pattern requires more current consumption than the reference test pattern requires. Therefore, when the test is performed without correcting the delay test pattern under the set Nrm, an overkill phenomenon that determines a normally operating semiconductor device as a defect occurs.

In order to prevent this phenomenon, when a failure occurs in the semiconductor device under the delay test pattern, the period of the pattern is gradually increased, and the operation is performed until the semiconductor device is determined to be normal. The period of the pattern at which the semiconductor device starts to be judged as normal is a point at which overkill due to excessive current caused by the delay test pattern is prevented. This is a time when the semiconductor device is determined to be normal since the ground bounce is reduced by the increase in the period.

After that, all power pins are restored by applying the set delay test pattern period, and then the subsequent semiconductor devices are tested. In addition, the period of the set delay test pattern is continuously applied to the same semiconductor device after that, and the set delay test pattern is applied as it is to subsequent semiconductor devices.

Of course, when the type of semiconductor element is changed, the number of removal power pins Nrm and the delay test pattern are changed.

Hardware for performing the above-described testing operation may be implemented in various ways.

For example, as shown in FIG. 2, a controllable switch is provided at a node connected to the pad in the semiconductor circuit to control a connection state between the pad and the conductive line.

In addition, the semiconductor circuit may be controlled by a separate test board or test equipment without being provided in the semiconductor circuit. This allows the switching elements to be placed between the power terminal of the semiconductor element and the power supply terminal of the test equipment on the test board, and to control the power supply applied to the semiconductor element through on / off of the switching element through a separate control signal. have. Similarly, the supply of power in the test rig itself can be individually limited to regulate the power supplied to the semiconductor device from the test rig itself. This allows the power pins of the semiconductor device to float and achieve the desired number of removal power pins Nrm.

1 is a flow chart illustrating a semiconductor device test method according to a preferred embodiment of the present invention.

2 is a circuit diagram illustrating a power pin removal operation according to a preferred embodiment of the present invention.

Claims (7)

Determining a final number of power pins by applying a reference test pattern to a semiconductor device to set the number of removal power pins in normal operation; And Applying a delay test pattern to the semiconductor device to set a period of the delay test pattern corresponding to the number of the removed power pins; Setting the period of the delay test pattern, Supplying current to the semiconductor device according to the final number of power pins and applying the delay test pattern; And And increasing the period of the delay test pattern when the semiconductor device is defective according to the application of the delay test pattern. The method of claim 1, wherein the setting of the number of the removal power pins comprises: Setting the number of the removed power pins to 0 and applying the reference test pattern to the semiconductor device; When the semiconductor device is determined to be normal, increasing the number of the removing power pins by one; And Supplying a current to the power pins of the semiconductor device according to the increased number of removed power pins, and reapplying the reference test pattern to the semiconductor device. The method of claim 2, wherein an increase in the number of application and removal power pins of the reference test pattern is performed until the semiconductor device is determined to be defective. The test of claim 3, wherein when the semiconductor device is determined to be defective according to the application of the reference test pattern, the final power pin number is determined by subtracting 1 from the number of removed power pins. Way. delete The method of claim 1, wherein the application of the delay test pattern and an increase in the period of the delay test pattern are performed until the semiconductor device is determined to be normal. The method of claim 1, wherein the reference test pattern is a functional test pattern for checking whether the functional blocks of the semiconductor device are operated or a test pattern having the same number of times of switching.

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