KR100995655B1 - Device for controlling operating mode of memory device - Google Patents

Abstract

The present invention relates to an operation mode control apparatus of a memory device that allows the memory device to operate normally in all timing intervals. According to an aspect of the present invention, there is provided an operation mode control apparatus of a memory device, the control apparatus comprising: first and second control for receiving a chip select signal and an address control signal and outputting first and second control signals, respectively; Way; And third control means for receiving the chip selection signal, the address control signal, the enable signal, and the output signal of the first control means, and outputting third and fourth control signals, wherein the memory device is in a normal mode. In this case, when the second control means is enabled to enable the second control signal and the memory device is in a test mode, the first and third control means are enabled to enable the first and third control means. And a fourth control signal is enabled.

Description

Device for controlling operating mode of memory device

1 is a block diagram showing an operation mode converter of a memory device.

2 is a circuit diagram showing an operation mode control apparatus of a conventional memory device.

3 is an operation waveform diagram of an operation mode control apparatus of a conventional memory device.

4A and 4B are circuit diagrams illustrating an operation mode control apparatus of a memory device according to the present invention;

FIG. 5 is a circuit diagram showing a decoder of the operation mode conversion device shown in FIG. 1; FIG.

6 is an operational waveform diagram of an operation mode control apparatus of a memory device according to the present invention;

Explanation of symbols on the main parts of the drawings

11: address buffer 12,13: transfer means

14: Decoder 15: Driver

16: control block 21, 22, 23, 410, 420, 430: control means

411,423,425,426,427: Delay 421,53: Input section

422: delay unit 424,433: pulse generator

431: buffer portion 432,441,54: latch portion

434, 435: output 436, 437, 51, 52: switching unit                 

438: CMOS buffer 439: pull-up section

440: pull-down section

The present invention relates to an operation mode control apparatus of a memory device, and more particularly, to an operation mode control apparatus of a memory device that allows the memory device to operate normally in all timing intervals.

In general, a memory device is tested by putting the memory device into a test mode to verify the characteristics and design of the memory device. In addition, the memory device is tested in a timing interval other than the normal mode of the memory device through a pad used in the normal mode of the memory device without a separate pad for testing the memory device.

1 is a block diagram illustrating an operation mode converter of a memory device.

The operation mode converter of the memory device includes an address buffer 11, transfer means 12, 13, a decoder 14, a driver 15, and a control block 16. The address buffer 11 buffers an address to receive, and the buffered address signal add is applied to the decoder 14 and the driver 15 via the transfer means 12 and 13. The control block 16 includes an enable signal en for enabling a test mode operation of the memory device, a chip select signal csb for selecting a chip to operate in the normal mode, and the address signal ( An address control signal adb that enables add is received. The control block 16 receiving the input signals (en, csb, adb) applies the output signals (tms, nms, tme1, tme2) to the transfer means (12, 13) and the decoder (14).

In the operation mode converter of such a memory device, when the memory device is in the normal mode, the transfer means 13 is turned on as the second control signal nms is enabled. As a result, the address signal add is transmitted to the driver 15, and the driver 15 applies the normal mode signal nm to the memory device so that the memory device performs the normal mode operation. On the other hand, when the memory device is in the test mode, the transfer means 12 is turned on as the first, third and fourth control signals tms, tme1, and tme2 are enabled. As a result, the address signal add is transmitted to the decoder 14, which applies the test mode signal tm to the memory device so that the memory device performs a test mode operation.

FIG. 2 is a circuit diagram showing a control block 16 which is an operation mode control device of a conventional memory device in the operation mode conversion device of the memory device shown in FIG.

The operation mode control device 16 of the conventional memory device includes three control means 21, 22, and 23. The first control means 21 receives the chip select signal csb and the address control signal adb to output the first control signal tms, and the second control means 22 is connected to the chip select signal csb. The address control signal adb is received and the second control signal nms is output. In addition, the third control means 23 receives the enable signal en and the address control signal adb and outputs the third and fourth control signals tme1 and tme2.

In the operation mode control apparatus of such a conventional memory device, as shown in FIG. 4, the chip select signal csb is selected at a low level, and the address control signal adb is enabled at a low level. Then, when the chip select signal csb is deselected at a high level (t1 to t2), the first and third and fourth control signals tms, tme1 and tme2 are set to a high level. Enabled, the memory device performs a test mode operation. However, these timing sections t1 to t2 are not sections in which the memory device performs a test mode operation but sections in which the memory device performs a normal mode operation. As a result, there is a problem that a timing section in which the memory device malfunctions occurs.

Therefore, the present invention was created to solve the problems inherent in the operation mode control apparatus of the memory device according to the prior art as described above, an object of the present invention, the memory to operate the memory device normally in all timing intervals It is to provide an operation mode control apparatus of the apparatus.

In order to achieve the object as described above, according to an aspect of the present invention, there is provided an operation mode control apparatus of a memory device, which receives a chip select signal and an address control signal to control first and second, respectively. First and second control means for outputting a signal; And third control means for receiving the chip selection signal, the address control signal, the enable signal, and the output signal of the first control means and outputting third and fourth control signals, wherein the memory device is in a normal mode. In this case, when the second control means is enabled to enable the second control signal, and the memory device is in a test mode, the first and third control means are enabled to enable the first and third control means. And the fourth control signal is enabled.

According to another aspect of the invention, the first control means, the first inverter for receiving the address control signal; A first NAND gate configured to receive an output signal of the inverter and the chip select signal; And a first delay unit and a second NAND gate, respectively, for receiving the output signal of the NAND gate, wherein the output signal of the first delay unit is applied to the second NAND gate, and the chip select signal is deselected. When the address control signal is enabled, the first control means enables and outputs the first control signal.

According to another aspect of the invention, the second control means, the input unit for receiving the chip select signal and the address control signal; A delay unit for receiving an output signal of the input unit; A first NOR gate configured to receive the chip select signal, the address control signal, and an output signal of the delay unit; A first delay unit for receiving an output signal of the first NOR gate; A first pulse generator for receiving an output signal of the first delay unit and outputting a pulse signal; And a first inverter for inverting the pulse signal, wherein when the chip selection signal is selected and the address control signal is enabled, the second control means enables and outputs the second control signal. .

According to another aspect of the invention, the third control means, the buffer unit for receiving the chip select signal and the address control signal; A first latch unit receiving an output signal of the buffer unit; A first NAND gate receiving the output signal of the latch unit and the enable signal at all times; A first pulse generator receiving the output signal of the first NAND gate and outputting a pulse signal; A third inverter for inverting the pulse signal; A first output unit configured to receive the output signal of the third inverter and the first control signal and output the third control signal; And a second output unit configured to receive an output signal of the third inverter and the first control signal and output the fourth control signal, wherein the chip select signal is deselected and the address control signal and the enable are enabled. When the signal is enabled and the first control signal is enabled, the third control means enables and outputs the third control signal; When the chip select signal is deselected and the address control signal and the enable signal are enabled, the third control means enables and outputs the fourth control signal.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A and 4B are circuit diagrams illustrating an operation mode control apparatus of a memory device according to the present invention.

The operation mode control device of the present invention includes three control means (410, 420, 430).

The first control means 410 includes an inverter IN1, NAND gates ND1 and ND2, and a delayer 411. The NAND gate ND1 receives the chip select signal csb and the address control signal adb inverted by the inverter IN1 and transfers the output signal to the delay unit 411 and the NAND gate ND2. The NAND gate ND2 additionally receives the output signal of the delayer 411 and outputs a first control signal tms. The first control means 410 turns on the first control signal tms to a high level when the chip select signal csb is deselected to a high level and the address control signal adb is enabled to a low level. Enable and print. That is, when the memory device is in the test mode, the first control means 410 that receives the chip select signal csb and the address control signal adb outputs the first control signal tms and is shown in FIG. 1. One delivery means 12 is enabled. Accordingly, the address signal add applied from the address buffer 11 to the transfer means 12 is transmitted to the decoder 14, as a result, the memory device is switched to the test mode and the memory device performs the test mode operation. Do it.

The second control means 420 includes an input unit 421, a delay unit 422, a NOA gate NO1, a delay 423, a pulse generator 424, and an inverter IN2.

The input unit 421 includes inverters IN3 and IN4, a NAND gate ND3, a NOA gate NO2, and a delay unit 425. The delay unit 422 includes NAND gates ND4 and ND5, delayers 426 and 427, and an inverter IN5. The NAND gate ND3 of the input unit 421 receives the chip select signal csb and the address control signal adb inverted by the inverter IN3 and transmits an output signal to the delay unit 425. The output signal of the delay unit 425 is applied to the NAND gate ND4 of the delay unit 422 via the inverter IN4. The NOA gate NO2 of the input unit 421 receives the chip select signal csb and the address control signal adb and applies an output signal to the NAND gate ND4 of the delay unit 422. The output signal of the NAND gate ND4 is transmitted to the delay unit 426 and another NAND gate ND5, and the output signal of the other NAND gate ND5 is passed through the delay unit 427 and the inverter IN5. It is applied to the gate NO1. The NOA gate NO1 receiving the output signal adbg of the delay unit 422 additionally receives the chip select signal csb and the address control signal adb, and the output signal of the NOA gate NO1 is delayed. Delivered to flag 423. The delay unit 423 applies an output signal to the pulse generator 424, and the pulse generator 424 is enabled only when the input signal is high level, and outputs a low level pulse signal. The pulse signal is inverted by the inverter IN2 and output as the second control signal nms.

When the chip select signal csb is selected at the low level and the address control signal adb is also enabled at the low level, the second control means 420 outputs the output signal adbg of the delay unit 422. It becomes a low level pulse signal and enables the second control signal nms to a high level and outputs it. That is, when the memory device is in the normal mode, the second control means 420 receiving the chip select signal csb and the address control signal adb outputs the second control signal nms and is shown in FIG. 1. One delivery means 13 is enabled. Accordingly, the address signal add applied from the address buffer 11 to the transfer means 13 is transmitted to the driver 15, as a result, the memory device is switched to the normal mode so that the memory device performs the normal mode operation. Do it.

The third control means 430 includes a buffer unit 431, a latch unit 432, inverters IN10, IN11, IN12, IN13, NAND gate ND6, pulse generator 433, NMOS transistor N3, and First and second outputs 434 and 435 are provided.

The buffer unit 431 may include a first switching unit 436 connected to an external power supply VDD, a second switching unit 437 connected to a ground terminal, and a first switching unit 436 and a second switching unit 437. CMOS type buffer 438 is connected between. The first switching unit 436 includes an inverter IN6 and a PMOS transistor P1, and the second switching unit 437 includes an NMOS transistor N1. The first and second switching units 436 and 437 are turned on and off by the chip select signal csb. The CMOS buffer 438 includes a PMOS transistor P2 and an NMOS transistor N2 connected in series between the first switching unit 436 and the second switching unit 437, and is inverted by the inverter IN7. An address control signal adb is received. That is, when the chip select signal csb is deselected to a high level, the buffer unit 431 turns on the first and second switching units 436 and 437, and as a result, the inverter controls the received address control signal adb. The data is transferred to the latch unit 432 as it is through the IN7 and the CMOS buffer 438. Here, the NMOS transistor N3 is connected between the common connection terminal and the ground terminal of the buffer unit 431 and the latch unit 432, and the power signal pwup inverted by the inverter IN12. Is turned on and off).

The latch unit 432 includes inverters IN8 and IN9, and inverts and holds the address control signal adb received from the buffer unit 431. The output signal of the latch unit 432 is applied to the NAND gate ND6 via the inverters IN10 and IN11. The NAND gate ND6 receives the output signal of the inverter IN11 and the enable signal en and transfers the output signal to the pulse generator 433. When the enable signal en is enabled at a high level, the NAND gate ND6 inverts the output signal of the received inverter IN11 and transmits the inverted signal to the pulse generator 433.

The pulse generator 433 is enabled only when the input signal is high level, and outputs a low level pulse signal. The pulse signal is inverted by the inverter IN13 and applied to the first and second output units 434 and 435.

The first output unit 434 includes a NAND gate ND7 and an inverter IN14. The NAND gate ND7 has an output signal and a first control signal of the pulse generator 433 inverted by the inverter IN13. Receive (tms) The inverter IN14 inverts the output signal of the NAND gate ND7 and outputs the third control signal tme1. That is, when the first control signal tms is enabled at a high level, the first output unit 434 is enabled and outputs the third control signal tme1.

The second output unit 435 includes a pull-up unit 439, a pull-down unit 440, a PMOS transistor P4, and a latch unit 441. The pull-up unit 439 and the pull-down unit 440 are connected in series between an external power supply VDD and a ground terminal. The pull-up unit 439 includes a PMOS transistor P3, and the pull-down unit 440 includes an NMOS. The transistor N4 is included. In addition, the pull-up unit 439 and the pull-down unit 440 respectively receive the enable signal en and the output signal of the inverter IN13 and transmit the output signal to the latch unit 441. Here, the PMOS transistor P4 is connected between the common connection terminal of the pull-up unit 439 and the pull-down unit 440 and the external power supply VDD, and the PMOS transistor P4 is turned on and turned on by the power signal pwup. Is turned off. The latch unit 441 includes inverters IN14 and IN15, and inverts and holds the output signals of the pull-up unit 439 and the pull-down unit 440, and also inverts the output signals to invert the fourth control signal tem2. ) That is, when the enable signal en is enabled at the high level, the second output unit 435 is enabled to output the fourth control signal tem2.                     

The third control means 430 has the chip select signal csb de-selected to a high level, the address control signal adb to a low level, and the enable signal en to a high level. When enabled, the fourth control signal is output at a high level. In addition, the third control means 430, the chip select signal (csb) is deselected to a high level, the address control signal (adb) is enabled to a low level, the enable signal (en) to a high level When enabled and the first control signal tsm is enabled at a high level, the third control signal tme1 is enabled at a high level and output. That is, when the memory device is switched to the test mode, the third control means 430 that receives the chip select signal csb, the address control signal adb, and the first control signal tms are the third and the third. 4 The control signals tme1 and tme2 are outputted to enable the decoder 14 shown in FIG. Accordingly, the decoder 14 causes the decoder 14 to apply the test mode signal tm to the memory device in accordance with the address signal add transmitted from the transfer means 12, so that the memory device performs the test mode operation.

FIG. 5 is a circuit diagram showing the decoder 14 in the test mode device of the memory device shown in FIG.

The decoder 14 may include a first switching unit 51 connected to an external power supply VDD, a second switching unit 52 connected to a ground terminal, and between the first switching unit 51 and the second switching unit 52. And an input unit 53 connected to the inverter, and inverters IN19 and IN20. The first switching unit 51 includes a PMOS transistor P5, and the second switching unit 52 includes an NMOS transistor N5. The first switching unit 51 is turned on and off by the fourth control signal tem2, and the second switching unit 52 is turned on and off by the third control signal tme1. The input unit 53 includes NMOS transistors N6 and N7 connected in series between the first switching unit 51 and the second switching unit 53. As the first control signal tms is enabled and the transmission means 12 is turned on, the input unit 53 receives the address signals add1 and add2 from the transmission means 12. At this time, when the switching units 51 and 52 are turned on by the third and fourth control signals tme1 and tme2, the address signals add1 and add2 are applied to the latch unit 54. The latch unit 54 applies the test mode signal tm to the memory device via the inverters IN19 and IN20, and as a result, the memory device performs a test mode operation.

In the operation mode control apparatus of the memory device according to the present invention, as shown in FIG. 6, the chip select signal csb is selected at a low level, and the address control signal adb is enabled at a low level. Next, when the chip select signal csb is deselected to a high level (t1 to t2), the first and fourth control signals tms and tme2 are enabled to a high level, but the third control signal ( tme1 is disabled at the low level and the second control signal nms is enabled at the high level, so that the memory device performs a normal mode operation. That is, in the timing period t1 to t2, the conventional memory device performs the test mode operation, but the memory device according to the present invention performs the normal mode operation.

According to the configuration as described above of the present invention, by preventing the test mode operation is performed in the normal mode section of the memory device, it is possible to operate the memory device normally in all timing sections.                     

While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. It will be readily apparent to one of ordinary skill in the art that modifications and variations can be made.

Claims (9)

In the operation mode control apparatus of the memory device, First and second control means for receiving a chip select signal and an address control signal and outputting first and second control signals, respectively; And third control means for receiving the chip selection signal, the address control signal, the enable signal, and the output signal of the first control means and outputting third and fourth control signals. When the memory device is in the normal mode, the second control means is enabled to enable the second control signal, And when the memory device is in the test mode, the first and third control means are enabled to enable the first and third and fourth control signals. The method of claim 1, The first control means, A first inverter receiving the address control signal; A first NAND gate configured to receive an output signal of the inverter and the chip select signal; And a first delay unit and a second NAND gate, respectively, for receiving the output signal of the NAND gate. The output signal of the first delay is applied to the second NAND gate, And when the chip select signal is deselected and the address control signal is enabled, enable and output the first control signal. The method of claim 1, The second control means, An input unit configured to receive the chip select signal and the address control signal; A delay unit for receiving an output signal of the input unit; A first NOR gate configured to receive the chip select signal, the address control signal, and an output signal of the delay unit; A first delay unit for receiving an output signal of the first NOR gate; A first pulse generator for receiving an output signal of the first delay unit and outputting a pulse signal; And And a first inverter for inverting the pulse signal. And when the chip select signal is selected and the address control signal is enabled, enable and output the second control signal. The method of claim 3, wherein The input unit, A second NOR gate receiving the chip select signal and the address control signal; A second inverter configured to receive the address control signal; A first NAND gate configured to receive the chip select signal and an output signal of the second inverter; A second delay unit configured to receive an output signal of the first NAND gate; And And a third inverter configured to receive an output signal of the second delay device. The method of claim 4, wherein The delay unit, A second NAND gate configured to receive an output signal of the second NOR gate and an output signal of the third inverter; A third delay unit configured to receive an output signal of the second NAND gate; A third NAND gate configured to receive an output signal of the third delay unit and an output signal of the second NAND gate; A fourth delay unit for receiving an output signal of the third NAND gate; And And a fourth inverter configured to receive the output signal of the fourth delay device. The method of claim 1, The third control means, A buffer unit configured to receive the chip select signal and the address control signal; A first latch unit configured to receive an output signal of the buffer unit; A first NAND gate receiving the output signal of the latch unit and the enable signal at all times; A first pulse generator receiving the output signal of the first NAND gate and outputting a pulse signal; A third inverter for inverting the pulse signal; A first output unit configured to receive the output signal of the third inverter and the first control signal and output the third control signal; And And a second output unit receiving the output signal of the third inverter and the enable signal and outputting the fourth control signal. The chip select signal is deselected, the address control signal and the enable signal are enabled, and when the first control signal is enabled, the third control signal is enabled and output; And when the chip select signal is deselected and the address control signal and the enable signal are enabled, the fourth control signal is enabled and output. The method of claim 6, The buffer unit, A first switching unit connected to an external power source; A second switching unit connected to a ground terminal; And a CMOS buffer connected between the first and second switching units, The first switching unit inverts and receives the chip select signal. The second switching unit receives the chip select signal, And the CMOS buffer receives the address control signal by inverting the address control signal. The method of claim 7, wherein The first output unit, And an end configured by a second NAND gate and a fourth inverter, wherein the second NAND gate receives an output signal of the third inverter and the first control signal. The method of claim 7, wherein The second output unit, A pull-up unit and a pull-down unit connected in series between the external power source and the ground terminal; And a second latch unit configured to receive output signals of the pull up unit and the pull down unit, The enable signal is applied to the pull-up unit, And an output signal of the third inverter is applied to the pull-down part.

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