KR100991979B1 - Synchronization apparatus and method for multiple CODEC DVR system - Google Patents

Abstract

The present invention relates to an apparatus and a method for synchronizing between a plurality of codec chips, in a digital video recorder having a plurality of video codecs, control of codecs, sharing of hard disks, and channel-to-channel through chip-level synchronization between a plurality of codec chips. Provided are a synchronization device between a plurality of codec chips capable of easily controlling video / audio synchronization, and a method thereof. According to an aspect of the present invention, there is provided a synchronization device between a plurality of codec chips, comprising: a reference counter for repeatedly counting unit times at predetermined time intervals according to offset values set differently based on a synchronization signal application order of the codec chips; And a pulse generator for generating a unit time period pulse according to the output of the reference counter. The pulse generator may be embedded in each codec chip, and the offset value of the reference count is a count start value of the reference counter and is input from an external device. The reference counter is loaded according to the signal. According to the above configuration, the present invention can easily control a plurality of codecs, adjust the stream input / output point of time, enable efficient hard disk sharing, and store video / audio according to time. The search for the synchronization of the voice is easy to effect.

Synchronization, digital video recorder, DVR, codec

Description

Synchronization apparatus and method for multiple CODEC DVR systems

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for synchronizing between a plurality of codec chips. In particular, in a digital video recorder having a plurality of video codecs, control of codecs, sharing of a hard disk, and The present invention relates to a synchronization device between a plurality of codec chips capable of easily controlling video / audio synchronization between channels, and a method thereof.

As a device for recording a video signal photographed by a surveillance camera based on digital image compression technology, a digital video recorder (DVR) has emerged.

This is distinguished from a conventional analog storage device (VCR). The input video signal can be digitized and compressed and stored in a hard disk (storage) which is a storage device.

As such, the number of recording / playback videos per unit time is increasing in response to user demand in devices having video recording / playback as a core function.

Accordingly, the processing power of the video codec for recording / reproducing is also expanding from a single channel to a plurality of channels.

On the other hand, since most existing video recorder devices use a single codec, the recording / playback capability of the system is determined by the specification of the codec.

To solve this problem, a device such as a digital video recorder may provide a desired performance by using a plurality of codecs.

However, even when a plurality of codecs are used, a separate device for synchronizing codecs is not provided, and thus the codecs are operated under asynchronous operation. In this case, there is a problem in that synchronization support is difficult at the system level.

The present invention has been proposed to solve the above problems, and an object of the present invention is to provide an apparatus and a method for synchronizing a plurality of codec chips capable of implementing chip level synchronization between a plurality of codec chips in a digital video recorder.

The present invention for achieving the above object is a reference for repeatedly counting the unit time at a predetermined time interval according to the offset value set differently based on the synchronization signal application order of the codec chip in a synchronization device between a plurality of codec chip A counter; And a pulse generator for generating a unit time period pulse according to the output of the reference counter. The pulse generator may be embedded in each codec chip, and the offset value of the reference count is a count start value of the reference counter. The reference counter is loaded according to a synchronization signal.

Preferably, the reference counter may repeatedly count one second.

Preferably, the pulse generator may be a comparator that outputs a pulse only when the value is the same by comparing a preset value and an output of the reference counter according to the order of storing the output signal of the codec chip.

The present invention may further include a first conversion unit for converting the input external synchronization signal into a set polarity.

The present invention may further include a second converter converting the output of the pulse generator into a set polarity and outputting the result to the outside.

Preferably, the first transform unit or the second transform unit may be an exclusive OR circuit.

A digital video recorder according to another aspect of the present invention is characterized in that at least two codec chips of a plurality of codec chips in which any one of the synchronization devices are incorporated are serially connected such that synchronization signals are sequentially input.

According to still another aspect of the present invention, there is provided a synchronization method between a plurality of codec chips, including: a setting step of differently setting an offset value of a count for generating pulses according to a synchronization signal application order of the codec chip; An initialization step of starting a repetition count of a unit time at a predetermined time interval according to a synchronization signal input from the outside based on the offset value; A generation step of generating a unit time period pulse in which a generation time is changed according to a value set based on an order of storing an output signal of the codec chip based on the count value; And converting the generated pulse according to a set polarity and outputting the result to the outside.

Preferably, the initialization step may convert the input external synchronization signal to a set polarity.

The apparatus and method for synchronizing between a plurality of codec chips according to the present invention are easy to control a plurality of codecs through the synchronization of a plurality of codec chips, and the stream input / output timing can be adjusted to enable efficient hard disk sharing, It is possible to store video / audio by time, so it is easy to search for synchronization of multi-channel video / audio.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a synchronization device between a plurality of codec chips according to an embodiment of the present invention.

The synchronization device 100 is embedded in a codec chip mounted on a digital video recorder as described below, and includes a first converter 110 for converting an external synchronization signal and a reference counter 120 for performing a reference count for the synchronization signal. ), A pulse generator 130 for generating a pulse based on the reference count, and a second converter 140 for converting an external output synchronization signal.

The first converter 110 converts a synchronization signal input from the outside according to the set input polarity for the operation of the reference counter 120. Here, the synchronization input from the outside is a frame synchronization signal output from the codec of the preceding stage among the plurality of codecs.

The external synchronization signal is used as a load strobe of the reference counter 120. For example, when the load strobe is set to '1', the external synchronization signal is configured to load an offset value. ) Adjusts the polarity of the external synchronization signal accordingly.

Since the characteristics of the noise vary depending on the polarity of the signal on the board, the first converter 110 sets the external synchronization signal to active low or active high.

For example, the first converter 110 operates as a buffer function when it is not necessary to change the polarity of the external synchronization signal, and functions as a NOT logic circuit when it is necessary to change the polarity of the external synchronization signal. It works.

Reference count

The reference counter 120 repeatedly counts the unit time at predetermined time intervals according to the offset value, and the offset value is loaded according to the external synchronization signal.

For example, the reference counter 120 repeatedly counts 1 second. For the National Television System Committee (NTSC) method based on 30 frames per second (fps) frame rate, the reference counter 120 counts 60 times at an interval of 16.6 ms. Seconds are counted, and for the PAL (Phase Alternation by Line) method based on a frame rate of 25 fps, 50 counts are performed every 20.0 ms to count one second.

Here, the offset value is a count start value of the reference counter 120, which is a value for time alignment between a plurality of codecs. That is, the offset value is set differently according to the synchronization signal application procedure of the codec chip as will be described later.

More specifically, the output pulse of the synchronization device 100 embedded in the first stage codec chip, that is, the frame synchronization signal is input to the synchronization device 100 embedded in the second stage codec chip. The synchronization signal is serially applied to the synchronization device 100 embedded in the codec chip.

At this time, the reference counter 120 of each codec chip starts counting with a certain amount of time difference, and in order to match the time difference, the count start value of the reference counter 120 of each codec chip is set different from each other. It is set to be the same count value at time.

On the other hand, the loading of the offset value is performed in accordance with the input of the external synchronization time signal, and as a result is synchronized to the external synchronization signal, that is, the external reference pulse.

As such, the reference counter 120 has a function of synchronizing an internal reference pulse generated by the codec chip with an external reference pulse input and a function of moving the offset set by the host controller.

Frame Sync Pulse Generation

The pulse generator 130 generates a unit time period pulse according to the output of the reference counter 120.

That is, the pulse generator 130 generates a periodic pulse of 1 second T based on the internal reference pulse output from the reference counter 120 and uses it as a reference pulse of the codec chip operation.

Here, the pulse generator 130 is input with a setting value with the output of the reference counter 120, the setting value is set according to the order of storing the output signal of the codec chip. As will be described later, when synchronization between the codec chips is synchronized, when the converted video signal is stored in the storage unit, it can be adjusted according to a preset schedule. Can be.

The output of the pulse generator 130 is used as an internal reference pulse and is output to the outside for synchronization between codec chips.

Pulse polarity conversion

When the output of the pulse generator 130 is output to the outside, the second converter 140 converts the output to the set polarity and outputs the output to the outside. Here, the converted pulse is output to the outside, for example, to the next stage codec chip for synchronization of the codec chip.

Similar to the first converter 110, the second converter 140 performs buffer function or NOT logic according to an output polarity signal that determines whether the output signal is output to one of active high and active low. It functions as a circuit.

2 is a detailed block diagram of a synchronization device between a plurality of codec chips according to an embodiment of the present invention.

The synchronization device 200 generates a pulse based on a first exclusive OR circuit 210 for converting an external synchronization signal, a reference counter 120 for performing a reference count for the synchronization signal, and a reference count. Comparator 230 and a second exclusive logic circuit 240 for converting the external output synchronization signal.

As an example of the first conversion unit 110 of FIG. 1, the first exclusive OR circuit 210 converts a polarity of a synchronization signal input from the outside according to a preset input polarity.

The reference counter 220 operates by receiving a system clock from the outside and is initialized by a reset signal. As described above, the reference counter 120 is loaded with an offset value according to the output signal of the first exclusive OR circuit 210 and starts counting according to the offset value.

The comparator 230 compares the output of the reference counter 120 with a preset value and outputs a pulse only when the value is the same. For example, when all of the set values are set to "0", when the output of the reference counter 120 is 0, a periodic pulse used as a synchronization signal is generated.

Here, by adjusting this setting value, an end point of encoding or decoding of each codec chip may be adjusted to enable scheduling for storing the data stream.

The second exclusive logical sum circuit 240 is an example of the second converter 140 of FIG. 1 and converts the polarity of the synchronization signal output to the outside according to a preset output polarity.

Sync multiple codecs

3 is a block diagram of a digital video recorder to which a synchronization device between a plurality of codec chips according to an embodiment of the present invention is applied.

The digital video recorder 300 includes a plurality of video decoders 310 that receive video signals from a camera, a video controller 320 that controls the outputs of the plurality of video decoders 310, and a plurality of video decoders 310. A plurality of video codecs 330 for encoding or decoding an image corresponding to each other, a host controller 340 for controlling the video codec 330, and a storage for storing video signals encoded by the video codec 330 ( 350).

The video decoder 310 is composed of individual chips and receives and decodes an output video signal of a camera for each channel. For example, the video decoder 310 is a four-channel decoder to which four cameras are connected.

The video controller 320 is composed of a separate chip, and switches the decoded signals of 16 channels input from a plurality of four-channel video decoders 310, for example, four video decoders 310, to the corresponding video codec 330. .

The video codec 330 is composed of individual chips and includes a synchronization device 100 as shown in FIGS. 1 and 2, and receives and encodes a video signal corresponding to the corresponding video decoder 310.

The video codec 330 receives a reference sync signal or a previous sync signal output as a sync signal and generates a sync signal by the sync device 100, and outputs the generated sync signal to the video codec 330 at a later stage. do.

In FIG. 3, the video codec 330 is serially connected so that the synchronization signals are sequentially input. However, at least two video codecs 330 of the plurality of video codecs 330 are serially connected so that the synchronization signals are sequentially input. Can be connected. That is, it may be configured as one to N for inputting the output synchronization signal of one video codec 330 to the plurality of video codec 330.

Meanwhile, the video codec 330 encodes a video signal for each channel and a synchronization signal for each frame or field encoding is used internally from the system clock, and a synchronization device (for synchronization between the video codecs 330) is used. 100) generates a synchronization signal of one second period.

The host controller 340 stores the video signals output from the plurality of video codecs 330 in the storage 350 according to a preset schedule.

In addition, the host controller 340 generates an input polarity, an output polarity, an offset, and a setting value used in the synchronization device 100 according to a user's setting, and applies it to the video codec 330.

The storage 350 stores a video signal encoded by the video codec 330 and may be, for example, a hard disk driver (HDD).

FIG. 4 is a timing diagram illustrating output time points of a result of asynchronous and synchronous codecs, and FIG. 5 is a diagram illustrating a storage structure of a stream generated by a codec.

As shown in Fig. 4, if the synchronization between each video codec 330 is not correct, it is difficult to plan the storage and other processing of the video signal due to irregular end points of encoding or decoding.

By synchronizing each of the video codecs 330 by the synchronization device 100, the operation of the video codec 330 can be predicted, thereby simplifying the control, and through the operation of the synchronized video codec 330, Efficient management of streams encoded with video signals generated from cameras makes it easy to search for the streams and synchronize images between them during playback.

Codec chip  Synchronization method between

Hereinafter, a synchronization method between a plurality of codec chips of the present invention will be described with reference to FIG. 6.

6 is a flowchart illustrating a synchronization method between a plurality of codec chips according to an embodiment of the present invention.

The synchronization method between a plurality of codec chips includes a setting step of setting an offset value of a count for generating a pulse (step S601), and a repetition count of unit time at a predetermined time interval according to a synchronization signal input from the outside based on the offset value. An initializing step (step S602) to be started, a generating step (step S603) of generating unit time period pulses according to the count value, and an output step (step S604) of converting the generated pulses according to a set polarity and outputting them to the outside; Include.

More specifically, first, an offset value is set for time alignment between a plurality of codec chips (step S601).

As shown in FIG. 3, the codec chip is applied with a synchronization signal in series, and the offset value is set differently according to the synchronization signal application order of the codec chip.

That is, after the count is started in the synchronization device 100 embedded in the first stage codec chip, when the second stage codec chip operates according to the synchronization signal of the first stage codec chip, the synchronization embedded in the second stage codec chip is performed. The apparatus 100 sets the offset value to have the same value as the count disclosed in the first stage.

As a result, the count start time of the codec chips of each stage is set differently so as to have the same count value at the same time as a whole.

At this time, a setting value according to a schedule for storing the output video signal of the codec chip is also set. That is, a setting value for controlling the end point of the output video signal of the codec chip is set.

In this way, when the setting is completed, each codec starts counting based on the offset value of the internal reference counter according to the input external synchronization signal (step S602).

Here, the offset value is loaded into the reference counter according to the external synchronization signal. At this time, the external synchronization signal is input to the set polarity for the loaded operation. That is, the polarity of the external synchronization signal is changed depending on whether the reference counter is operated in the active low or the active high with respect to the external synchronization signal.

Next, a frame synchronizing signal is generated according to the reference count value (step S603).

At this time, the pulse generation time of the frame synchronization signal may be changed in the order of storing the output signal of the codec chip by the setting value set in the setting step (step S601). The synchronization signal generated as described above may be used as an internal synchronization signal of a codec on which the synchronization device 100 is mounted or may be output to the outside.

In this way, the synchronization signal used internally is output to the outside for use as a reference for synchronization of the next stage codec chip (step S604).

At this time, it is preferable to change the polarity of the output synchronization signal according to the set output polarity.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those skilled in the art.

1 is a schematic block diagram of a synchronization device between a plurality of codec chips according to an embodiment of the present invention;

2 is a detailed block diagram of a synchronization device between a plurality of codec chips according to an embodiment of the present invention.

3 is a block diagram of a digital video recorder to which a synchronization device between a plurality of codec chips according to an embodiment of the present invention is applied;

4 is a timing diagram showing an output time point of a result of asynchronous and synchronous codec;

5 is a diagram showing a storage structure of a stream generated by a codec;

6 is a flowchart illustrating a synchronization method between a plurality of codec chips according to an embodiment of the present invention.

7 is a timing diagram of a conventional asynchronous codec.

Explanation of symbols on the main parts of the drawings

100: synchronization device 110: first conversion unit

120: reference counter 130: pulse generator

140: second conversion unit 300: digital video recorder

310: video decoder 320: video controller

330 video codec 340 host controller (CPU)

350: storage unit

Claims (9)

In the synchronization device between a plurality of codec chips, A reference counter for repeatedly counting unit times at predetermined time intervals according to offset values set differently based on the synchronization signal application order of the codec chip; A pulse generator for generating a unit time period pulse according to the output of the reference counter; And an offset value of the reference count is a count start value of the reference counter, and is loaded into the reference counter according to a synchronization signal input from the outside. The method of claim 1, And the reference counter repeatedly counts one second. The method of claim 1, The pulse generator is a synchronization device between a plurality of codec chips, characterized in that the comparator for outputting a pulse only when the same value by comparing the output of the reference value and the preset value according to the order of storing the output signal of the codec chip . The method of claim 1, And a first converter configured to convert the input external synchronization signal into a set polarity. The method of claim 1, And a second converter configured to convert the output of the pulse generator into a set polarity and output the pulse generator to the outside. The method according to claim 4 or 5, And the first or second transform unit is an exclusive OR circuit. A digital video recorder, characterized in that at least two codec chips of a plurality of codec chips having a synchronization device according to any one of claims 1 to 5 are connected in series so that synchronization signals are sequentially input. In the synchronization method between a plurality of codec chips, A setting step of setting an offset value of a count for generating a pulse differently according to a synchronization signal application order of the codec chip; An initialization step of starting a repetition count of a unit time at a predetermined time interval according to a synchronization signal input from the outside based on the offset value; A generation step of generating a unit time period pulse whose generation time is changed according to a value set based on an order of storing the output signal of the codec chip based on the count value; And converting the generated pulses according to a set polarity and outputting them to the outside. The method of claim 8, And the initializing step converts the input external synchronization signal into a set polarity.

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