KR100984346B1 - Liquid crystal display having multi domain and panel for the same - Google Patents

Abstract

A gate line formed on an insulating substrate, a data line insulated from and intersecting the gate line, a first pixel electrode, a gate line, a data line, and a first pixel electrode formed in each pixel region defined by the intersection of the gate line and the data line A liquid crystal display including thin film transistors each having three terminals connected to each other, and a second pixel electrode formed in each pixel region and overlapping a coupling electrode connected to the first pixel electrode and capacitively coupled to the first pixel electrode Arrange the device. In this case, the first or second pixel electrode has a cutout that divides and aligns the liquid crystal molecules. The cutout does not overlap with the coupling electrode, so that the coupling electrode is completely covered with the first or second pixel electrode.

  In this way, a wide viewing angle liquid crystal display device having improved side visibility can be obtained, and a test can be prevented from occurring at the end of the cutout portion, thereby ensuring display characteristics.

LCD, vertical alignment, cutout, coupling electrode

Description

Multi-domain liquid crystal display and display panel used therefor {LIQUID CRYSTAL DISPLAY HAVING MULTI DOMAIN AND PANEL FOR THE SAME}

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

2 is a layout view of a color filter display panel for a liquid crystal display according to a first embodiment of the present invention;

3 is a layout view of a liquid crystal display according to a first exemplary embodiment of the present invention;

4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3,

5 is a circuit diagram of a liquid crystal display according to a first embodiment of the present invention;

6 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view of the thin film transistor array panel of FIG. 6 taken along the line VII-VII ′. FIG.

8 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a third exemplary embodiment of the present invention.

9 is a circuit diagram of a liquid crystal display device including the thin film transistor array panel according to the third exemplary embodiment of the present invention.                 

121 gate line, 123 gate electrode,

133a, 133b, 133c sustain electrode, 176 bond electrode,

171 data lines, 173 source electrodes,

175 drain electrodes, 190 pixel electrodes,

191, 192, 193 incisions, 151, 154 amorphous silicon layer,

270 reference electrode, 271, 272, 273 incision

The present invention relates to a liquid crystal display device and a display panel used therefor.

In general, a liquid crystal display device injects a liquid crystal material between an upper display panel on which a common electrode and a color filter are formed, and a lower display panel on which a thin film transistor and a pixel electrode are formed. By applying a different voltage to form an electric field to change the arrangement of the liquid crystal molecules, and through this to adjust the transmittance of light to represent the image.

However, it is an important disadvantage that the liquid crystal display device has a narrow viewing angle. In order to overcome these disadvantages, various methods for widening the viewing angle have been developed. Among them, liquid crystal molecules are oriented vertically with respect to the upper and lower display panels, and a method of forming a constant incision pattern or forming protrusions on the pixel electrode and the common electrode that is opposite thereto. This is becoming potent.                         

As a method of forming an incision pattern, an incision pattern is formed on each of the pixel electrode and the common electrode, and the viewing angle is widened by adjusting the direction in which the liquid crystal molecules lie down using a fringe field formed by the incision patterns. .

The protrusions are formed by forming protrusions on the pixel electrode and the common electrode formed on the upper and lower display panels, respectively, to adjust the lying direction of the liquid crystal molecules using an electric field distorted by the protrusions.

In another method, an incision pattern is formed on the pixel electrode formed on the lower panel, and protrusions are formed on the common electrode formed on the upper panel, so that the liquid crystal lies down using a fringe field formed by the incision pattern and the protrusion. There is a way to form a domain by controlling.

In such a multi-domain liquid crystal display, the gray scale inversion reference viewing angle defined as a contrast ratio reference viewing angle based on a contrast ratio of 1:10 or a limit angle of luminance inversion between gray scales is excellent, more than 80 ° in all directions. However, a side gamma curve distortion phenomenon occurs in which the front gamma curve and the side gamma curve do not coincide with each other, thereby inferior visibility in the left and right sides compared to the TN (twisted nematic) mode liquid crystal display. For example, in the patterned vertically aligned (PVA) mode, which makes an incision by domain dividing means, the screen looks brighter and the color tends to shift toward white as the side faces. Occasionally, the picture appears clumped and disappears. However, as liquid crystal display devices are used for multimedia in recent years, visibility has become increasingly important as pictures and moving pictures are viewed.

On the other hand, when the domain is formed by adjusting the lying direction of the liquid crystal molecules using the projection pattern or the cutout, the liquid crystal molecules positioned at the edge of the pixel are affected by the distorted electric field, thereby disorienting the orientation. As a result, a texture or a light leakage phenomenon may be caused to deteriorate display characteristics.

The technical problem to be achieved by the present invention is to implement a multi-domain liquid crystal display device having excellent visibility.

Another object of the present invention is to provide a thin film transistor array panel capable of minimizing texture or light leakage.

In order to solve this problem, in the present invention, the pixel electrode is divided into two and different potentials are applied to the two sub pixel electrodes.

In this case, the two sub pixel electrodes are capacitively coupled through the coupling electrode, and the coupling electrode is completely covered with at least one sub pixel electrode, or coincides with the arrangement direction of the liquid crystal and the electric field direction formed between the two sub pixel electrodes. Two sub pixel electrodes are arranged.

More specifically, in the thin film transistor array panel according to the exemplary embodiment of the present invention, a first signal line is formed on an insulating substrate, and a second signal line insulated from and intersecting the first signal line is formed. A first pixel electrode is formed in each pixel region defined by the intersection of the first signal line and the second signal line, and the first thin film transistor having three terminals connected to the first signal line, the second signal line, and the first pixel electrode, respectively. Formed. In addition, a second pixel electrode capacitively coupled to the pixel region first pixel electrode is formed, and a coupling electrode connected to the first pixel electrode and overlapping the second pixel electrode in an insulated state is formed. . In this case, at least one of the first pixel electrode and the second pixel electrode has first domain dividing means for dividing and aligning the liquid crystal molecules, and the coupling electrode and the first domain dividing means do not overlap.

The first domain dividing means is an incision, and the coupling electrode is completely covered with the first or second pixel electrode.

The coupling electrode extends from the drain electrode among the three terminals of the first thin film transistor.

A gate insulating layer formed between the first signal line and the second signal line, and a passivation layer formed between the second signal line and the first and second pixel electrodes, wherein the coupling electrode is formed through a contact hole formed in the passivation layer; It is preferable to be connected to one pixel electrode.

It is preferable that two long sides of the boundary lines adjacent to each other between the first pixel electrode and the second pixel electrode form 45 ° with the first signal line.

The display device may further include a second thin film transistor insulated from and intersecting the second signal line, and having three terminals connected to the third signal line, the first signal line, the second pixel electrode, and the third signal line to which the reference potential is applied. In this case, the first thin film transistor and the second thin film transistor in the same pixel area are respectively connected to adjacent first signal lines.

The direction of the electric field formed between the first pixel electrode and the second pixel electrode is oriented in the same direction as the alignment direction of the liquid crystal molecules oriented by the cutout separating the first pixel electrode and the second pixel electrode. The second pixel electrode is arranged.

In addition, the liquid crystal display according to the exemplary embodiment of the present invention includes a common electrode display panel including the thin film transistor array panel and a common electrode facing the first and second pixel electrodes to form an electric field for driving the liquid crystal molecules.

The common electrode preferably has second domain dividing means for dividing the pixel region into a plurality of small domains together with the first domain dividing means.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.                     

Next, a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention, FIG. 2 is a layout view of a color filter substrate for a liquid crystal display according to a first embodiment of the present invention, and FIG. 4 is a layout view of a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line IV-IV 'of FIG. 3.

The liquid crystal display according to the exemplary embodiment of the present invention is a liquid crystal which is injected between the lower display panel 100 and the upper display panel 200 facing the lower display panel 100 and the lower display panel 100 and the upper display panel 200 and oriented perpendicular to the display panel. The liquid crystal layer 310 includes molecules 310.

First, the thin film transistor array panel, which is the lower panel 100, has the following configuration.

First and second pixel electrodes 190a and 190b made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) are formed on the insulating substrate 110 made of a transparent insulating material such as glass. have. The first pixel electrode 190a is connected to the thin film transistor to receive an image signal voltage, and the second pixel electrode 190b overlaps the coupling electrode 176b connected to the first pixel electrode 190a so that the first pixel electrode 190a is connected to the thin film transistor. It is electromagnetically coupled (capacitively coupled) with the pixel electrode 190a. In this case, the thin film transistor is connected to the gate line 121 transmitting the scan signal and the data line 171 transmitting the image signal, respectively, to turn on the image signal applied to the first pixel electrode 190a according to the scan signal. on) off. In this case, the first and second pixel electrodes 190a and 190b have cutouts 191, 192, 193, 194, and 195, and the coupling electrode 176b has a cutout 192 of the second pixel electrode 190b. 193, 194 with branches extending parallel to them. In addition, the lower polarizing plate 12 is attached to the lower surface of the insulating substrate 110. Here, the first and second pixel electrodes 190a and 190b may not be made of a transparent material in the case of a reflective liquid crystal display device, and in this case, the lower polarizer 12 is also unnecessary.

Next, the configuration of the upper panel 200 is as follows.

It is also made of a black matrix 220 to prevent light leakage on the lower surface of the insulating substrate 210 made of a transparent insulating material such as glass, a color filter 230 of red, green, and blue and a transparent conductive material such as ITO or IZO. The common electrode 270 is formed. Here, the cutouts 271, 272, and 273 are formed in the common electrode 270. The black matrix 220 may be formed not only in the peripheral portion of the pixel region but also in the portion overlapping the cutouts 271, 272, and 273 of the common electrode 270. This is to prevent light leakage caused by the cutouts 271, 272, and 273.

The lower panel for the liquid crystal display device, that is, the thin film transistor array panel 100 according to the first embodiment, will be described in more detail.

A plurality of gate lines 121 and storage electrode lines 131 extending mainly in the horizontal direction are formed on the lower insulating substrate 110.

The gate line 121 has a plurality of portions extending up and down to form a gate electrode 123, and one end portion 125 is widely extended for connection with an external circuit.                     

Each of the storage electrode lines 131 includes a plurality of storage electrodes 133a, 133b, 133c, and 133d that extend out therefrom and are disposed at edges of the pixel. Three of the storage electrodes 133a, 133b, and 133c of the pair of storage electrodes 133a, 133b, 133c, and 133d extend in the vertical direction, and the other storage electrode 133d that extends in the horizontal direction is located at the bottom of the pixel. Position and connects the two sustain electrodes 133a and 133c. In this case, each of the storage electrode lines 131 may be formed of two or more horizontal lines.

The gate line 121 and the storage electrode line 131 are made of metal such as Al, Al alloy, Ag, Ag alloy, Cr, Ti, Ta, Mo, or the like. As shown in FIG. 4, the gate line 121 and the storage electrode line 131 of the present embodiment are formed of a single layer, but have a high physical and chemical properties such as Cr, Mo, Ti, Ta, and the like and an Al series having a small specific resistance or It may be made of a double layer including an Ag-based metal layer. In addition, the gate line 121 and the storage electrode line 131 may be made of various metals or conductors.

The sidewalls of the gate line 121 and the storage electrode line 131 are inclined, and the inclination angle with respect to the horizontal plane is 30 to 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or the like is formed on the gate line 121 and the storage electrode line 131.

A plurality of thin film transistor drain electrodes 175 and a plurality of coupling electrodes 176b are formed on the gate insulating layer 140, as well as a plurality of data lines 171. Each data line 171 extends mainly in a vertical direction, and forms a plurality of branches toward each drain electrode 175 to form a source electrode 173 of the thin film transistor. The coupling electrode 176 is connected to the drain electrode 175 and overlaps the V-shaped refracted portion of the branch extending in parallel between the cutouts 192, 193, and 194 and the storage electrodes 133b and 133c. To include the part.

Like the gate line 121, the data line 171, the drain electrode 175, and the coupling electrode 176 may be made of a material such as chromium and aluminum, and may be formed of a single layer or multiple layers.

Under the data line 171 and the drain electrode 175, a plurality of linear semiconductors 151 extending mainly vertically along the data line 171 are formed. Each linear semiconductor 151 made of amorphous silicon branches to the gate electrode 123, the source electrode 173, and the drain electrode 175 to form a channel portion 154 of the thin film transistor.

Between the semiconductor 151 and the data line 171 and the drain electrode 175, a plurality of linear ohmic contacts 161 and an island type drain resistive contact member 165 to reduce contact resistance between the two. Is formed. The ohmic contact 161 may include a source ohmic contact 163 positioned under the source electrode 173, and these 161 and 165 may be made of amorphous silicon doped with silicide or n-type impurities at a high concentration. .

A passivation layer 180 made of an inorganic insulator such as silicon nitride or an organic insulator such as resin is formed on the data line 171 and the drain electrode 175.

The passivation layer 180 is provided with a plurality of contact holes 181 and 183 exposing at least a portion of the drain electrode 175 and the end portion 179 of the data line 171, respectively, and the end of the gate line 121. A plurality of contact holes 182, 184, and 185 exposing portions 125 and portions of the storage electrode lines 131 penetrate the gate insulating layer 140 and the passivation layer 180, respectively.

A plurality of contact assistants 95 and 97 and a plurality of storage bridge 91 are formed on the passivation layer 180, as well as a plurality of pixel electrodes 190a and 190b. The pixel electrodes 190a and 190b, the contact auxiliary members 95 and 97, and the connection legs 91 may be formed of a transparent conductor such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a light reflection characteristic such as aluminum (Al). This excellent opaque conductor is made.

The pixel electrodes 190a and 190b are classified into the first pixel electrode 190a and the second pixel electrode 190b, and the first pixel electrode 190a is connected to the drain electrode 175 through the contact hole 181a. The second pixel electrode 190b overlaps the coupling electrode 176 connected to the drain electrode 175. Therefore, the second pixel electrode 190b is electromagnetically coupled (capacitively coupled) to the first pixel electrode 190a.

The cutout 192 dividing the first pixel electrode 190a and the second pixel electrode 190b is divided into a portion perpendicular to a portion that forms a 45 ° angle with respect to the gate line 121, and two portions that form a 45 ° portion. The part is longer in length than the vertical part. In addition, the vertical portions are overlapped with the storage electrode 133a, and two portions constituting 45 ° are connected to the vertical portions, and are perpendicular to each other.

The first and second pixel electrodes 190a and 190b have cutouts 191 and 193, respectively, which are 45 ° with respect to the gate line 121, and each of the first and second pixel electrodes 190a and 190b respectively includes the first and second pixel electrodes 190a and 190b. It is formed inside 190b). In addition, the second pixel electrode 190b has a cutout 194. The second pixel electrode 190b penetrates from the right side to the left side of the second pixel electrode 190b, and the inlet is widened. The cutout 193 of the second pixel electrode 190b includes a portion that forms 45 ° with respect to the gate line 121 and a portion that is dug toward the left side from the right side.

The cutouts 191, 192, 193, 194, and 195 defining the shapes of the first pixel electrode 190a, the second pixel electrode 190b, and the shapes of the first and second pixel electrodes 190a and 190b are respectively the gate line 121 and the data line. Substantially mirror image symmetry is achieved with respect to a line (a line parallel to the gate line) that bisects the pixel region defined by intersection 171.

On the passivation layer 180, a storage wiring connecting leg 91 is formed to connect the two storage electrode lines 131 across the gate line 121 and positioned at both sides thereof. The storage wiring connection leg 91 is in contact with the storage electrode 133a and the storage electrode line 131 through the contact holes 183 and 184 penetrating through the passivation layer 180 and the gate insulating layer 140. The storage wiring connection leg 91 serves to electrically connect the entire storage electrode line 131 on the lower substrate 110. The storage electrode line 131 may be used to repair a defect of the gate line 121 or the data line 171 if necessary, and when the laser is irradiated for such repair, the gate line 121 and the sustain wiring connection bridge ( In order to assist the electrical connection of the 91, a leg metal piece may be disposed between the two in the same layer as the data line 171.

The contact auxiliary members 95 and 97 are connected to the end portion 125 of the gate line and the end portion 179 of the data line through the contact holes 182 and 183, respectively.

Meanwhile, the upper panel 200 facing the thin film transistor array panel has the following configuration.

A black matrix 220 is formed on the upper insulating substrate 210 facing the lower insulating substrate 110 to prevent light leakage. The red, green, and blue color filters 230 which are sequentially disposed in the pixel area are formed on the black matrix 220. A common electrode 270 having a plurality of cutouts 271, 272, 273, 274, 275, and 276 is formed on the color filter 230. The common electrode 270 is formed of a transparent conductor such as ITO or indium zinc oxide (IZO).

A pair of cutouts 271, 272, 273, 274, 275, and 276 of the common electrode 270 are cutouts 192 that are boundaries between two pixel electrodes 190a and 190b and cutouts of these 191a and 191b. A portion of 191, 193, and 194, which is positioned at 45 ° with respect to the gate line 121, is disposed at the center thereof, and includes an oblique portion parallel to them and an end portion overlapping the sides of the pixel electrodes 190a and 190b. have. At this time, the end is classified into a longitudinal end part and a horizontal end part.

When the thin film transistor array panel and the color filter display panel having the above structure are aligned and combined, and a liquid crystal material is injected and vertically aligned therebetween, the basic structure of the liquid crystal display according to the exemplary embodiment of the present invention is provided.

When the thin film transistor array panel and the color filter panel are aligned, the cutouts 271, 272, and 273 of the common electrode 270 divide the two pixel electrodes 190a and 190b into a plurality of sub-areas, respectively. In the present embodiment, as illustrated in FIG. 3, the two pixel electrodes 190a and 190b are divided into eight sub-regions. As can be seen in FIG. 3, each subregion is elongated to distinguish the width direction from the length direction.

The portion of the liquid crystal layer 300 between each subregion of the pixel electrodes 190a and 190b and the corresponding subregion of the reference electrode 270 is referred to as a subregion in the future, and these small regions are applied when an electric field is applied. It is classified into eight types according to the average major axis direction of the liquid crystal molecules located therein, which is called domain in the future.

In the liquid crystal display having the structure, the first pixel electrode 190a receives an image signal voltage through the thin film transistor, whereas the voltage of the second pixel electrode 190b varies due to capacitive coupling with the coupling electrode 176. As a result, the voltage of the second pixel electrode 190b is always lower than the voltage of the first pixel electrode 190a. As such, when two pixel electrodes having different voltages are disposed in one pixel area, the two pixel electrodes compensate for each other to reduce distortion of the gamma curve.

Next, the reason why the voltage of the first pixel electrode 190a is lower than the voltage of the second pixel electrode 190b will be described with reference to FIG. 5.

5 is a circuit diagram illustrating a liquid crystal display according to a first exemplary embodiment of the present invention.

In FIG. 5, Clca represents a liquid crystal capacitor formed between the first pixel electrode 190a and the common electrode 270, and Cst represents a storage capacitor formed between the first pixel electrode 190a and the storage electrode line 131. . Clcb represents a liquid crystal capacitor formed between the second pixel electrode 190b and the common electrode 270, and Ccp represents a coupling capacitor formed between the first pixel electrode 190a and the second pixel electrode 190b.

When the voltage of the first pixel electrode 190a with respect to the voltage of the common electrode 270 is called Va, and the voltage of the second pixel electrode 190b is called Vb, according to the voltage division law,

Va = Vb × [Ccp / (Ccp + Clcb)]

Since Ccp / (Ccp + Clcb) is always less than 1, Vb is always smaller than Va.

 On the other hand, by adjusting Ccp, the ratio of Vb to Va can be adjusted. The adjustment of Ccp is possible by adjusting the overlapping area and distance of the coupling electrode 176 and the second pixel electrode 190b. The overlapping area can be easily adjusted by changing the width of the coupling electrode 176, and the distance can be adjusted by changing the formation position of the coupling electrode 176. That is, in the exemplary embodiment of the present invention, the coupling electrode 176 is formed on the same layer as the data line 171, but the coupling electrode 176 and the second pixel electrode 190b are formed on the same layer as the gate line 121. You can increase the distance between them.

In this case, since the second pixel electrode 190b to which the low voltage is transmitted is located below the first pixel electrode 190a to which the high voltage is applied, in the area A, the second pixel electrode 190b to the first pixel electrode 190a. The electric field is formed in the direction, which is similar to the direction in which the liquid crystal molecules divided by the fringe field formed by the cutout 192 in the region A lay down. Therefore, the arrangement of the liquid crystal molecules is not disturbed in the region A, thereby preventing the occurrence of a texture or light leakage, thereby securing display characteristics.

In addition, in the structure of the liquid crystal display according to the exemplary embodiment of the present invention, the coupling electrode 176b is completely covered by the second pixel electrode 190b and the cutouts 191, 192, of the pixel electrodes 190a and 190b are formed. Since the coupling electrode 176b is not exposed at 193, 194, and 195, a test may be prevented from occurring at the edges of the cutouts 191, 192, 193, 194, and 195. In particular, as shown in FIGS. 1 and 3, the boundary line of the cutout 193 of the second pixel electrode 190b is positioned inside the boundary line of the coupling electrode 176b. Therefore, the fringe field formed near the edge of the cutout 193 in the region B is not affected by the coupling electrode 176b, so that a distorted electric field does not occur in the region B and the fringe field is formed by the cutout 193. Only by lying down the liquid crystal molecules are determined. Accordingly, the alignment of the liquid crystal molecules may be prevented from being disturbed due to the electric field distorted in the region B, thereby preventing the occurrence of texture or light leakage, thereby securing display characteristics.

The arrangement and structure of the coupling electrode 176b may be modified in various ways depending on the shape of the cutout, which is a pixel indispensable means, or depending on whether the drain electrode 175 is connected to the first or second pixel electrodes 190a and 190b. . One example of this is described as the second embodiment.

6 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view of the thin film transistor array panel of FIG. 6 taken along the line VII-VII ′.

In the thin film transistor array panel for the liquid crystal display according to the second embodiment, the drain electrode 175 extends below the second pixel electrode 190b and is connected to the second pixel electrode 190b through the contact hole 181b. The coupling electrode 176a overlaps the first pixel electrode 190a and is disposed on both sides of the cutout 191 of the first pixel electrode 190a and is aligned with the common electrode display panel. Branch portions overlapping the cutouts 271, 272, 275, and 276 of the plurality of cutouts 271, 272, 275, and 276. At this time, a portion of the coupling electrode 176a and a portion adjacent to the cutouts 191 and 195 of the first pixel electrode 190a in the region C have a width smaller than that of the other portion. This is to prevent the coupling electrode 176a from being exposed at the cutouts 191 and 195 of the first pixel electrode 190a as in the first exemplary embodiment. As a result, the texture may be prevented from occurring in the edge C region of the pixel as in the first exemplary embodiment.

Meanwhile, the thin film transistor array panel 100 according to the second exemplary embodiment of the present invention includes a plurality of linear semiconductors 151 and 154 and a plurality of ohmic contacts 161, 163 and 165.

In this case, the linear semiconductors 151 and 154 may include the plurality of data lines 171 and the plurality of drain electrodes 175 except for the channel portion 154 of the thin film transistor between the source electrode 173 and the drain electrode 175. It is almost the same flat shape. That is, although the data line 171 and the drain electrode 175 are separated from each other in the channel unit 154, the linear semiconductor 154 is connected without being disconnected to form a channel of the thin film transistor. The ohmic contacts 161, 163, and 165 have the same shape as the data line 171 and the drain electrode 175, respectively.

8 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIG. 9 is a view of a liquid crystal display including the thin film transistor array panel according to the third exemplary embodiment of the present invention. It is a circuit diagram.

First and second pixel electrodes 190a and 190b made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) are formed on the insulating substrate 110 made of a transparent insulating material such as glass. have. The first pixel electrode 190a is electromagnetically coupled (capacitively coupled) to the first pixel electrode 190a by overlapping the coupling electrode 176b connected to the second pixel electrode 190b, and the second thin film. It is connected to the drain electrode 175a of the transistor to receive a reference potential.

In this case, the gate electrode 123 and the source electrode 173 of the first thin film transistor are connected to the main gate line 121 for transmitting the scan signal and the data line 171 for transmitting the image signal, respectively, according to the scan signal. The image signal applied to the second pixel electrode 190b is turned on.

The gate electrode 123a and the source electrode 173a of the second thin film transistor are connected to the front gate line 121 and the sustain electrode connection bridge 91, respectively, and according to a scan signal applied to the front gate line 121. The pixel electrode 190a is refreshed at the reference potential.

The second thin film transistor includes an amorphous silicon layer 155 overlapping the front gate line 121 and an ohmic contact layer (not shown) thereon, and the source electrode 173a of the second thin film transistor includes a passivation layer 180. ) Is connected to the sustain electrode connector 91 through a contact hole 186 penetrating through the contact hole, and the drain electrode 175b of the first thin film transistor is connected to the second pixel through a contact hole 181b penetrating through the passivation layer 180. It is connected to the electrode 190b.                     

 Referring to FIG. 9, a thin film transistor T2 connecting the first pixel electrode to the reference potential is formed, and the gate electrode thereof is connected to the front gate line. Therefore, before the on signal is applied to the main gate line and the image signal is charged to the second pixel electrode, the first pixel electrode is refreshed to the reference electrode potential.

In this case, even if abnormal charge flows into the first pixel electrode, since the first pixel electrode is refreshed at the reference potential every frame, the image signal is not distorted.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights. In particular, the arrangement of the cutouts formed on the pixel electrode and the common electrode may have various variations, and the protrusions may be used as the pixel dividing means for dividing and aligning the liquid crystal molecules instead of the cutouts.

Through the above configuration, the side angle of the liquid crystal display device can be improved, and the viewing angle can be extended. In addition, the edge of the pixel is cut by arranging two pixel electrodes such that the coupling electrode for capacitively coupling the two pixel electrodes is not exposed out of the cutout, or the electric field direction formed between the two pixel electrodes is formed along the alignment direction of the liquid crystal molecules. It is possible to prevent the texture from occurring at the lower end, thereby improving display characteristics.

Claims (13)

Insulation board, A first signal line formed on the insulating substrate, A second signal line insulated from and intersecting the first signal line, A first thin film transistor connected to the first signal line and the second signal line, A first pixel electrode connected to the first thin film transistor, a second pixel electrode capacitively coupled to the first pixel electrode, and A coupling electrode connected to the first pixel electrode and overlapping the second pixel electrode in an insulated state Including; At least one of the first pixel electrode and the second pixel electrode has first domain dividing means for dividing and aligning liquid crystal molecules, and the coupling electrode and the first domain dividing means do not overlap, The coupling electrode is completely covered with the first pixel electrode or the second pixel electrode. In claim 1, And the first domain dividing means is a cutout. In claim 1, The coupling electrode extends from the drain electrode among the three terminals of the first thin film transistor. In claim 2, A gate insulating film formed between the first signal line and the second signal line, and a passivation film formed between the second signal line and the first and second pixel electrodes; The coupling electrode is connected to the first pixel electrode through a contact hole formed in the passivation layer. In claim 1, 2. The thin film transistor array panel of claim 1, wherein two long sides of adjacent boundary lines between the first pixel electrode and the second pixel electrode form a 45 ° angle with the first signal line. In claim 1, A third signal line insulated from and intersecting the second signal line and to which a reference potential is applied; A second thin film transistor having three terminals connected to the first signal line, the second pixel electrode, and the third signal line, respectively; Thin film transistor display panel further comprising. In claim 6, And the first thin film transistor and the second thin film transistor in the same pixel region are respectively connected to adjacent first signal lines. In claim 1, The direction of the electric field formed between the first pixel electrode and the second pixel electrode is directed toward the same direction as the alignment direction of the liquid crystal molecules oriented through the cut-off portion dividing the first and second pixel electrodes. The thin film transistor array panel on which the second pixel electrode is disposed. The thin film transistor array panel of claim 1, A common electrode panel including a common electrode facing the first and second pixel electrodes to form an electric field for driving liquid crystal molecules Liquid crystal display comprising a. The method of claim 9, And the common electrode has second domain dividing means for dividing the pixel region into a plurality of small domains together with the first domain dividing means. In claim 5, The first pixel electrode is positioned above and below the second pixel electrode and on the left or right side of the second pixel electrode to surround the second pixel electrode. The voltage applied to the first pixel electrode is higher than the voltage applied to the second pixel electrode. In claim 11, The coupling electrode is exposed between the boundary lines between the first pixel electrode and the second pixel electrode which are 45 ° with the first signal line. In claim 11, And a width of the coupling electrode positioned on an extension line of one end of the first domain dividing means is smaller than a width of the coupling electrode not located on the extension line.

Images