KR100983251B1 - Driver circuit, test device, and adjustment method - Google Patents

Abstract

A test apparatus for testing a device under test, comprising: a test signal generator for generating a test signal to be supplied to a device under test, a driver circuit for supplying a test signal to the device under test, and a device under test output according to the test signal And a judging section for judging whether the device under test is judged on the basis of the output signal, wherein the driver circuit differentiates the main driver, the sub-driver, and the drive signal output by the sub-driver, respectively, outputting the drive signal according to the test signal. A test apparatus including a differential circuit for outputting a signal and an adder for adding a differential signal to a drive signal output by the main driver and supplying a signal having a waveform corresponding to the test signal to a device under test.

Driver circuit, test device, adjustment method, main driver, sub driver, differential circuit

Description

Driver circuit, test device, and adjusting method

The present invention relates to a driver circuit, a test apparatus, and an adjustment method. In particular, the present invention relates to a driver circuit, a test apparatus, and an adjustment method for supplying an output signal of a waveform corresponding to an input signal to a circuit at a connection destination. This application is related to the following US application. Regarding a designated country where the incorporation by reference of documents is recognized, the contents described in the following application are incorporated into the present application by reference, and are made a part of the present application.

1. US Patent Application No. 11/262507, filed October 28, 2005

In test apparatuses, such as a semiconductor device, speeding up the driver circuit which supplies a test signal to a device under test is requested | required as the test speed increases. In addition, since the presence of a prior art document is not recognized at this time, description regarding a prior art document is abbreviate | omitted.

However, in the test apparatus, the test signal is attenuated or lost in the transmission line due to the long physical length of the transmission line from the driver circuit to the device under test. For this reason, in the test apparatus, it is difficult to cope with speeding up the test speed only by speeding up the driver circuit.

Therefore, an object of the present invention is to provide a driver circuit, a test apparatus, and an adjustment method capable of solving the above problems. This object is achieved by a combination of the features described in the independent claims of the claims. The dependent claims also define another advantageous embodiment of the invention.

In order to solve the said subject, according to the 1st aspect of this invention, the driver circuit which supplies the output signal of the waveform according to an input signal to the circuit of a connection destination WHEREIN: The main driver which outputs the drive signal according to an input signal, respectively; There is provided a driver circuit including a sub-driver, a differential circuit for outputting a differential signal obtained by differentiating a drive signal output by the sub-driver, and an adder for outputting an output signal obtained by adding a differential signal to a drive signal output by the main driver.

The driver circuit may further include a delay circuit for delaying the input signal input to the main driver to match the phase of the drive signal and the differential signal.

The sub driver may have a smaller power consumption than the main driver.

The adder may include a multiplier for correcting the amplitude of the differential signal by multiplying the differential signal by a predetermined correction value, and an adder for outputting an output signal obtained by adding a differential signal corrected by the multiplier to a drive signal output by the main driver.

The adder outputs an adder that adds a differential signal to the drive signal output by the main driver, and an output signal that has an output impedance substantially equal to the characteristic impedance of the transmission line transmitted to the circuit of the connection and amplifies the signal output by the adder. An amplifier may also be included.

According to the second aspect of the present invention, in a driver circuit for supplying an output signal of a waveform corresponding to an input signal to a circuit of a connection destination, the input signal is a logic value for each bit included in data to be supplied to a circuit of the connection destination. A main driver for converting each of the plurality of bit signals into a signal having a predetermined amplitude according to the bit position, and outputting a driving signal in which the plurality of bit signals after conversion are summed; A plurality of differential circuits provided corresponding to the signals and outputting differential signals obtained by differentiating the bit signal, and an addition of outputting an output signal obtained by adding a plurality of differential signals outputted by the plurality of differential circuits to a drive signal output by the main driver; It provides a driver circuit comprising a portion.

An adder is provided corresponding to each bit signal, and the multiplier corrects the amplitude of the differential signal by multiplying the differential signal by a predetermined correction value according to the bit position, and the multiplier corrects the drive signal output by the main driver. It may also include an adder for outputting an output signal obtained by adding the plurality of differentiated signals.

According to the third aspect of the present invention, in a driver circuit for supplying an output signal of a waveform corresponding to an input signal to a circuit of a connection destination, a main driver for outputting a drive signal according to the input signal, having a different time constant and an input signal A driver circuit including a plurality of differential circuits for outputting a plurality of differential signals each of which is differentiated, and an adder for outputting an output signal obtained by adding a plurality of differential signals outputted by the plurality of differential circuits to a drive signal output by the main driver; to provide.

The adder is provided corresponding to each differential circuit, and a plurality of multipliers for correcting the amplitude of the differential signal by multiplying the differential signal output from the differential circuit by a predetermined correction value according to the differential circuit, and a drive signal output by the main driver. And an adder for outputting an output signal obtained by adding a plurality of differential signals corrected by a plurality of multipliers.

According to a fourth aspect of the present invention, in a test apparatus for testing a device under test, a test signal generation unit for generating a test signal to be supplied to the device under test, a driver circuit for supplying the test signal to the device under test, and And a determination unit that determines whether the device under test is based on an output signal output by the device under test, wherein the driver circuit includes a main driver, a sub driver, and a sub driver each of which outputs a drive signal according to the test signal. A differential circuit for outputting a differential signal obtained by differentiating the drive signal to be output, and an adder for adding a differential signal to the drive signal output by the main driver and supplying a signal having a waveform according to the test signal to the device under test Provide a device.

According to a fifth aspect of the present invention, in a test apparatus for testing a device under test, a test signal generator for generating a test signal to be supplied to the device under test, a driver circuit for supplying the test signal to the device under test, and A determination unit that determines whether the device under test is based on an output signal output by the device under test, wherein the test signal indicates a logic value for each bit included in data to be supplied to the device under test. A main driver including a plurality of bit signals, wherein the driver circuit converts each of the plurality of bit signals into a signal having a predetermined amplitude according to the bit position, and outputs a driving signal in which the plurality of bit signals after conversion are summed; A plurality of signals provided corresponding to the signals and outputting differential signals obtained by differentiating the bit signals; There is provided a test apparatus including a differential circuit and an adder for outputting an output signal obtained by adding a plurality of differential signals outputted by a plurality of differential circuits to a drive signal output by the main driver.

According to a sixth aspect of the present invention, in a test apparatus for testing a device under test, a test signal generation unit for generating a test signal to be supplied to the device under test, a driver circuit for supplying the test signal to the device under test, and And a determination section for determining whether or not the device under test is based on an output signal output by the device under test, wherein the driver circuit has a main driver for outputting a drive signal according to the test signal, and has a different time constant A test apparatus including a plurality of differential circuits for outputting a plurality of differential signals each differentiating a signal, and an adder for outputting an output signal obtained by adding a plurality of differential signals outputted by a plurality of differential circuits to a drive signal output by the main driver. To provide.

The adder is provided corresponding to each differential circuit, and a plurality of multipliers for correcting the amplitude of the differential signal by multiplying the differential signal output from the differential circuit by a predetermined correction value according to the differential circuit, and a drive output by the main driver And an adder for outputting an output signal obtained by adding a plurality of differential signals corrected by a plurality of multipliers, wherein the test apparatus transmits the output signal to a circuit to which the connection is made when adjusting a plurality of correction values supplied to the plurality of multipliers. An acquisition unit for acquiring an output signal from an end connecting the circuit of the connection destination in the transmission line, a comparison unit for comparing the expected value of the output signal to be supplied to the circuit of the connection destination according to the output signal and the input signal acquired by the acquisition unit, and And an adjusting unit for adjusting the plurality of correction values based on the comparison result by the comparing unit. Selector for selecting each of a plurality of correction values from the correction value having a large time constant of the corresponding differential circuit as an adjustment target in order, and a longer time after the input signal is changed when the time constant of the differential circuit corresponding to the correction target is larger. The output to be supplied to the circuit of the connection destination in accordance with the input signal based on the result of the comparison by the timing setting unit and the comparison unit which causes the acquisition unit to acquire the output signal at this elapsed timing. An adjustment processing unit for adjusting the correction value to substantially match the expected value of the signal may be included.

According to the seventh aspect of the present invention, in a method of adjusting a driver circuit for supplying an output signal of a waveform corresponding to an input signal to a circuit to be connected, the driver circuit is different from a main driver for outputting a drive signal according to the input signal. A plurality of differential circuits for outputting a plurality of differential signals each having a time constant differentiating an input signal, and a plurality of differential signals output from a plurality of differential circuits to a drive signal output from the main driver in advance according to the differential circuit And an adder for outputting an output signal obtained by adding a signal multiplied by a predetermined correction value, wherein the adjusting method includes: an acquisition step of acquiring an output signal from an end connecting a circuit of a connection destination in a transmission line for transmitting the output signal to a circuit of a connection destination; And the output signal to be supplied to the circuit of the connection destination according to the output signal and the input signal acquired in the acquisition step. An input signal when the comparison step of comparing the expected values, a selection step of selecting each of the plurality of correction values as the adjustment target in order from the correction value having a large time constant of the corresponding differential circuit, and a time constant of the differential circuit corresponding to the correction target of the adjustment The value of the output signal at the timing is changed according to the input signal on the basis of the timing setting step for acquiring the output signal by the acquiring step at a timing after a longer time elapses after the change is made. And an adjustment processing step of adjusting the correction value to substantially match the expected value of the output signal to be supplied to the circuit of.

In addition, the summary of the present invention does not enumerate all of the features required by the present invention, and the sub-combination of these feature groups may also be invented.

1 shows a configuration of a test apparatus 10 according to the first embodiment.

2 shows the drive signal output from the main driver 22, the derivative signal output from the differential circuit 24, the output signal output from the adder 25, and the DUT 100 side end of the transmission line 200. FIG. Indicates the output signal to be detected.

3 shows an example of the configuration of the adder 25.

4 shows a configuration of a test apparatus 40 according to the second embodiment.

FIG. 5 shows the drive signal (a point), the input value of the differential circuit 53 (b point), and the input value (c point) of the differential circuit 54 with respect to the logic values of the DRE signal and the PAT signal.

6 shows a waveform obtained by multiplying the differential signal output from the differential circuit 53 by the correction value for the drive signal waveform (point a), and the waveform multiplied by the correction value by the differential signal output from the differential circuit 54. Dot) and the waveform (f point) of the output signal output from the adder 33. FIG.

7 shows a configuration of a test apparatus 70 according to the third embodiment.

8 shows a configuration of a test apparatus 80 according to a modification of the third embodiment.

9 shows a specific configuration of the adjusting unit 83.

10 shows a flow of the adjustment process by the test apparatus 80 according to the modification of the third embodiment.

DESCRIPTION OF EMBODIMENTS Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims, and not all combinations of the features described in the embodiments are essential to the solving means of the invention. .

1 shows a configuration of a test apparatus 10 according to the first embodiment. The test apparatus 10 according to the present embodiment supplies an output signal to the device under test 100 (hereinafter referred to as the DUT 100) through the transmission line 200, and the DUT in accordance with the supply of the output signal. The DUT 100 is tested by determining the signal output from the 100. In addition, the DUT 100 may be an electric circuit to which an output signal is supplied through the transmission line 200.

The test apparatus 10 includes a test signal generator 11, a driver circuit 12, a level comparator 13, and a determiner 14. The test signal generator 11 generates a test signal to be supplied to the DUT 100. The driver circuit 12 receives a test signal generated by the test signal generator 11 as an input signal and supplies an output signal of a waveform corresponding to the input signal to the DUT 100 through the transmission line 200. . Driver circuit 12 has sufficient drive capability to drive DUT 100. The level comparator 13 receives a signal output from the DUT 100 through the transmission line 200 in accordance with the supply of an output signal as a test signal, and determines the logic level of the signal. The determination unit 14 compares the logic level result determined by the level comparator 13 with the expected value generated by the test signal generator 11 to determine whether the DUT 100 is successful.

The driver circuit 12 includes a delay circuit 21, a main driver 22, a sub driver 23, a differential circuit 24, and an adder 25. The delay circuit 21 receives an input signal output from the test signal generator 11 and corresponds to match a phase of a drive signal output from the main driver 22 and the differential signal output from the differential circuit 24. Delay the input signal. Specifically, the delay circuit 21 delays the input signal by the delay time by the differential circuit 24.

The main driver 22 receives an input signal delayed by the delay circuit 21 and outputs a drive signal according to the input signal. Specifically, the main driver 22 outputs a drive signal having the same waveform as the input signal or a drive signal having a waveform specified by the input signal. The sub driver 23 receives an input signal output from the test signal generator 11 and outputs a driving signal corresponding to the input signal. The sub driver 23 is a circuit simulating the main driver 22, has a frequency characteristic equivalent to that of the main driver 22, and preferably has a smaller power consumption than the main driver 22.

The differential circuit 24 receives a drive signal output from the sub driver 23, and outputs a differential signal obtained by differentiating the drive signal. The adder 25 outputs an output signal obtained by adding the differential signal output from the differential circuit 24 to the drive signal output from the main driver 22. The output signal output from the adder 25 is supplied to the DUT 100 through the transmission line 200.

2 shows the drive signal output from the main driver 22, the differential signal output from the differential circuit 24, the output signal output from the adder 25, and the end of the DUT 100 of the transmission line 200. Indicates the output signal to be detected. The drive signal (FIG. 2 (A)) output from the main driver 22 is supplied to the adder 25. FIG. The differential signal (Fig. 2 (B)) is supplied to the adder 25 as a signal obtained by extracting an edge component from the drive signal. The output signal (Fig. 2 (C)) is a waveform obtained by adding a drive signal and a differential signal, that is, a waveform emphasizing the edge portion of the drive signal.

Here, since the transmission line 200 usually has an integration characteristic, the output signal is supplied to the DUT 100 by the high frequency component being lost by the transmission line 200 as indicated by the dotted line in FIG. 2 (D). In contrast, the driver circuit 12 supplies an output signal emphasizing the edge portion of the drive signal, and compensates for the loss in the transmission line 200. Therefore, the driver circuit 12 can apply an output signal having the same waveform as the drive signal to the DUT 100 from the end of the transmission line 200 (solid line in Fig. 2D).

As described above, the driver circuit 12 emphasizes the drive signal by the differential circuit 24 in advance to compensate for the deterioration of the high frequency component by the transmission line 200. Thereby, the driver circuit 12 can reproduce the signal waveform of the output terminal of the main driver 22 in the circuit terminal of a connection destination, and can supply an appropriate signal to the circuit of the connection destination. Therefore, according to the test apparatus 10 which concerns on this embodiment, the DUT 100 can be tested suitably. In addition, since the driver circuit 12 emphasizes the drive signal by the differential signal, it is possible to compensate for the loss caused by the time constant longer than the period of the test signal.

3 shows an example of the configuration of the adder 25. The adder 25 may include a multiplier 31, a correction value register 32, an adder 33, and an amplifier 34. The multiplier 31 corrects the amplitude of the differential signal by multiplying the differential signal output from the differential circuit 24 by a predetermined correction value. The test apparatus 10 according to the present embodiment can add the appropriate differential signal according to the characteristics of the transmission line 200 to the drive signal by correcting the amplitude of the differential signal by the multiplier 31. The correction value register 32 stores the correction value multiplied by the multiplier 31. The adder 33 outputs an output signal obtained by adding a differential signal whose amplitude is corrected by the correction value register 32 to the drive signal output from the main driver 22. The amplifier 34 outputs an output signal obtained by amplifying the signal output by the adder 33. The amplifier 34 has an output impedance substantially equal to the characteristic impedance of the transmission line 200 transmitting to the DUT 100. For this reason, the adder 25 and the transmission line 200 can supply the output signal to the DUT 100 in the state where impedance matching is performed and the transmission loss is the least.

4 shows a configuration of a test apparatus 40 according to the second embodiment. The test apparatus 40 according to the present embodiment supplies the multilevel output signal to the DUT 100 via the transmission line 200. And the test apparatus 40 tests the said DUT 100 by determining the signal output from the DUT 100 according to supply of the said output signal. Since the member of the test apparatus 40 which has the same code | symbol as the member of the test apparatus 10 which concerns on 1st Embodiment has substantially the same function and structure as the member of the test apparatus 10 which concerns on 1st Embodiment, The description is omitted below except for differences.

The test apparatus 40 includes a test signal generator 41, a second driver circuit 42, a level comparator 13, and a determiner 14. The test signal generator 41 generates a test signal to be supplied to the DUT 100. The test signal generated by the test signal generator 41 includes a plurality of bit signals each representing a logic value for each bit included in data to be supplied to the DUT 100. The test signal generator 41 generates test signals (DRE signals, PAT signals) that specify three values of VL (minimum level), VH (intermediate level), and VT (maximum level) as an example. More specifically, VT is specified when the DRE signal is L logic, VL is designated when the DRE signal is H logic and L logic, and VH is specified when the DRE signal is H logic and the PAT signal is H logic. Generate the test signal you specify.

The second driver circuit 42 receives a test signal generated by the test signal generator 41 as an input signal, and outputs an output signal of a waveform designated by the input signal through the transmission line 200 through the DUT ( 100). The second driver circuit 42 has sufficient drive capability to drive the DUT 100. The second driver circuit 42 includes a main driver 51, a logic circuit 52, a plurality of differential circuits 53 and 54, and an adder 55.

The main driver 51 receives a test signal from the test signal generator 41, converts each of the plurality of bit signals into a signal having a predetermined amplitude according to the bit position, and drives the sum of the plurality of bit signals after the conversion. Output the signal. As an example, the main driver 51 converts into driving signals of three value levels VL, VH, and VT determined according to the logic values of the bit signals included in the DRE signal and the PAT signal.

The differential circuit 53 and the differential circuit 54 are provided corresponding to a plurality of bit signals, respectively, and output differential signals obtained by differentiating the bit signals. The differential circuit 53 outputs a differential signal obtained by differentiating a bit signal representing a logic value of the first bit position by differentiating the signal output from the logic circuit 52 which detects whether or not the drive signal is VL. In addition, the differential circuit 54 outputs a differential signal obtained by differentiating the bit signal representing the logic value of the second bit position by differentiating the DRE signal generated by the test signal generation section 41 as an example.

The adder 55 outputs an output signal obtained by adding the differential signal output from each of the differential circuits 53 and 54 to the drive signal output from the main driver 51. The adder 55 includes multipliers 61 and 62 provided in correspondence with the respective differential circuits 53 and 54, correction value registers 63 and 64 and adders 33 provided in correspondence with the multipliers 61 and 62 respectively. And an amplifier 34 may be included. The multipliers 61 and 62 correct the amplitude of the differential signal by multiplying the differential signal output from the corresponding differential circuits 53 and 54 by a predetermined correction value according to the bit position. The correction value registers 63 and 64 store correction values to be multiplied by the corresponding multipliers 61 and 62. The adder 33 outputs an output signal obtained by adding a plurality of differential signals corrected by the plurality of multipliers 61 and 62 to a drive signal output from the main driver 51. In the test apparatus 40, a delay circuit may be provided at the front end of the main driver 51 or at the front end of the plurality of differential circuits 53, 54 to adjust the phase of the adder 33.

5 shows a drive signal (a point) output from the main driver 51, an input value (b point) of the differential circuit 53, and an input value (c) of the differential circuit 54 with respect to the DRE signal and the PAT signal. Dot). In this example, the drive signal output from the main driver 51 becomes VT when the DRE signal is L logic, VL when the DRE signal is H logic, and VL when the PAT signal is L logic, and the DRE signal is H logic and PAT. When the signal is H logic, it becomes VH. The differential circuit 53 receives L logic when the DRE signal is H logic and PAT signal is L logic, and H logic is input regardless of the PAT signal when the DRE signal is L logic and rising and falling (b point). . In the differential circuit 54, L logic is input when the drive signal is VT, and H logic is input when the drive signals are VL and VH (point c).

6 shows, as an example, a waveform obtained by multiplying a differential signal output from the differential circuit 53 by a correction value with respect to the drive signal waveform (a point) output from the main driver 51, and outputting from the differential circuit 54. The waveform (e point) obtained by multiplying the differential signal by the correction value and the waveform (f point) of the output signal output from the adder 33 are shown. The differential signal output from the differential circuit 53 changes its level when the drive signal is changed from VH or when it is changed to VH (d point). Further, the differential signal output from the differential circuit 53 changes its level when the drive signal is changed from VT or when it is changed to VT (point e). Moreover, the amplitude of the differential signal corresponds to the drive signal by having the amplitude value in the correction value registers 63 and 64. Therefore, the output signal is a waveform in which the edge portion of the drive signal is emphasized in amplitude according to the level change amount (point f). As described above, since the second driver circuit 42 emphasizes the edge component of the drive signal, it is possible to reproduce the signal waveform of the output terminal of the main driver 51 at the circuit terminal of the connection destination and supply the appropriate signal to the circuit of the connection destination. Can be.

7 shows a configuration of a test apparatus 70 according to the third embodiment. The test apparatus 70 according to the present embodiment supplies the output signal to the DUT 100 via the transmission line 200, and determines the signal output from the DUT 100 in accordance with the supply of the output signal, thereby determining the DUT ( Test 100). The test apparatus 70 can test by supplying an appropriate signal to the circuit terminal of a connection destination. Since the member of the test apparatus 70 which has the same code | symbol as the member of the test apparatus 10 which concerns on 1st Embodiment has substantially the same function and structure as the member of the test apparatus 10 which concerns on 1st Embodiment, The description is omitted below except for differences.

The test apparatus 70 according to the present embodiment includes a test signal generation unit 11, a level comparator 13, a determination unit 14, and a third driver circuit 71. The third driver circuit 71 receives a test signal generated by the test signal generator 11 as an input signal, and outputs an output signal of a waveform corresponding to the input signal to the DUT 100 through the transmission line 200. Supply. The third driver circuit 71 has a drive capability sufficient to drive the DUT 100.

The third driver circuit 71 includes a main driver 22, a plurality of differential circuits 72 (72-1, 72-2, ..., 72-n (n is an integer of 2 or more)), and an adder 73 ). The main driver 22 receives an input signal output from the test signal generator 11 and outputs a drive signal having a waveform corresponding to the input signal. The plurality of differential circuits 72 receive an input signal output from the test signal generator 11 and output a plurality of differential signals obtained by differentiating the input signals, respectively. The plurality of differential circuits 72 have different time constants. The adder 73 outputs an output signal obtained by adding a differential signal to a drive signal output from the main driver 22.

The adder 73 includes a plurality of multipliers 74 (74-1, 74-2, ..., 74-n) provided in correspondence with the respective differential circuits 72, and correction values provided in correspondence with the multipliers 74, respectively. Register 75 (75-1, 75-2, ..., 75-n), adder 33, and amplifier 34. The plurality of multipliers 74 respectively correct the amplitude of the differential signal by multiplying the differential signal output from the corresponding differential circuit 72 by a predetermined correction value. The plurality of correction value registers 75 store correction values to be supplied to the corresponding multipliers 74, respectively. The adder 33 adds the differential signal whose amplitude is corrected by each multiplier 74 to the drive signal output from the main driver 22, and outputs an output signal.

Since the test apparatus 70 adds a plurality of differential signals generated by a plurality of differential circuits 72 having different time constants to the drive signal, the drive signal can be adjusted by appropriate distribution along the transmission line 200. In the test apparatus 70, a delay circuit may be provided at the front end of the main driver 22 or at the front end of the plurality of differential circuits 72 to adjust the phase of the signal input to the adder 33.

8 shows a configuration of a test apparatus 80 according to a modification of the third embodiment. The test apparatus 80 according to the present modification includes an acquisition unit 81, a comparison unit 82, and an adjustment unit 83 in addition to each circuit included in the test apparatus 70 illustrated in FIG. 7. It has an adjustment function for adjusting the correction value supplied to the multiplier 74. The acquisition unit 81 is connected to the DUT 100 when adjusting the correction value, and acquires an output signal from an end connecting the DUT 100 in the transmission line 200. The comparison unit 82 compares the expected value of the output signal to be supplied to the DUT 100 in accordance with the output signal acquired by the acquisition unit 81 and the input signal. The adjusting unit 83 adjusts the plurality of correction values stored in the plurality of correction value registers 75 based on the comparison result by the comparing unit 82.

9 shows a specific configuration of the adjusting unit 83. The adjusting unit 83 includes a selecting unit 86, a timing setting unit 87, and an adjusting processing unit 88. The selection unit 86 sequentially selects each of the plurality of correction values from the correction values having the large time constant of the corresponding differential circuit 72 as the adjustment target. When the time constant of the differential circuit 72 corresponding to the correction value to be adjusted is larger, the timing setting unit 87 changes the input signal and acquires the output signal at a timing after a longer time elapses. To acquire. The adjustment processor 88 adjusts the correction value such that the value of the output signal at the timing substantially matches the expected value of the output signal to be supplied to the DUT 100 according to the input signal based on the comparison result by the comparator 82. do.

10 shows a flow of the adjustment process in the test apparatus 80 according to the present modification. When the adjustment process is started, first, the selection unit 86 first selects a correction value corresponding to the differential circuit 72 having the largest time constant as the adjustment target (step S11). Specifically, the selection unit 86 selects, as an adjustment target, one correction value register 75 in which a correction value corresponding to the differential circuit 72 having the largest time constant among the plurality of correction value registers 75 is stored. Subsequently, the timing setting unit 87 sets the measurement time from the timing at which the amplitude of the input signal is changed to the timing at which the acquisition unit 81 acquires the output signal (step S12).

Subsequently, the test apparatus 80 according to the present modification performs measurement processing (step S13). Specifically, the processing of steps S21 to S24 is performed as the measurement processing. The test apparatus 80 changes the value of the input signal by the test signal generator 11 and supplies an output signal corresponding to the input signal to the DUT 100 (step S21). Subsequently, the timing setting unit 87 gives an acquisition instruction to the acquisition unit 81 for a predetermined measurement time from the timing at which the value of the input signal is changed (step S22). Subsequently, upon receiving an acquisition instruction, the acquisition unit 81 acquires an output signal from the end of the DUT 100 (step S23). Subsequently, the comparison unit 82 compares the value of the output signal acquired by the acquisition unit 81 with the expected value of the output signal at the same timing (step S24).

Subsequently, when the measurement processing in step S13 is finished, the adjustment processing unit 88 adjusts the correction value selected such that the expected value substantially matches the value of the output signal acquired by the acquisition unit 81 based on the comparison result obtained in step S13 ( Step S14). Specifically, the adjustment processing unit 88 changes the correction value in the correction value register 75 selected by the selection unit 86. Subsequently, the selection unit 86 selects the correction value corresponding to the differential circuit 72 with the next largest time constant as the adjustment target (step S15). Then, the timing setting part 87 sets the measurement time from the timing which changed the amplitude of an input signal to the timing which the acquisition part 81 acquires an output signal (step S16). At this time, the timing setting unit 87 sets the measurement time so that the time constant adjusted earlier becomes shorter than the large correction value.

Subsequently, the test apparatus 80 according to this modification performs the same measurement processing as in step S13 (step S17). Subsequently, the adjustment processing unit 88 adjusts the selected correction value such that the expected value substantially matches the value of the output signal acquired by the acquisition unit 81 based on the comparison result obtained in the process of step S17 (step S18). Subsequently, the test apparatus 80 according to the present modification determines whether or not the adjustment with respect to the correction value having the smallest time constant is completed (step S19). As a result of the determination, if the adjustment is incomplete, the process is repeated from step S15, and if the adjustment is completed, the adjustment process ends.

As described above, the test apparatus 80 according to the present modification adjusts the correction amount for the differential circuit 72 having a long time constant first (steps S11 and S15), and when the time constant is larger, the measurement time is made longer. The correction value is adjusted (step S22). For this reason, since the test apparatus 80 adjusts first from the correction amount which affects a wider band, it can perform an adjustment process efficiently.

As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvement can be added to the said embodiment. It is clear from description of a claim that the form which added such a change or improvement can also be included in the technical scope of this invention.

As is clear from the above description, according to the present invention, a driver circuit, a test apparatus, and an adjustment method for supplying an appropriate signal to a circuit terminal of a connection destination can be realized.

Claims (14)

In a driver circuit for supplying an output signal of a waveform corresponding to an input signal to a circuit of a connection destination, A main driver and a sub driver respectively outputting a driving signal according to the input signal; A differential circuit for outputting a differential signal obtained by differentiating the drive signal output by the sub driver; And An adder configured to output an output signal obtained by adding the differential signal to the drive signal output by the main driver; Including, The addition unit, A multiplier that corrects the amplitude of the differential signal by multiplying the differential signal by a predetermined correction value; And An adder for outputting an output signal obtained by adding the differential signal corrected by the multiplier to the drive signal output by the main driver; Driver circuit comprising a. The method of claim 1, And a delay circuit for delaying the input signal input to the main driver to match the phase of the drive signal and the differential signal. The method of claim 1, And the sub driver has a lower power consumption than the main driver. In a driver circuit for supplying an output signal of a waveform corresponding to an input signal to a circuit of a connection destination, A main driver and a sub driver respectively outputting a driving signal according to the input signal; A differential circuit for outputting a differential signal obtained by differentiating the drive signal output by the sub driver; And An adder configured to output an output signal obtained by adding the differential signal to the drive signal output by the main driver; Including, The addition unit, An adder for adding the differential signal to the drive signal output from the main driver; And An amplifier having an output impedance substantially equal to the characteristic impedance of the transmission line transmitted to the circuit of the connection destination, and an amplifier for amplifying a signal output by the adder and outputting an output signal. Driver circuit comprising a. The method of claim 4, wherein And a delay circuit for delaying the input signal input to the main driver to match the phase of the drive signal and the differential signal. The method of claim 4, wherein And the sub driver has a lower power consumption than the main driver. In a driver circuit for supplying an output signal of a waveform corresponding to an input signal to a circuit of a connection destination, The input signal includes a plurality of bit signals each representing a logic value for each bit included in data to be supplied to a circuit of the connection destination; A main driver for converting each of the plurality of bit signals into a signal having a predetermined amplitude according to a bit position, and outputting a driving signal in which the plurality of bit signals after conversion are summed; A plurality of differential circuits provided corresponding to each of the plurality of bit signals and outputting a differential signal obtained by differentiating the bit signals; And An adder for outputting an output signal obtained by adding the plurality of differential signals outputted by the plurality of differential circuits to the drive signal output by the main driver; Including, The addition unit, A plurality of multipliers provided corresponding to each of the plurality of bit signals and correcting the amplitude of the differential signal by multiplying the differential signal by a predetermined correction value according to a bit position; And An adder for outputting an output signal obtained by adding the plurality of differential signals corrected by the plurality of multipliers to the drive signal output by the main driver; Driver circuit comprising a. delete In a driver circuit for supplying an output signal of a waveform corresponding to an input signal to a circuit of a connection destination, A main driver for outputting a driving signal according to the input signal; A plurality of differential circuits having different time constants and outputting a plurality of differential signals each differentiating the input signal; And An adder for outputting an output signal obtained by adding the plurality of differential signals outputted by the plurality of differential circuits to the drive signal output by the main driver; Including, The addition unit, A plurality of multipliers provided corresponding to each of said plurality of differential circuits and correcting an amplitude of said differential signal by multiplying said differential signal output by said differential circuit by a predetermined correction value according to said differential circuit; And An adder for outputting an output signal obtained by adding the plurality of differential signals corrected by the plurality of multipliers to the drive signal output by the main driver; Driver circuit comprising a. In a test apparatus for testing a device under test, A test signal generator which generates a test signal to be supplied to the device under test; A driver circuit for supplying the test signal to the device under test; And Determination unit for determining whether or not the device under test based on the first output signal output from the device under test according to the test signal Including; The driver circuit, A main driver and a sub driver respectively outputting a driving signal according to the test signal; A differential circuit for outputting a differential signal obtained by differentiating the drive signal output by the sub driver; And An adder which adds the differential signal to the drive signal output by the main driver and supplies a signal having a waveform according to the test signal to the device under test; Including, The addition unit, A multiplier that corrects the amplitude of the differential signal by multiplying the differential signal by a predetermined correction value; And An adder for outputting a second output signal obtained by adding the differential signal corrected by the multiplier to the drive signal output by the main driver; Test device comprising a. In a test apparatus for testing a device under test, A test signal generator which generates a test signal to be supplied to the device under test; A driver circuit for supplying the test signal to the device under test; And Determination unit for determining whether or not the device under test based on the first output signal output from the device under test according to the test signal Including; The test signal includes a plurality of bit signals each representing a logic value for each bit included in data to be supplied to the device under test, The driver circuit, A main driver for converting each of the plurality of bit signals into a signal having a predetermined amplitude according to a bit position, and outputting a driving signal in which the plurality of bit signals after conversion are summed; A plurality of differential circuits provided corresponding to the respective bit signals and outputting differential signals obtained by differentiating the bit signals; And An adder for outputting a second output signal obtained by adding the plurality of differential signals output by the plurality of differential circuits to the drive signal output by the main driver; Including, The addition unit, A plurality of multipliers provided corresponding to each of the plurality of bit signals and correcting the amplitude of the differential signal by multiplying the differential signal by a predetermined correction value according to a bit position; And An adder for outputting the second output signal obtained by adding the plurality of differential signals corrected by the plurality of multipliers to the drive signal output by the main driver; Test device comprising a. In a test apparatus for testing a device under test, A test signal generator which generates a test signal to be supplied to the device under test; A driver circuit for supplying the test signal to the device under test; And Determination unit for determining whether or not the device under test based on the first output signal output from the device under test according to the test signal Including; The driver circuit, A main driver for outputting a driving signal according to the test signal; A plurality of differential circuits having different time constants and outputting a plurality of differential signals each differentiating the test signal; And An adder for outputting a second output signal obtained by adding the plurality of differential signals output by the plurality of differential circuits to the drive signal output by the main driver; Including, The addition unit, A plurality of multipliers provided corresponding to each of said plurality of differential circuits and correcting an amplitude of said differential signal by multiplying said differential signal output by said differential circuit by a predetermined correction value according to said differential circuit; And An adder for outputting the second output signal obtained by adding the plurality of differential signals corrected by the plurality of multipliers to the drive signal output by the main driver; Test device comprising a. The method of claim 12, The test device, When adjusting the plurality of correction values supplied to the plurality of multipliers, the second output from an end connecting the circuit of the device under test at a transmission line that transmits the second output signal to a circuit of the device under test. An acquisition unit for acquiring a signal; A comparison unit for comparing an expected value of the second output signal to be supplied to the circuit of the device under test according to the second signal and the test signal acquired by the acquisition unit; And An adjusting unit for adjusting the plurality of correction values based on a comparison result by the comparing unit More, The adjusting unit, A selection unit that selects each of the plurality of correction values in turn from the correction values having a large time constant of the corresponding differential circuit as an adjustment target; A timing setting unit for acquiring the second output signal by the acquiring unit at a timing after a longer time after changing the test signal when the time constant of the differential circuit corresponding to the correction value to be adjusted is greater; ; And The value of the second output signal at the timing based on a comparison result by the comparing unit so that the value of the second output signal to be supplied to the circuit of the device under test according to the test signal substantially matches the expected value. Adjustment processing unit for adjusting the correction value Test device comprising a. In the adjustment method of the driver circuit which supplies the output signal of the waveform according to an input signal to the circuit of a connection destination, The driver circuit, A main driver for outputting a driving signal according to the input signal; A plurality of differential circuits having different time constants and outputting a plurality of differential signals each differentiating the input signal; And An adder for outputting an output signal obtained by adding a signal obtained by multiplying a plurality of differential signals output from the plurality of differential circuits by a signal obtained by multiplying a predetermined correction value according to the differential circuit; Including; The adjustment method, An acquisition step of acquiring the output signal from an end connecting the circuit at the connection destination in a transmission line for transmitting the output signal to the circuit at the connection destination; A comparison step of comparing the expected value of the output signal to be supplied to the circuit of the connection destination according to the input signal and the output signal acquired in the acquiring step; A selection step of selecting each of the plurality of correction values from the correction value having a large time constant of the corresponding differential circuit as an adjustment target in order; A timing setting step of acquiring the output signal by the acquiring step at a timing after a longer time after changing the input signal when the time constant of the differential circuit corresponding to the correction value to be adjusted is greater; And Adjustment to adjust the correction value such that the value of the output signal at the timing is substantially equal to the expected value of the output signal to be supplied to the circuit of the connection destination according to the input signal based on the comparison result by the comparing step. Processing steps Adjustment method comprising a.

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