JP2007235797A - Equalizer characteristic setting circuit and equalizer characteristic setting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a characteristics setting circuit for an equalizer capable of setting the equalizer circuit used for forming signal waveforms so that overall characteristics of a transmission frequency characteristics and an equalizer frequency characteristics become even at each frequency, and the equalizer characteristics setting means. <P>SOLUTION: The equalizer characteristics setting circuit for setting the equalizer characteristics of the equalizer circuit correcting and outputting waveform distortion of a signal received via a transmission path is provided with a signal generation means 4 for repeatedly outputting waveform signals at multiple different frequencies in a frequency band required for signal transmission, an equalizer circuit K1 for receiving a signal from the signal generation means 4 via the transmission path; and an equalizer characteristics regulation means 5 for selecting the equalizer characteristics compensating a frequency characteristics of the transmission path based on output waveforms of the equalizer circuit, and for setting the equalizer characteristics to the equalizer circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an equalizer characteristic setting circuit and an equalizer characteristic setting method, and more particularly to an equalizer circuit used for signal waveform shaping in high-speed signal transmission so that the overall characteristics of the transmission frequency characteristic and the equalizer frequency characteristic are uniform at each frequency. The present invention relates to an equalizer characteristic setting circuit and an equalizer characteristic setting method.

  Conventionally, in high-speed signal transmission of an electronic device or the like, when the waveform attenuation by the transmission path is large, an equalizer circuit is inserted on the receiving side to shape the waveform. In this case, the equalizer circuit has a frequency characteristic that cancels transmission distortion received in the transmission line.

  As this type of prior art, for example, there is an attenuation equalizer proposed in Japanese Patent Laid-Open No. 1-245626, an equalizer circuit proposed in Japanese Patent Laid-Open No. 2004-172660, and the like.

  In the technique proposed in Japanese Patent Laid-Open No. 1-245626, in order to equalize the attenuation distortion generated in a telephone line or the like, the attenuation distortion generated in the transmission path of the signal received through the transmission path is changed to the signal frequency and the signal. It is estimated from the level, and an attenuation equalization characteristic that optimally equalizes the estimated attenuation distortion is selected and set in an attenuation equalizer (equalizer circuit).

Further, the technique proposed in Japanese Patent Application Laid-Open No. 2004-172660 adjusts the gain of a filter based on the reception level of the received signal so that the filter has a frequency characteristic opposite to the attenuation characteristic in the transmission path, The signal level with respect to the frequency of the signal received via the transmission line is made substantially constant.
JP-A-1-245626 JP 2004-172660 A

  In the above prior art, when setting the characteristic of the equalizer circuit, the specific signal frequency of the transmitted signal is detected, and the attenuation characteristic for all frequencies is estimated from the attenuation characteristic of the signal level for this frequency. The characteristic of the equalizer circuit is set so that the characteristic is compensated. This prior art attenuation characteristic for frequencies other than the received signal frequency is only an estimate, and therefore, in the entire frequency band required for signal transmission, there is a conflicting frequency characteristic that compensates for the attenuation characteristic in the transmission path. Is not always possible. Since the frequency characteristics of the transmission line are different from each other, it is difficult to obtain the attenuation characteristic from only a specific signal frequency and obtain the frequency characteristic for all frequencies of the transmission line from this, and therefore the frequency required for signal transmission. It is difficult to satisfy the characteristics in all the bands.

  In view of the problems of the prior art, the present invention relates to an equalizer characteristic setting circuit that can set an equalizer circuit used for signal waveform shaping so that the overall characteristics of the transmission frequency characteristic and the equalizer frequency characteristic are uniform at each frequency, and It is to provide an equalizer characteristic setting method.

The gist of the invention according to claim 1 of the present invention is that an equalizer characteristic setting circuit for setting an equalizer characteristic of an equalizer circuit that corrects and outputs a waveform distortion of a signal received via a transmission line is necessary for signal transmission. Based on a signal generating means for outputting a signal having a repetitive waveform at a plurality of different frequencies within a frequency band, an equalizer circuit for receiving a signal from the signal generating means via the transmission line, and an output waveform of the equalizer circuit The equalizer characteristic setting circuit includes an equalizer characteristic adjusting unit that selects an equalizer characteristic that compensates for the frequency characteristic of the transmission line and sets the equalizer characteristic in the equalizer circuit.
The gist of the invention according to claim 2 of the present invention is that the equalizer characteristic adjusting means detects an equalizer characteristic storage means for storing a plurality of equalizer characteristics and an amplitude of an output waveform of the equalizer circuit at the plurality of frequencies. Based on the amplitude detected by the amplitude detecting means and the amplitude detecting means, one equalizer characteristic capable of compensating the frequency characteristic of the transmission line within an allowable range at the plurality of frequencies is stored in the equalizer characteristic storing means. The equalizer characteristic setting circuit according to claim 1, further comprising a determination / adjustment circuit configured to select the plurality of equalizer characteristics and set the equalizer circuit in the equalizer circuit.
The gist of the invention according to claim 3 of the present invention is that the determination / adjustment circuit is configured such that the signal amplitude output from the equalizer circuit is predetermined with respect to a target frequency characteristic in all received frequency signals. 3. The equalizer characteristic setting circuit according to claim 2, wherein an equalizer characteristic that can be compensated so as to fall within an allowable range is selected.
The invention according to claim 4 of the present invention is characterized in that the amplitude detecting means comprises a plurality of comparing means for comparing the output waveform of the equalizer circuit with different predetermined reference voltage values. It exists in the equalizer characteristic setting circuit of Claim 2 or Claim 3.
The gist of the invention according to claim 5 of the present invention is that the signal generating means sequentially outputs signals of different frequencies, and the equalizer characteristic adjusting means first selects the equalizer characteristic to be selected in the signal of the frequency received next. The equalizer characteristic setting circuit according to any one of claims 1 to 4, wherein the equalizer characteristic setting circuit is further selected from the equalizer characteristics selected.
According to a sixth aspect of the present invention, there is provided an equalizer characteristic setting method for an equalizer circuit that corrects and outputs a waveform distortion of a signal, and a plurality of signal waveforms having different frequencies are transmitted by an equalizer circuit via a transmission line. Based on the waveform received and output from the equalizer circuit, an equalizer characteristic that compensates the frequency characteristic of the transmission line at all of the plurality of different frequencies is selected from a plurality of equalizer characteristics prepared in advance, and the equalizer circuit is selected. There exists an equalizer characteristic setting method characterized by setting.
The gist of the invention according to claim 7 of the present invention is that the plurality of equalizer characteristics prepared in advance are stored in a storage unit in advance, and the stored equalizer characteristics are based on a waveform output from the equalizer circuit. 7. The equalizer characteristic setting circuit according to claim 6, wherein the equalizer characteristic setting circuit is selected from the above and set in the equalizer circuit.
The gist of the invention according to claim 8 of the present invention is to select an equalizer characteristic capable of compensating so that the signal amplitude output from the equalizer circuit falls within a predetermined allowable range in all received frequency signals. It exists in the equalizer characteristic setting circuit of Claim 6 or Claim 7 characterized by the above-mentioned.
According to a ninth aspect of the present invention, the output waveform of the equalizer circuit is compared with different predetermined reference voltage values to determine the signal amplitude output from the equalizer circuit. It exists in the equalizer characteristic setting circuit of Claim 8.
The gist of the invention according to claim 10 of the present invention is that the equalizer circuit sequentially receives signals of different frequencies, and selects the equalizer characteristic to be selected in the signal of the next received frequency from among the equalizer characteristics previously selected. The equalizer characteristic setting circuit according to any one of claims 6 to 10, wherein the equalizer characteristic setting circuit is further selected.

  According to the present invention, there are provided an equalizer characteristic setting circuit and an equalizer characteristic setting method capable of setting an equalizer circuit used for signal waveform shaping so that a total characteristic of a transmission frequency characteristic and an equalizer frequency characteristic is uniform at each frequency. can do.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[First embodiment]

  FIG. 1 is an example of an equalizer characteristic setting circuit according to an embodiment of the present invention.

  In FIG. 1, reference numeral 1 denotes an equalizer characteristic setting circuit. Reference numeral 2 denotes a transmission circuit unit, and 3 denotes a reception circuit unit.

4 is a pulse generator, 1 times the fundamental frequency _{f 1,} 1/2-fold, 1/4-fold, a plurality of flip-flops _F 1 to generate a repetitive signal _···, F 2 ,, ··· F comprising a signal generating circuit constituted by _n, a selection circuit SL for selecting and outputting one of the outputs of the signal generating circuit.

F ₁ is a flip-flop that generates the fundamental frequency f ₁ , the inverting output terminal is connected to the data input terminal, the clock signal that determines the fundamental frequency f ₁ is input to the clock terminal, and the output terminal is the input of the selection circuit SL. It is connected to the.

F ₂ is a flip-flop that divides the output frequency of the flip-flop F ₁ by ½, the inverting output terminal is connected to the data input terminal, the output terminal of the flip-flop F ₁ is connected to the clock terminal, and the output terminal Is connected to the input of the selection circuit SL.

F _n is a flip-flop that divides the output frequency of the flip-flop F _n-1 by ½, the inverting output terminal is connected to the data input terminal, and the output terminal of the flip-flop F _n-1 is connected to the clock terminal. The output terminal is connected to the input of the selection circuit SL.

Thus connected flip-flops _{F 1,} F 2, ... _{F n} is 1 times the fundamental frequency _{f 1,} respectively, 1/2-fold, 1/4-fold, the signal for generating a repetitive signal ... A generation circuit is configured.

The selection circuit SL selects and outputs one output of the flip-flops F ₁ , F ₂ ,... F _n when a selection signal is input. The selection signal of the selection circuit SL is switched in accordance with the progress of the processing of the EQ characteristic adjustment unit 5 as will be described later.

5 determines the characteristics of the transmission path L by receiving a signal from the pulse generator 4, an EQ (equalizer) characteristic adjustment unit for setting the characteristics of EQ (equalizer) circuit K _1.

The transmission circuit unit 2 and the reception circuit unit 3 are connected between the transmission end TM ₁ and the reception end TM ₂ by a transmission line L.

The EQ characteristic adjusting unit 5 includes comparators D ₁ , D ₂ ,... _DN , a determination / adjustment circuit K _2, and the like.

The EQ circuit K ₁ receives a signal from the transmission line L via the receiving end TM ₂ and outputs a signal corrected by the equalizer characteristic to the buffer circuit BF. The buffer circuit BF outputs a signal to a circuit unit (not shown) connected to the output side.

The output of the EQ circuit _{K 1} includes comparator _{D 1,} D 2, is outputted to · · · _{D N.}

Comparator _{D 1,} D 2, each of the · · · _{D N,} the reference voltage for each comparison, i.e. the reference voltage Vref ₁ to comparator _{D 1} is, the reference voltage Vref ₂ to the comparator _{D 2} is input Vref _N in ... comparator _{D N.} And these reference voltages is compared with the output voltage of the EQ circuit K _1.

Outputs of the comparators D ₁ , D ₂ ,... _DN are input to the determination / adjustment circuit K ₂ . Judgment / regulation circuit _{K 2} comparators _{D 1, D 2,} the output state of · · · _{D N,} to determine the output amplitude of the EQ circuit _{K 1,} acceptable properties as properties of the EQ circuit _{K 1,} prestored Select from a number of characteristics. This selection process is done by sweeping through the frequency band required for signal transmission at a frequency from the pulse generator 4, the EQ circuits K ₁ by selecting one of the finally remaining characteristics as acceptable properties It is supposed to be set. With respect to characteristic setting processing of the EQ circuit K ₁ will be described later with reference to FIG.

The levels of the reference voltages Vref ₁ , Vref ₂ ... Vref _N are illustrated in FIG. In Figure 2, the output of the EQ circuit _{K 1} is, take the three kinds of signals having different amplitude values as an example, the waveform (a), waveform (b), is drawn as a waveform (c). The signal from the pulse generator 4 is a rectangular pulse in the case of a signal such as digital data, but waveform distortion occurs due to the transmission characteristics of the transmission line L, so that the waveform (a), waveform (b), waveform (c) Is drawn as a pseudo sine wave.

Comparator _{D 1,} D 2 by 2, the operation of the · · · _{D N.}

For example, the signal from the EQ circuit _{K 1} waveform (a) is output. In this case, the reference voltage Vref ₁ is compared with comparator D ₁ In the waveform (a), the output of the comparator D ₁ Waveform (a) never exceeds the reference voltage Vref ₁ is always 0. Similarly, the outputs of the comparators D ₂ and D ₃ are always 0. In the comparator D ₄ , there is a part where the peak value of the waveform (a) is slightly higher than the reference voltage Vref ₄ , so that 1 is output in the part exceeding this, and 0 is output in the other part. Thus, the comparator D ₄ outputs 1 and 0. Similarly, the outputs of the comparators D ₅ and D ₆ are 1 and 0. The comparator D ₇ compares the waveform (a) with the reference voltage Vref _7, but since the waveform (a) always exceeds the reference voltage Vref ₇ , the comparator D ₇ always outputs 1. Similarly, the outputs of the comparators D ₈ and D ₉ are always 1.

Further, the signal from the EQ circuit _{K 1} waveform (b) is output. In this case, the comparator D ₁ reference voltage Vref ₁ and the waveform (b) in are compared, the output of comparator D ₁ Waveform (b) never exceeds the reference voltage Vref ₁ is always 0. Similarly, the output of the comparator D ₂ is always zero. In the comparator D ₃ , there is a part where the peak value of the waveform (b) is slightly higher than the reference voltage Vref ₃ , so that 1 is output in the part exceeding this, and 0 is output in the other part. Thus, the output comparator D ₃ in 1 and 0. Similarly, the outputs of the comparators D _{4 to} D ₇ are 1 and 0. Comparator D reference voltage Vref ₈ and waveform (b) in ₈ are compared, since the waveform (b) is always higher than the reference voltage Vref _8, always one is output from comparator D _8. Similarly, the output of comparator D ₉ is always 1.

Further, the signal from the EQ circuit _{K 1} waveform (c) is output. In this case, the comparator D ₁ reference voltage Vref ₁ and the waveform (c) in are compared, the output of comparator D ₁ Waveform (c) never exceeds the reference voltage Vref ₁ is always 0. In the comparator D ₂ , there is a portion where the peak value of the waveform (c) is slightly higher than the reference voltage Vref ₂ , so 1 is output in the portion exceeding this, and 0 is output in the other portion. Thus, the output comparator D in ₂ 1 0. Similarly, 1 and 0 are output as outputs from the comparators D _{3 to} D ₈ . The comparator D ₉ compares the waveform (c) with the reference voltage Vref _9, but since the waveform (c) always exceeds the reference voltage Vref ₉ , the comparator D ₉ always outputs 1.

In this way, the outputs of the comparators D _{1 to} D ₉ differ depending on the level of the amplitude value of the signal input from the EQ circuit K _1, and the determination / adjustment circuit K ₂ receiving this signal receives the signal from the EQ circuit K ₁ . The level, and therefore the gain of the transmission line L can be determined. That is, by comparing the comparators D ₁ , D ₂ ,... D ₉ that output both 0 and 1 and the comparators that always output 0 or 1 , the output amplitude of the EQ circuit K ₁ can be determined to where it is in the range of the reference voltages of the comparators.

Figure 3 is a view for explaining the outline of the characteristic setting processing of the EQ circuit K ₁ of the present embodiment.

In FIG. 3, 10 indicates the frequency characteristic of the transmission line L. Gain of the point 16 on the frequency characteristic 10 in the frequency _{f m + 1,} the gain of the point 17 is at the frequency _{f m,} the point 18 represents the gain at the frequency _{f m-1.} Reference numeral 11 denotes an upper limit frequency (= basic frequency f ₁ ) of a frequency band required for signal transmission. Reference numeral 12 denotes a target frequency characteristic synthesized by the target transmission line L and the EQ circuit K ₁ , and the target is that the frequency characteristic synthesized by the transmission line L and the EQ circuit K ₁ becomes a flat characteristic. For example the gain due to the transmission path L at the frequency f _m which is indicated by point 17, as synthesized gain of the transmission path L and EQ circuit K _1, as shown the gain correction by the arrow 14, the point on the target frequency characteristic 12 19 It is to set the characteristics of the EQ circuit K ₁ to come. The target frequency characteristic 12 indicates an allowable width lower limit line that is a minimum allowable gain.

In this embodiment, in order to correct the frequency characteristics of the transmission path L, and a plurality of candidates of the equalizer characteristic to be set to the EQ circuit K _1, but in advance stored in the judgment / regulation circuit K ₂ are prepared are real so often the frequency characteristics of the transmission path L is has become a complicated frequency characteristic, for example, setting the point at other frequencies also be ideally set at the frequency f _m is over the target frequency characteristic 12 Not necessarily. It is difficult to select an equalizer characteristic that can be corrected so as to be the target frequency characteristic 12 at all frequencies within the frequency band required for signal transmission. Therefore, in this embodiment, the selection is made with a predetermined allowable width. The allowable width in this case is indicated by 15. Reference numeral 13 denotes an allowable gain upper limit line of allowable gain. The allowable width 15 can be adjusted.

  Next, the equalizer characteristic setting according to the present embodiment will be described with reference to FIG.

Prior to the present process, are candidates in advance prepare a plurality of equalizer characteristic to be set to the EQ circuit K _1, it is stored in the judgment / regulation circuit K _2.

First, in step S1, initializing the characteristics of the EQ circuit _{K 1} to the default values. For example, in all frequencies within the frequency band required for signal transmission, the characteristics of the EQ circuit K ₁ is set to be a flat gain characteristic. The flat gain characteristic facilitates the correspondence with the characteristics of the transmission line L. However, if conversion is performed when the correspondence is taken, the present invention is not limited to this.

Next, in step S2, it selects the output from the flip-flop F ₁ of pulse generator 4 by the selection circuit SL, and outputs the fundamental frequency f ₁ from the pulse generator 4, via the transmission line L EQ circuit K ₁ receives this.

In step S3, by comparing the signal from the EQ circuit _{K 1} by the comparator _D 1 to D _N, the comparator _D 1 to D determination / adjustment circuit _{K 2} which receives the output of the _N, the comparator _D 1 to D determining the magnitude of the output of the EQ circuit K ₁ from the output state of _N.

In step S4, judgment / regulation circuit K ₂ is the equalizer characteristic having a gain magnitude of the output of the EQ circuit K ₁ enters the allowable range 15 is selected from among a plurality of characteristics stored in advance. In this case, a plurality of equalizer characteristics in which the output of the EQ circuit K ₁ falls within the allowable width 15 at the frequency f ₁ are selected.

Next, in step S5, output from the pulse generator 4 to the next frequency f _2, and transmits to the EQ circuits K ₁ via the transmission line L. This can make a selection signal for selecting the output of the flip-flop F _2, and from the determination / adjustment circuit K ₂ when the process of step S4 has been completed so as to output to the selector SL.

In step S6, the magnitude of the output of the EQ circuit K ₁ is the equalizer characteristic to enter the allowable range 15 to select from among the properties selected in the previous step S4. The characteristic selected at this time is an equalizer characteristic in which the output of the EQ circuit K ₁ falls within the allowable range 15 at both the frequencies f ₁ and f ₂ .

In step S7, whether the frequency of the pulse generator 4 was performed for all frequencies f ₁ ~f _n is checked. When the frequency is not executed for all frequencies, the process returns to step S5, and the process is continued until the frequency is executed for all frequencies. In this case step S5~S7 are repeatedly executed, in step S6, so that all the output of the EQ circuit _{K 1} for the execution frequency _{f 1, f} 2 ··· is gradually left equalizer characteristic to enter the tolerance 15 Will be processed.

  If it is determined in step S7 that the process has been executed for all frequencies, the process proceeds to step S8. In step S8, it is checked whether or not there is an equalizer characteristic that falls within the remaining allowable width 15.

  If it is determined in step S7 that there is no remaining characteristic, the process proceeds to step S9, the allowable width 15 is increased by a predetermined width, and the process returns to step S2. As a result, the suboptimal characteristic selection process is continued, and is repeatedly performed until it is determined that there is a remaining characteristic in step S8.

If it is determined in step S8 that there is no remaining characteristic, the allowable width 15 set in step S9 is gradually widened, but an upper limit is provided for this width, and even this upper allowable width 15 is finally reached in step S8. remains when the characteristic is determined not to, the alarm displays that can not be set the proper equalizer characteristic EQ circuit K _1, or may end the process so as to issue a warning sound.

  In addition, when there are a lot of characteristics finally remaining in step S8, it is conceivable to reduce the allowable width 15 set in step S9 so that an appropriate number of characteristics remain.

If it is determined in step S8 that there are finally remaining characteristics, the process proceeds to step S10. In step S8 from the finally remaining properties by selecting one characteristic set to the EQ circuit K _1. For this selection, any one may be selected, or one in a specific order (for example, the first selected characteristic) may be selected. Further, it is possible to verify to what extent the total characteristics of the transmission frequency characteristic and the equalizer frequency characteristic are deviated from the target frequency characteristic 12 at each frequency, and select the one having the smallest deviation amount.

When remaining equalizer characteristic in this final is set to the EQ circuit K _1, becomes the overall frequency characteristics of the transmission path L and EQ circuit K ₁ is approximated to the target frequency characteristic. Therefore, it is possible to obtain a signal without waveform distortion from EQ circuit K _1.

Note that after the equalizer characteristic adjustment is completed, the pulse generator 4 transmission line L is disconnected, alternatively control circuit for transmitting a signal is connected to, is connected to the tip of the buffer circuit BF via the EQ circuits K ₁ Data transmission / reception is performed with a circuit unit (not shown). Here, it is assumed that the transmission circuit unit 2 includes only the pulse generation unit 4 and may be removed after the equalizer characteristic adjustment is completed. However, the transmission circuit unit 2 may be mounted together with another control circuit unit (not shown). In this case, after the equalizer characteristic adjustment is completed, the output from the pulse generation unit 4 and the output from the other control circuit unit may be switched by the selection circuit SL.

In the above embodiment has been to sequentially decrease the frequency of the pulse generator 4 from the basic frequency f _1, which may be performed in any order. Further, although the pulse generation unit 4 is configured by the flip-flops F _{1 to} F _n , an oscillator having another configuration may be used. Further, although the comparators D _{1 to DN} are used to detect the signal level of the EQ circuit K _1, the maximum value may be detected by the peak voltage detection circuit to detect the signal level.

  As mentioned above, although this invention was demonstrated by specific embodiment, this invention is not limited to the said embodiment, It cannot be overemphasized that it can change and implement in the range which does not deviate from the summary of this invention.

  INDUSTRIAL APPLICABILITY The present invention can be used for an equalizer circuit (equalization device) that improves signal waveform distortion caused by a signal transmission path in an electronic device and a signal transmission path between electronic devices.

It is a block diagram of the equalizer characteristic setting circuit by embodiment of this invention. It is a figure which shows the example of the output waveform of EQ circuit by embodiment of this invention. It is a figure which shows the concept of the equalizer characteristic setting by embodiment of this invention. It is an operation | movement flowchart of the equalizer characteristic setting circuit by embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Equalizer characteristic setting circuit 2 ... Transmission circuit part 3 ... Reception circuit part 4 ... Pulse generation part 5 ... EQ characteristic adjustment part (Equalizer characteristic adjustment part)
10: Frequency characteristic of transmission line L 11: Upper frequency limit of frequency band required for signal transmission 12 ... Target frequency characteristic (allowable width lower limit line)
13 ... tolerance limit line 14 ... gain correction showing the arrow 15 ... tolerance 16-18 ... _F 1 point on a point 19 ... target frequency characteristic 12 of the frequency characteristic 10 to F _n ... flip-flop SL ... selection circuit K ₁ ... EQ circuit (equalizer circuit)
K ₂ ... Judgment / adjustment circuits D _{1 to} D _N ... Comparator BF ... Buffer circuits Vref _{1 to} Vref _N ... Reference voltage TM ₁ ... Transmission end TM ₂ ... Reception end

Claims (10)

In an equalizer characteristic setting circuit for setting an equalizer characteristic of an equalizer circuit that corrects and outputs a waveform distortion of a signal received via a transmission line,
Signal generating means for outputting a signal having a repetitive waveform at a plurality of different frequencies within a frequency band required for signal transmission;
An equalizer circuit for receiving a signal from the signal generating means via the transmission path;
An equalizer characteristic setting circuit comprising: equalizer characteristic adjusting means for selecting an equalizer characteristic for compensating the frequency characteristic of the transmission line based on an output waveform of the equalizer circuit and setting the equalizer characteristic in the equalizer circuit. The equalizer characteristic adjusting means is
Equalizer characteristic storage means for storing a plurality of equalizer characteristics;
Amplitude detecting means for detecting the amplitude of the output waveform of the equalizer circuit at the plurality of frequencies;
Based on the amplitude detected by the amplitude detection means, one equalizer characteristic capable of compensating the frequency characteristic of the transmission line within an allowable range at the plurality of frequencies is stored in the equalizer characteristic storage means. The equalizer characteristic setting circuit according to claim 1, further comprising a determination / adjustment circuit that selects and sets the equalizer circuit in the equalizer circuit.   The determination / adjustment circuit selects an equalizer characteristic that can compensate so that a signal amplitude output from the equalizer circuit falls within a predetermined allowable range with respect to a target frequency characteristic in all received frequency signals. The equalizer characteristic setting circuit according to claim 2.   4. The equalizer characteristic setting circuit according to claim 2, wherein the amplitude detection means includes a plurality of comparison means for comparing the output waveforms of the equalizer circuit with different predetermined reference voltage values. The signal generating means sequentially outputs signals of different frequencies,
5. The equalizer characteristic adjustment unit according to claim 1, wherein the equalizer characteristic adjusting unit further selects an equalizer characteristic to be selected in a signal of a frequency received next from among the equalizer characteristics selected in advance. Equalizer characteristic setting circuit. In the equalizer characteristic setting method of the equalizer circuit that corrects and outputs the waveform distortion of the signal,
A signal waveform of a plurality of different frequencies is received by an equalizer circuit via a transmission line,
Based on the waveform output from the equalizer circuit, an equalizer characteristic that compensates the frequency characteristic of the transmission path at all of the plurality of different frequencies is selected from a plurality of equalizer characteristics prepared in advance and set in the equalizer circuit. The equalizer characteristic setting method characterized by this. The plurality of equalizer characteristics prepared in advance are stored in advance in storage means,
The equalizer characteristic setting circuit according to claim 6, wherein the equalizer characteristic setting circuit is selected from the plurality of stored equalizer characteristics and set in the equalizer circuit based on a waveform output from the equalizer circuit.   8. The equalizer characteristic according to claim 6, wherein an equalizer characteristic capable of compensating so that a signal amplitude output from the equalizer circuit falls within a predetermined allowable range is selected for signals of all frequencies received. Equalizer characteristic setting circuit.   9. The equalizer characteristic setting circuit according to claim 8, wherein an output waveform of the equalizer circuit is compared with different predetermined reference voltage values to determine a signal amplitude output from the equalizer circuit. The equalizer circuit sequentially receives signals of different frequencies,
The equalizer characteristic setting circuit according to any one of claims 6 to 10, wherein an equalizer characteristic to be selected in a signal having a frequency to be received next is further selected from the previously selected equalizer characteristics. .

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