KR100980422B1 - Apparatus for driving data of semiconductor integrated circuit - Google Patents

Abstract

The present invention provides a decoder configured to output a voltage level detection signal by decoding a code signal whose code value is changed according to a change in an external voltage; And a driver configured to drive and output data at a variable slew rate, the slew rate of which varies according to the voltage level detection signal.

Slew Rate, ZQ Calibration

Description

Data driving device for semiconductor integrated circuits {APPARATUS FOR DRIVING DATA OF SEMICONDUCTOR INTEGRATED CIRCUIT}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a data driving apparatus of a semiconductor integrated circuit.

The data driver of a semiconductor integrated circuit according to the related art sets a slew rate to match a predetermined supply voltage through simulation.

Therefore, when the level of the supply voltage changes, the slew rate also changes according to the level change of the supply voltage.

That is, as shown in FIG. 1, the slew rate of the driver increases as the level of the supply voltage (eg, VDD) increases, and decreases as the level of the external voltage VDD decreases. .

As a result, as shown in FIG. 1, when the external voltage VDD is a low voltage condition and a high voltage condition, the slew rate may have an abnormal value out of a predetermined specification. .

In addition to the supply voltage, the slew rate of the driver can also be changed by process or temperature changes.

As such, when the slew rate of the driver increases above a predetermined level, signal quality such as high frequency noise and overshoot due to the increase of the high frequency component of the output signal is increased, and additionally, electromagnetic magnetic interference ) Can also be increased.

Even if the slew rate of the driver decreases below a predetermined level, data driving is not performed quickly and reliably, resulting in deterioration of data processing performance and inability to guarantee the reliability of the output data.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data driving apparatus for a semiconductor integrated circuit capable of maintaining a slew rate at an optimal level regardless of a change in operating environment.

According to another aspect of the present invention, a data driving apparatus of a semiconductor integrated circuit may include: a decoder configured to decode a code signal whose code value is changed according to a change in an external voltage and output a voltage level detection signal; And a driver configured to vary the slew rate according to the voltage level detection signal and to drive and output data at a variable slew rate.

According to another aspect of the present invention, a data driving apparatus of a semiconductor integrated circuit may include: a decoder configured to decode a code signal whose code value is changed according to a change in an external voltage and output a voltage level detection signal; And a plurality of driving elements having different sizes, wherein the plurality of driving elements are configured to selectively drive data by selectively operating in response to the voltage level detection signal.

According to another aspect of the present invention, a data driving apparatus of a semiconductor integrated circuit may include: a decoder configured to decode a code signal whose code value is changed according to a change in an external voltage and output a voltage level detection signal; A pre-driver configured to output a pull-up / pull-down signal by varying the slew rate according to the voltage level detection signal and driving data at the variable slew rate; And a main driver configured to drive the data pad to a level corresponding to the pull up / pull down signal.

The data driving apparatus of the semiconductor integrated circuit according to the present invention can maintain the slew rate at an optimal level regardless of the change in the operating environment including the supply voltage, thereby improving data driving performance.

The semiconductor integrated circuit includes a ZQ calibration block for matching a ZQ calibration resistance value with a resistance value of a reference resistor external to the semiconductor integrated circuit connected through the ZQ pin.

The termination resistance value of the driver is set according to the ZQ calibration code signal determined through the process of matching the ZQ calibration resistance value with the resistance value of the reference resistor in the ZQ calibration block.

The ZQ calibration resistance value may change in response to a change in the PVT (PROCESS / VOLTAGE / TEMPERATURE), for example, the external voltage VDD, and the ZQ calibration code signal is a value capable of compensating the ZQ calibration resistance value. Has changing characteristics.

The code value of the ZQ calibration code signal changes according to the value of the ZQ calibration resistor, and the code value of the ZQ calibration code signal is different depending on the height of the external voltage VDD even for the same ZQ calibration code signal.

As a result, it is possible to know the change of the external voltage according to the code value of the ZQ calibration code signal.

The ZQ calibration code signal may include a first code signal PCODE <N: 0> and a second code signal NCODE <N: 0>. The first code signal PCODE <N: 0> is a code signal for setting a termination resistance value on the pull-up side of the driver, and the second code signal NCODE <N: 0> is a code signal of the driver. Code signal to set the pull-down side termination resistor value.

According to the present invention, it is possible to know a change in an external voltage according to the above-described principle, that is, a code value of a ZQ calibration code signal, and by using a characteristic in which a code value of a ZQ calibration code signal is changed in a direction to compensate for the above-described change in external voltage. The slew rate of the data driver is maintained at a constant level.

Hereinafter, exemplary embodiments of a data driving apparatus for a semiconductor integrated circuit according to the present invention will be described with reference to the accompanying drawings.

2 is a block diagram of a data driving apparatus of a semiconductor integrated circuit according to the present invention.

As shown in FIG. 2, the data driving apparatus 100 of the semiconductor integrated circuit according to the present invention may include a decoder 110, a first pre-driver 130, a second pre-driver 150, and a first main driver 170. ) And a second main driver 190.

The decoder 110 is an external code signal and includes some upper bits of each of the first code signal PCODE <N: 0> and the second code signal NCODE <N: 0> output from the ZQ calibration block 10. decode any one of (bit) (PCODE <N: K>, NCODE <N: K>) (for example, PCODE <N: K>) (hereinafter, code signal for voltage level detection) And configured to generate the three voltage level detection signals HV, MV, and LV. Each of the first to third voltage level detection signals HV, MV, and LV includes a section to which an external voltage VDD belongs, that is, a high voltage section High VDD, a middle voltage section Mid VDD, and a low voltage section Low VDD. This signal is activated by detecting.

The decoder 110 defines that a code value of the voltage level detection code signal PCODE <N: K> defines the high voltage section High VDD, the medium voltage section Mid VDD, or the low voltage section Low VDD. Accordingly, the first to third voltage level detection signals HV, MV, and LV may be selectively activated.

The first pre driver 130 drives the data DATAR at a slew rate that is variable according to the first to third voltage level detection signals HV, MV, and LV, and pulls up the data DATAR. And output a pull up signal UP.

The second pre-driver 150 drives the data DATAF at a slew rate variable according to the first to third voltage level detection signals HV, MV, and LV to pull down signals DN. Is configured to output

The first main driver 170 is configured to drive the data pad DQ to a power level (eg, VDDQ) according to the pull-up signal UP. In the first main driver 170, a termination resistance value is set according to the first code signal PCODE <N: 0>.

The second main driver 190 is configured to drive the data pad DQ to a ground level (eg, VSSQ) according to the pull down signal DN. The second main driver 190 has a termination resistance value set according to the second code signal NCODE <N: 0>.

Output terminals of the first main driver 170 and the second main driver 190 are commonly connected to the data pad DQ.

The slew rates of the first main driver 170 and the second main driver 190 are determined by the pull up signal UP and the pull down signal DN, respectively. That is, as the slew rate of the first pre-driver 130 increases / decreases, the slew rate of the first main driver 170 also increases / decreases. The same applies to the second main driver 190.

3 is a circuit diagram of the first pre-driver of FIG. 2.

The first pre-driver 130 and the second pre-driver 150 may be configured in the same manner.

As illustrated in FIG. 3, the first pre-driver 130 supplies the first to third inverters IV1 to IV3 and the first to third tree state inverters TSB_HV, TSB_MV, and TSB_LV. Equipped.

The first to third inverters IV1 to IV3 are configured to invert and output each of the first to third voltage level detection signals HV, MV, and LV.

Input terminals and output terminals are commonly connected to the first to third tree state inverters TSB_HV, TSB_MV, and TSB_LV, respectively. The first to third tree state inverters TSB_HV, TSB_MV, and TSB_LV are configured to operate in response to activation of each of the first to third voltage level detection signals HV, MV, and LV.

The first to third tree state inverters TSB_HV, TSB_MV, and TSB_LV show an example in which the sizes increase in order and the slew rate increases in proportion.

The operation of the data driving apparatus of the semiconductor integrated circuit according to the present invention configured as described above is as follows.

As described above, the code value of the voltage level detection code signal PCODE <N: K> also increases or decreases as the external voltage VDD rises or falls.

The decoder 110 may have a code value of the voltage level detection code signal PCODE <N: K> in which the external voltage VDD has a high voltage section High VDD, a middle voltage section Mid VDD, or a low voltage section Low. VDD) selectively activates the first to third voltage level detection signals HV, MV, and LV.

When the external voltage VDD belongs to the intermediate voltage section Mid VDD, the decoder 110 may perform a second voltage level detection signal MV among the first to third voltage level detection signals HV, MV, and LV. Only activate it.

As the second voltage level detection signal MV is activated, the second tree state inverter TSB_MV drives the data DATAR from among the first to third tree state inverters TSB_HV, TSB_MV, and TSB_LV of FIG. 3. The up signal UP is output.

On the other hand, when the external voltage VDD belongs to the high voltage section High VDD, the decoder 110 performs a first voltage level detection signal HV among the first to third voltage level detection signals HV, MV, and LV. ) To activate only.

As the first voltage level detection signal HV is activated, the first tree state inverter TSB_HV drives the data DATAR from among the first to third tree state inverters TSB_HV, TSB_MV, and TSB_LV of FIG. 3. The up signal UP is output.

The first tree state inverter TSB_HV is designed to have a smaller size than the second tree state inverter TSB_MV.

Accordingly, when the first tree state inverter TSB_HV is selected, the first pre-driver 130 operates at a reduced slew rate than when the second tree state inverter TSB_MV is selected.

That is, since the external voltage VDD belongs to the high voltage section High VDD, a driver having a smaller size than the medium voltage section Mid VDD is selected to reduce the slew rate, thereby causing an abnormal slew due to the increase in the external voltage level. Rate increase can be compensated.

On the other hand, when the external voltage VDD belongs to the low voltage section Low VDD, the decoder 110 performs a third voltage level detection signal LV among the first to third voltage level detection signals HV, MV, and LV. ) To activate only.

As the third voltage level detection signal LV is activated, the third tree state inverter TSB_LV drives the data DATAR among the first to third tree state inverters TSB_HV, TSB_MV, and TSB_LV of FIG. 3. Output the pull-up signal UP.

The third tree state inverter TSB_LV is designed to have a larger size than the second tree state inverter TSB_MV.

Therefore, when the third tree state inverter TSB_LV is selected, the first pre-driver 130 operates at an increased slew rate than when the second tree state inverter TSB_MV is selected.

That is, since the external voltage VDD belongs to the low voltage section Low VDD, an increase in the slew rate by selecting a driver having a larger size than the mid voltage section Mid VDD results in abnormal slew due to the drop in the external voltage VDD level. Rate reduction can be compensated.

The second predriver 150 also operates in the same manner as the first predriver 130.

The first main driver 170 and the second main driver 190 operate at a slew rate determined by the pull-up signal UP and the pull-down signal DN to bring the data pad DQ to a power level or a ground level. Drive.

4 is a graph illustrating a slew rate variation with respect to an external voltage variation according to the present invention.

As shown in FIG. 4, the present invention can confirm that the slew rate is varied according to the level variation of the external voltage VDD, and the variation of the variable slew rate satisfies a specified specification.

As a result, the data driving apparatus of the semiconductor integrated circuit according to the present invention can maintain the slew rate at an optimal level regardless of the variation of the external voltage.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a graph showing a slew rate variation with respect to an external voltage variation according to the prior art;

2 is a block diagram of a data driving apparatus of a semiconductor integrated circuit according to the present invention;

3 is a circuit diagram of a first predriver of FIG. 2;

4 is a graph illustrating a slew rate variation with respect to an external voltage variation according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10: ZQ calibration block 110: decoder

130: first free driver 150: second free driver

170: first main driver 190: second main driver

Claims (16)

A decoder configured to output a voltage level detection signal by decoding a code signal whose code value is changed according to a change in an external voltage; A driver configured to drive and output data at a slew rate, the slew rate being variable according to the voltage level detection signal; And And a code adjusting block configured to vary a code value of the code signal by comparing a difference between an external resistor and an internal resistor connected to an external resistor connecting pin of the semiconductor integrated circuit. delete The method of claim 1, The decoder And decode some bits of all bits of the code signal to generate the voltage level detection signal. The method of claim 3, wherein The driver It has a plurality of driving elements of different sizes, And the plurality of driving elements are selectively operated according to the voltage level detection signal. The method of claim 4, wherein And a plurality of driving elements of which the input terminal and the output terminal are commonly connected. A decoder configured to output a voltage level detection signal generated by decoding a code signal whose code value is changed according to an external voltage change; A driver having a plurality of driving elements having different sizes, the driver configured to selectively drive the data by selectively operating the plurality of driving elements in response to the voltage level detection signal; And And a code adjusting block configured to vary a code value of the code signal by comparing a difference between an external resistor and an internal resistor connected to an external resistor connecting pin of the semiconductor integrated circuit. delete The method of claim 6, The decoder And decode some bits of all bits of the code signal to generate the voltage level detection signal. The method of claim 8, The voltage level detection signal includes a plurality of detection signals, The driver And a driving element for inputting the plurality of detection signals to correspond to the plurality of driving elements in a one-to-one manner, and configured to operate a driving element for receiving a detection signal activated among the plurality of detection signals. The method of claim 6, And a plurality of driving elements of which the input terminal and the output terminal are commonly connected. delete delete delete delete delete delete

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