KR100976412B1 - Method for manufacturing semiconductor memory device - Google Patents

Abstract

The present invention discloses a method of manufacturing a semiconductor memory device having a zigzag storage node contact plug, which can simplify the process. The disclosed invention firstly sequentially deposits a first interlayer insulating film, an etch stopper and a second interlayer insulating film over a semiconductor substrate on which a bit line is formed. Thereafter, a second interlayer insulating film, an etch stopper, and a first interlayer insulating film are etched to expose a predetermined portion of the semiconductor substrate, thereby defining a preliminary storage node contact region, and a second adjoining the preliminary storage node contact region and one side thereof. A photoresist pattern is formed so that a predetermined portion of the interlayer insulating film is exposed. Thereafter, the second interlayer insulating film is etched in the form of the photoresist pattern, and then the photoresist pattern is removed to define a storage node contact region in which an upper edge portion extends laterally. Finally, a plug is formed inside the storage node contact area.

Storage Node, Zigzag, Photoresist, Process Simplification

Description

Method for manufacturing semiconductor memory device

1A to 1D are cross-sectional views of respective processes for explaining a method of manufacturing a conventional semiconductor memory device.

2A to 2D are cross-sectional views of respective processes for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 110 bit line

120: first interlayer insulating film 130: etch stopper

140: second interlayer insulating film 150: photoresist film

160: storage node contact plug 170: lower electrode

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a semiconductor memory device having a storage node contact plug arranged in a zigzag shape.                         

In recent years, as the degree of integration of semiconductor devices increases, the area occupied by devices within chips is decreasing. Accordingly, the lower electrode of the capacitor is formed in a three-dimensional form, such as a cylinder (cylinder), a fin (fin), or the like, and furthermore, the lower electrode is formed in a three-dimensional form, arranged in a jig-jag form Therefore, a method of securing a maximum surface area in a limited space has been proposed.

1A to 1D, a method of manufacturing a lower electrode arranged in a zigzag form according to the related art will be described.

First, referring to FIG. 1A, a bit line 12 is formed on a semiconductor substrate 10 in a known manner. Although not shown in the drawings, a word line, a source, a drain, and a contact plug are formed in the semiconductor substrate 10. The first interlayer insulating layer 14 is deposited on the semiconductor substrate 10 on which the bit lines 12 are formed, and then contacted with a predetermined portion of the semiconductor substrate 10, for example, a source (not shown) or a source. The interlayer insulating layer 14 is etched to expose the contact plug (not shown), thereby defining the first storage node contact region A. FIG.

As shown in FIG. 1B, a first polysilicon film is deposited on the resultant semiconductor substrate 10, and then the first polysilicon film is subjected to chemical mechanical polishing (CMP) or until the surface of the interlayer insulating film 14 is exposed. It etches back to form the first storage node contact plug 16 in the first storage node contact region A. FIG.

Next, as illustrated in FIG. 1C, the etch stopper 18 and the second interlayer insulating layer 20 are sequentially stacked on the interlayer insulating layer 14 on which the first storage node contact plug 16 is formed. Next, in order to arrange the contact plugs in a zigzag form, the second interlayer insulating film 20 and the etch stopper 18 are exposed to expose a portion of the first storage node contact plug 16 and the first interlayer insulating film 14 adjacent thereto. ) Is defined to define the second storage node contact region (B).

Thereafter, as shown in FIG. 1D, a second polysilicon film is deposited on the second interlayer insulating film 20 to fill the second storage node contact region B, and the second poly film is exposed to expose the second interlayer insulating film 20. The silicon film is CMP or etched back to form the second storage node contact plug 22. Thereafter, a cylindrical lower electrode 24 is formed on the second storage node contact plug 22.

However, the method of forming the zigzag lower electrode requires a repeated process of polysilicon film deposition to form the first and second storage node contact plugs, and planarization processes such as CMP and etchback, thereby increasing process time. Of course, there is a high possibility that defects will occur as the process becomes complicated.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor memory device having a zigzag bottom electrode which can simplify the process.

In order to achieve the above object of the present invention, the manufacturing method of the semiconductor memory device of the present invention is as follows. First, a first interlayer insulating film, an etch stopper, and a second interlayer insulating film are sequentially deposited on the semiconductor substrate on which the bit lines are formed. Thereafter, a second interlayer insulating film, an etch stopper, and a first interlayer insulating film are etched to expose a predetermined portion of the semiconductor substrate, thereby defining a preliminary storage node contact region, and a second adjoining the preliminary storage node contact region and one side thereof. A photoresist pattern is formed so that a predetermined portion of the interlayer insulating film is exposed. Thereafter, the second interlayer insulating film is etched in the form of the photoresist pattern, and then the photoresist pattern is removed to define a storage node contact region in which an upper edge portion extends laterally. Finally, a plug is formed inside the storage node contact area.

In this case, the first interlayer insulating film may be formed of one film selected from BPSG film, TEOS film, and SOG, and the second interlayer insulating film may be a PE-TEOS film, LP-TEOS film, PE-USG film, room temperature oxide film, It can be formed of one film selected from a BPSG film and an HDP film.

In addition, the thickness of the second interlayer insulating film is characterized in that the same as or thinner than the thickness of the first interlayer insulating film.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. 2A to 2D are cross-sectional views of respective processes for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 2A, a bit line 110 is formed on the semiconductor substrate 100. As described above, the semiconductor substrate 100 may include a transistor including a word line, a source, and a drain, and a connection pad electrically connected to the source and the drain. In addition, the bit line 110 may be arranged in a direction crossing the word line, and may be formed, for example, of a doped polysilicon film, a stacked film of a doped polysilicon film and a transition metal film, or a transition metal film.

The first interlayer insulating layer 120 is formed on the semiconductor substrate 100 on which the bit line 110 is formed. The first interlayer insulating layer 120 may be formed of, for example, a borophosphorus silicate glass (BPSG) film, a tetraethoxysilane (TEOS) film, a spin on glass (SOG) film, or the like.

An etch stopper 130 and a second interlayer insulating layer 140 are sequentially formed on the first interlayer insulating layer 120. The etch stopper 130 is formed of a material having a different etching selectivity from the first and second interlayer insulating films 120 and 140, for example, a silicon nitride film, and may be formed of a plasma enhanced chemical vapor deposition (PECVD) method or a low pressure chemical vapor deposition (LPCVD) method. It may be formed to a thickness of 100 to 1000Å by the vapor deposition method. The second interlayer insulating layer 140 may be formed to be the same or thinner than the first interlayer insulating layer 120. For example, the second interlayer insulating layer 140 may be formed to have a thickness of 300 to 3000 μs, a PE (plasma enhanced) -TEOS layer, and a low pressure (LP). ) -TEOS film, PE-USG (undoping silicate glass) film, room temperature oxide film, BPSG film or HDP (high density plasma) film can be formed.

Next, as illustrated in FIG. 2B, the second interlayer insulating layer 140, the etch stopper 130, and the first interlayer insulating layer 140 are exposed to expose a predetermined region of the semiconductor substrate, for example, a source or a connection pad electrically contacted with the source. The first interlayer insulating layer 120 is etched to form a preliminary storage node contact region A. FIG.                     

Referring to FIG. 2C, the photoresist film is coated to a predetermined thickness so that the preliminary storage node contact region A is filled on the resultant, and then the second interlayer insulating layer 140 on one side of the storage node contact region A and the storage node contact region is formed. The photoresist film is exposed and developed to expose a predetermined portion of the upper portion thereof, thereby forming the photoresist pattern 150.

As shown in FIG. 2D, the second interlayer insulating layer 140 is etched using the photoresist pattern 150 as a mask, and then the photoresist pattern 150 is removed. This defines a storage node contact region whose top region extends laterally. Next, a doped polysilicon layer is deposited on the semiconductor substrate 100 to fill the storage node contact region A. Then, the doped polysilicon layer is CMP or etched back to expose the surface of the second interlayer insulating layer 140. Thus, the storage node contact plug 160 is formed. In this case, the storage node contact plug 160 has a shape in which an upper region extends laterally, that is, a zigzag shape, as compared with the related art.

Thereafter, the lower electrode 170 is formed in a known cylinder manner to be in contact with the storage node contact plugs 160 arranged in a zigzag form.

As described in detail above, according to the present invention, the first interlayer insulating film, the etch stopper and the second interlayer insulating film are sequentially formed on the semiconductor substrate product on which the bit lines are formed, and then the preliminary storage node contact region is defined. Thereafter, a photoresist pattern is formed to expose the preliminary storage node contact region and the second interlayer insulating layer on one side of the preliminary storage node contact region. Then, the second interlayer insulating layer is etched in the form of a photoresist pattern, and the photoresist pattern is removed. The top defines a storage node contact region extending laterally. Thereafter, a plug is formed in the storage node contact area.

Accordingly, the zigzag-type storage node contact plug and the lower electrode may be formed by one process of depositing and planarizing the conductive layer for a plug. Therefore, the process can be simplified as compared with the prior art.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (4)

Providing a semiconductor substrate having bit lines formed thereon; Sequentially depositing a first interlayer insulating film, an etch stopper, and a second interlayer insulating film on the semiconductor substrate; Etching a second interlayer insulating film, an etch stopper, and a first interlayer insulating film to expose a predetermined portion of the semiconductor substrate to define a preliminary storage node contact region; Forming a photoresist pattern to expose a portion of the preliminary storage node contact region and a second interlayer insulating layer adjacent to one side thereof; Etching a second interlayer insulating film in the form of the photoresist pattern; Removing the photoresist pattern to define a storage node contact region in which an upper edge portion extends laterally; And And forming a plug in the storage node contact region. The method of claim 1, wherein the first interlayer insulating film is formed of one of BPSG film, TEOS film, and SOG. The semiconductor memory device of claim 1, wherein the second interlayer insulating film is formed of one film selected from a PE-TEOS film, an LP-TEOS film, a PE-USG film, a BPSG film, and an HDP film. Way. The method of manufacturing a semiconductor memory device according to any one of claims 1 to 3, wherein the thickness of the second interlayer insulating film is equal to or smaller than the thickness of the first interlayer insulating film.

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