KR100975941B1 - Nonvolatile Memory Device Using an impurity trap formed by a metal doping as a charge storage level and a Manufacturing method thereof - Google Patents

Abstract

The present invention relates to a nonvolatile memory device using an impurity trap formed by metal doping as a charge storage level, comprising: a p-type silicon substrate; A silicon oxide film deposited to a thickness of 5 nm formed on the p-type silicon substrate; An alumina layer (Al ₂ O ₃ ) deposited at a thickness of 40 nm on the silicon oxide film through atomic layer deposition (ALD); And an ion implantation layer comprising one of Nb, V, Ta, and Ru metal ions implanted into the alumina layer through an ion implantation method on the alumina layer, wherein the ion implantation layer acts as an impurity trap. The metal is characterized in that formed in atomic units.

 According to the nonvolatile memory device using the impurity trap formed by the metal doping according to the present invention as a charge storage level and a method of manufacturing the same, the impurity level is accurately determined by selecting a suitable type of metal ion by physical calculation and the concentration thereof is adjusted. It can be effective.

Impurity Trap, Ion Implantation, Doping, Charge Storage

Description

Nonvolatile memory device using an impurity trap formed by a metal doping as a charge storage level and a manufacturing method

The present invention relates to a nonvolatile memory device using the impurity trap formed by metal doping as a charge storage level, and a method of manufacturing the same. More particularly, the impurity level can be accurately determined by selecting the type of metal ion and the concentration thereof can be adjusted. The present invention relates to a non-volatile memory device using the impurity trap formed by metal doping as a charge storage level and thereby a method of manufacturing the same.

In the field of next-generation nonvolatile memory currently being studied, researches using discontinuous charge storage media such as silicon (Si) or germanium (Ge) nanocrystals and nitride traps have been actively conducted in charge trap memory (CTF). . Such research can prevent the loss of charge transfer, thereby improving the preservation of stored data. However, the density of charge storage traps of materials based on silicon (Si) nanocrystals stays in the range of 10 ¹¹ to 10 ¹² cm ^{- 2} , which does not provide enough memory window to implement multibit memory. Had Recently, memory devices such as Si / SiO ₂ / SiN / SiO ₂ / poly Si (SONOS) and Si / SiO ₂ / SiN / Al ₂ O ₃ / TaN (TANOS) using nitride traps have been developed for low driving voltage and thin tunnel insulating film. This is attracting attention because of the high possibility of high integration. However, the number of nitride traps is not enough to implement a device of about 45 nm, and especially in the case of SONOS, it is difficult to control the energy and concentration of naturally formed defect levels. This has the disadvantage of being limited.

In addition, one of the key issues of CTF is the write / erase (Program / Erase, P / E) speed and data preservation. These two factors have conflicting characteristics. For multilevel writes in the Fowler-Nordheim (FN) tunneling regime for hundreds of seconds, the thickness of the tunnel oxide should be less than 7 nm. In order to overcome such a trade-off, an optimized state of materials and structures such as a tunnel barrier, a charge trap layer, and a control barrier is required. In order to improve the performance of CTF memory, the use of high-k dielectric materials such as silicon nitride (SiN) and alumina (Al ₂ O ₃ ) can overcome the limitations of the thickness of the insulating film. Do.

1 is a graph showing the necessity of a memory semiconductor device during a charge trap such as a nanocrystal memory according to a technical problem of a polysilicon floating gate memory semiconductor device according to the related art.

Referring to FIG. 1, the conventional polysilicon floating gate memory semiconductor device requires a high operating voltage (9-10V), has a problem that the thickness of an oxide film, which is a dielectric material, becomes thick, and is programmed / deleted. / erasing) was a slow problem.

In addition, there was a low feasibility in the process of 65 nm or less (parts indicated as technical gaps, see FIG. 1). Thus, there has been a problem under viable standards.

2 is a view showing an example of a conventional charge trap flash memory semiconductor device.

Referring to Figure 2, as a method for replacing the conventional polysilicon floating gate as a method for overcoming the limitation of the continuous charge storage material. That is, a charge is injected and stored in a charge trap formed in a silicon oxide film or alumina (Al ₂ O ₃ ), which is a high-k material deposited on a p-type silicon substrate.

3A to 3C are energy band diagrams and a TEM graph in a SANOS structure in a programming and erasing mode of a semiconductor device of a conventional SONOS and SANOS structure.

As shown in Figs. 3A to 3C, previous research has implemented a memory device using a trap of nitride film, and this material has not had enough traps as the memory device is miniaturized. In addition, since the trap formed naturally in the nitride material has a great difficulty in controlling the energy and concentration of the defect level.

An object of the present invention is proposed to solve the problems in the prior art as described above, formed by metal doping and can artificially control the energy level and concentration, and even by reducing the size of the device by storing charge in atomic units The present invention provides a nonvolatile memory device using the impurity trap formed by metal doping that does not deteriorate as a charge storage level, and a method of manufacturing the same.

According to a preferred embodiment of the present invention for achieving the above object, the nonvolatile memory device using the impurity trap formed by the metal doping as the charge storage level is a p-type silicon substrate; A silicon oxide film deposited to a thickness of 5 nm formed on the p-type silicon substrate; An alumina layer (Al ₂ O ₃ ) deposited on the silicon oxide film by atomic layer deposition (ALD) at a thickness of 40 nm; And an ion implantation layer comprising one of Nb, V, Ta, and Ru metal ions implanted into the alumina layer through an ion implantation method on the alumina layer, wherein the ion implantation layer acts as an impurity trap. The metal is characterized in that formed in atomic units.

A method of manufacturing a nonvolatile memory device using an impurity trap formed by metal doping as a charge storage level according to the present invention is a method of depositing a silicon oxide film on a p-type silicon substrate with a thickness of 5 nm by thermal deposition. Stage 1; Depositing an alumina layer (Al ₂ O ₃ ) to a thickness of 40 nm on the silicon oxide film by atomic layer deposition (ALD); And a third step of performing an ion implantation process through an ion implantation method using one of Nb, V, Ta, and Ru metal ions on the alumina layer. An impurity trap is formed and the metal is formed in atomic units.

Preferably, the method further includes a fourth step of rapidly heat-treating the memory device including the alumina layer ion-implanted after the third step, wherein the fourth step is performed at a temperature of about 800 degrees in an N ₂ atmosphere for about 1 minute. Characterized in that.

Also preferably, a fifth step of depositing aluminum for use as an electrode after the third step is performed, wherein the diameter of the aluminum electrode in the fifth step is 100 micrometers.

Also preferably, the depth of the metal layer formed by implanting the metal by a predetermined depth of the alumina layer as a result of the ion implantation is formed at a depth of 20 to 25 nm vertically downward from the upper surface of the alumina layer.

Also preferably, the depth of the metal layer formed by implanting the metal by a predetermined depth of the alumina layer as a result of the ion implantation is formed at a depth of 30 to 35 nm vertically downward from the upper surface of the alumina layer.

As described above, according to the nonvolatile memory device using the impurity trap formed by the metal doping according to the present invention as the charge storage level and a method of manufacturing the same, the impurity level is accurately determined by selecting the appropriate type of metal ion by physical calculation. It has the effect of setting and adjusting the concentration.

Therefore, according to the present invention, the energy and concentration of the charge trap can be artificially controlled compared to the conventional nonvolatile memory device, and the trap is formed in atomic units, which is advantageous to manufacture a smaller device, and the reliability of the device is increased. There is.

According to the present invention, the existing research is to use the trap layer of SiN material as a memory device while the present invention artificially trapped by ion implanting metal (V, Nb, Ru, Ta) ion into Al ₂ O ₃ material It is very different in that it is used as a memory device by forming a layer, and this material / structure is the first research technology developed worldwide.

In addition, according to the present invention, there is a difference in memory characteristics according to each metal, among which V and Nb showed excellent performance in terms of memory characteristics, followed by Ru and Ta in the order of small amount of memory characteristics.

In addition, according to the present invention, as a result of SIMS measurement of a sample injected with vanadium (V) ions, it is determined that most vanadium ions are located near the interface between Al ₂ O ₃ and SiO ₂ (about 35 to 38 nm of Al ₂ O ₃ ). This was also confirmed by STEM.

In addition, according to the present invention, as a result of measuring CV hysteresis, a small amount of memory window appears in the case of a sample in which metal ion is not injected as the gate voltage increases, whereas metal ion ) Was injected into the memory window (memory window) increased.

Also, according to the present invention, the voltage of the full program / erase is set to + 12 / -12 V and 1 s, respectively, and the memory characteristics are measured using pulses. In the case of low energy samples, the program / erase (P / E) time is respectively 1 ms and 1 ms, however, the P / E time of the high energy samples was improved to 100 μs and 1 ms, respectively.

According to the present invention, the retention rate of the sample injected with low energy at room temperature resulted in about 38% charge loss based on 10 years, while the retention of the sample injected with high energy with V and Nb ion occurred. As a result, the charge loss ratio was about 26% for V and 19% for Nb.

In addition, according to the present invention, it can be seen that the CTF nonvolatile memory technology using the deep impurity trap level by metal ion implantation is a highly commercialized technology.

Hereinafter, a nonvolatile memory device using the impurity trap formed by metal doping according to the present invention as a charge storage level and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

In the present invention, as a method of forming a discontinuous charge storage trap layer, a high-k thin film Al ₂ O ₃ is doped with metal ions to artificially form a discontinuous impurity deep-level in an energy band gap. A nonvolatile semiconductor device was developed using the charge storage level.

An advantage of the present invention is that it is possible to accurately determine the impurity level and control its concentration by selecting the appropriate type of metal ion by physical basic calculation. Ion implantation was used as a method of doping metal ions to an Al ₂ O ₃ thin film formed by atomic layer deposition (ALD). As a result, the memory semiconductor device having excellent characteristics could be developed.

4A and 4B are diagrams illustrating a charge trap mechanism and an energy band by doped metal ions of a semiconductor device according to the present invention.

4A and 4B, the energy interval of Al ₂ O ₃ is 8.7 eV and a metal doping process, that is, a metal doping process by substitution of aluminum (Al) or oxygen (o) atoms is performed. The advantages of this method are the formation of deep-level traps, control of the electron storage trap density by the doping material, control of the electron / hole ratio by the doping material, and high-k ), The coupling ratio (coupling ratio) is increased.

Where k = 9 and the energy interval is 8.7 eV for alumina.

According to the present invention, as a result of calculation based on a physical basis, four metals (V, Nb, Ru, Ta) are doped into an Al ₂ O ₃ material and discontinuous impurity deep-substitution by substitution or the like. The CTF memory device was developed using the principle that the level) is artificially formed in the energy band gap, and it is difficult to escape to the outside when electrons are stored in the deep impurity level.

Hereinafter, a method of manufacturing a nonvolatile memory device using an impurity trap formed by metal doping according to the present invention as a charge storage level will be described sequentially with reference to FIGS. 5A to 5C.

Referring to FIG. 5A, a silicon oxide film 14 is deposited to a thickness of 5 nm on the p-type silicon substrate 12 by thermal deposition.

Subsequently, an alumina layer (Al ₂ O ₃ ) 16 is deposited to 40 nm on the silicon oxide layer 14 by atomic layer deposition (ALD).

Referring to FIG. 5B, an ion implantation process is performed on the alumina layer 16 formed in FIG. 5A through ion implantation using one of Nb, V, Ta, and Ru metal ions.

Reference numeral 15 denotes an ion implanted metal, and reference numeral 19 designates a metal injection layer range for indicating an implantation depth of the ion implanted metal.

Referring to FIG. 5C, the memory device including the alumina layer 16 implanted with ion in FIG. 5B is rapidly heat treated (about 1 minute at about 800 ° C. in an N ₂ atmosphere). Aluminum is then deposited (100 micrometers in diameter) for use as electrode 18.

The ion-implanted metal 15 is characterized by being implanted in atomic units, which is different from conventional nano-particles and can further increase the deposition density, thereby improving the characteristics of the device. The layer (ie, impurity trap) generated by the ion implanted metal 15 is used as the charge storage level. As a result, it is possible to artificially control the energy and concentration of the charge trap, which is possible by forming the impurity trap in atomic units as described above.

6 and 7 are diagrams schematically showing the metal ions implanted in the metal ion injection process performed in the process of FIG. 5b according to the present invention and the resulting implantation energy.

Referring to FIG. 6, at least one of V (vanadium), Nb (niobium), Ru (ruthenium), and Ta (tantalum) as the metal ions to be implanted is 50 keV, 80 keV for Nb and Ta, and 110 keV for Ru. The ion implantation energy is ion implanted at 1x 10 ¹² , 1x 10 ¹³ , 1x 10 ¹⁴ , 1x 10 ¹⁵ , 1x 10 ¹⁶ cm ^-2 , and the projected distance is 20-25nm from the surface.

Referring to FIG. 7, at least one material of V (vanadium) and Nb (niobium) as the implanted metal ion is 70 keV and Nb is 100 keV with ion implantation energy of 1x 10 ¹⁴ , 1x 10 ¹⁵ , 1x 10 ¹⁶ cm The ion implantation process is ^-2 , and the projected distance is 30 to 35 nm from the surface.

A memory characteristic according to Figure 8 to Figure 10 is an ion implantation respectively of the metal as graphs showing, respectively, the memory characteristics of the metal ion implantation is 1x10 ¹⁵ cm ^{- 2} of V ion the case of injection memory window up to 8.71 V is was measured, 1x10 ¹⁴ cm ^- the memory window was measured up to 5.02 V when the inject ^two of Nb ion. In the case of Ru and Ta ion implantation, a small amount of memory window was measured overall.

FIG. 11 is a graph showing the profile depth in the ion implantation energy (high energy (high energy) compared to FIG. 6) of FIG.

Referring to FIG. 11, the depth profile of V ions was measured for the sample of FIG. 7 through secondary ion mass spectrometry (SIMS). After the heat treatment (After Annealing) as shown in the above results, it was confirmed that most of the V ion is located near the interface between the Al ₂ O ₃ and SiO ₂ material (about 35 ~ 38 nm of Al ₂ O ₃ ).

12 is a graph showing metal ions for the sample of FIG.

Referring to FIG. 12, as a result of analyzing a sample by using a scanning transmission electron microscope (STEM), it was confirmed that V ion was detected at the same position as the SIMS measurement result.

FIG. 13 is a graph showing the hysteresis width for the sample of FIG. 7.

Referring to FIG. 13, in the case of the sample in which no metal ion was injected, the hysteresis window width was hardly increased even though the gate voltage was increased, whereas Vx and Nb ion injected with 1x10 ¹⁴ and 1x10 ¹⁵ per cm ⁻² were added. In the case of the sample, the hysteresis window increased as the measurement section voltage increased. This confirms that the memory effect is due to the metal ion implantation.

FIG. 14 is a graph showing the relationship between programming / erase rate versus implanted ions for the sample of FIG. 6.

Referring to FIG. 14, the increase and decrease of the memory window according to the pulse application time are measured using an Agilent 4284A CV meter and an Agilent 8114A pulse generator.

 As a result of setting the voltage of full program / erase to + 12 / -12 V and 1s, respectively, the program time of the sample of FIG. 6 is about 1 ms and the erase time is about 1ms.

FIG. 15 is a graph showing the relationship between programming / erase rate versus implanted ions for the sample of FIG. 7.

Referring to FIG. 15, in the case of the sample of FIG. 7, the program time is 100 μs and the erase time is about 1 ms. Compared with the sample of FIG. 6, it was confirmed to have a faster P / E rate at higher energy.

FIG. 16 is a graph showing the relationship between the retention time versus the injected V ion concentration for the sample of FIG. 6.

Referring to FIG. 16, the retention measurement of the sample of FIG. 6 at room temperature increases the memory window according to the increase of the amount of injected V ions, whereas the calculation is based on 10 years overall regardless of the amount injected. Overall, the charge loss was about 38 ~ 39%.

17 is a graph showing the retention time for the sample of FIG. 7 in which the same concentration of V or Nb is ion-implanted.

Referring to FIG. 17, as a result of retention measurement for the sample of FIG. 7 at room temperature, a sample in which the amount of V ion and Nb ion was 1x10 ¹⁴ was extended by 10 years. For samples injected with% and Nb ions, a charge loss of about 19% was measured. Thus, this is a good result compared to the sample of FIG. 6 and very good when compared to the results published in other materials / structures previously. In particular, V (10 ¹⁴ ) decreased by 26.1% and Nb (10 ¹⁴ ) by 19.3%.

1 is a graph illustrating the necessity of a charge trap flash memory semiconductor device such as a nanocrystal memory according to a technical problem of a polysilicon floating gate memory semiconductor device according to the related art.

2 is a view showing an example of a conventional charge trap flash memory semiconductor device.

3A to 3C are energy band diagrams and TEM graphs in a SANOS structure in a programming and erasing mode of a semiconductor device of a conventional SONOS and SANOS structure.

4A and 4B are diagrams illustrating a charge trap mechanism and an energy band by doped metal ions of a semiconductor device according to the present invention.

5A through 5C are diagrams sequentially illustrating a method of manufacturing a nonvolatile memory device using an impurity trap formed by metal doping as a charge storage level.

6 and 7 are diagrams schematically showing the metal ions implanted in the metal ion implantation process performed in the process of FIG. 5b according to the present invention and the resulting implantation energy.

8 to 10 are graphs showing memory characteristics according to respective metal ion implantations.

FIG. 11 is a graph showing the V ion profile depth for the sample of FIG. 7. FIG.

FIG. 12 is a STEM image showing a relationship between a structure and V ions of the sample of FIG. 7.

FIG. 13 is a graph showing the hysteresis width for the sample of FIG. 7.

FIG. 14 is a graph showing the relationship between programming / erase rate versus implanted ions for the sample of FIG. 6.

FIG. 15 is a graph showing the relationship between programming / erase rate versus implanted ions for the sample of FIG. 7.

FIG. 16 is a graph showing the relationship between the retention time versus the injected V ion concentration for the sample of FIG. 6.

17 is a graph showing the retention time for the sample of FIG. 7 in which the same concentration of V or Nb is ion-implanted.

Explanation of symbols on the main parts of the drawings

12: p-type silicon substrate

14: silicon oxide film

15: metal

16: alumina layer (Al ₂ 0 ₃ )

18: electrode layer

19: metal injection range

Claims (6)

p-type silicon substrate; A silicon oxide film deposited to a thickness of 5 nm formed on the p-type silicon substrate; An alumina layer (Al ₂ O ₃ ) deposited on the silicon oxide film by atomic layer deposition (ALD) at a thickness of 40 nm; And It comprises a; ion implantation layer made of one of the Nb, V, Ta, Ru metal ions implanted into the alumina layer through the ion implantation method on the alumina layer, The ion implantation layer acts as an impurity trap, and the metal is a nonvolatile memory device using an impurity trap formed by metal doping as a charge storage level, characterized in that formed in atomic units. Depositing a silicon oxide film to a thickness of 5 nm on the p-type silicon substrate by thermal deposition; Depositing an alumina layer (Al ₂ O ₃ ) to a thickness of 40 nm on the silicon oxide film by atomic layer deposition (ALD); And A third step of performing an ion implantation process through an ion implantation method using one of Nb, V, Ta, and Ru metal ions on the alumina layer; A method of manufacturing a nonvolatile memory device using an impurity trap formed by metal doping as a charge storage level, wherein an impurity trap made of metal is formed as a result of ion implantation in the third step, and the metal is formed in atomic units. The method of claim 2, further comprising a fourth step of rapidly heat-treating the memory device including the alumina layer implanted after the third step, wherein the fourth step is performed at about 800 ° C. in an N ₂ atmosphere. A method of manufacturing a nonvolatile memory device using an impurity trap formed by metal doping as a charge storage level, which is performed for a minute. The method of claim 2, wherein after the third step, performing a fifth step of depositing aluminum for use as an electrode, wherein the diameter of the aluminum electrode in the fifth step is 100 micrometers. A method of manufacturing a nonvolatile memory device using the impurity trap formed by the charge storage level. 3. The metal doping method of claim 2, wherein a depth of the metal layer formed by implanting the metal by a predetermined depth of the alumina layer as a result of the ion implantation is formed at a depth of 20 to 25 nm vertically downward from an upper surface of the alumina layer. A method of manufacturing a nonvolatile memory device using the impurity trap formed by the charge storage level. 3. The metal doping method of claim 2, wherein a depth of the metal layer formed by implanting the metal by a predetermined depth of the alumina layer as a result of the ion implantation is formed at a depth of 30 to 35 nm vertically downward from an upper surface of the alumina layer. A method of manufacturing a nonvolatile memory device using the impurity trap formed by the charge storage level.

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