KR100973281B1 - SONOS memory device and method of manufacturing the same - Google Patents

Abstract

A sonos memory device and a method of manufacturing the same are disclosed. The disclosed invention provides a sonos memory element comprising a semiconductor substrate and a multifunction element formed on the semiconductor substrate having both a switching function and a data storage function. Here, the multifunction device is formed by injecting a predetermined conductive impurity into the semiconductor substrate, the first and second impurity regions and the first and second impurity regions, which are spaced at predetermined intervals and have channels formed therebetween. And a data storage stack formed on the semiconductor substrate therebetween. In the data storage stack, a tunneling oxide layer, a memory node layer in which data is stored, a blocking layer, and an electrode layer are sequentially stacked.

Description

SONOS memory device and method of manufacturing the same

1 is a cross-sectional view of a Sonos memory device according to the prior art.

FIG. 2 is a graph illustrating a problem of a sonos memory device including an oxide / high k stack at its gate for low voltage operation, presented as an alternative to the sonos memory device shown in FIG.

3 is a cross-sectional view of a sonos memory device according to an exemplary embodiment of the present invention.

4 is a cross-sectional view illustrating a case in which a tunneling insulating layer is formed of a plurality of layers in the sonos memory device illustrated in FIG. 3.

FIG. 5 is a cross-sectional view illustrating a case in which a blocking layer is formed of multiple layers in the sonos memory device illustrated in FIG. 3.

6 to 8 are cross-sectional views illustrating a method of manufacturing the sonos memory device illustrated in FIG. 3 step by step.

FIG. 9 is a graph illustrating C-V characteristics of the sonos memory device illustrated in FIG. 3.

FIG. 10 is a graph showing a change in a flat band voltage according to a data writing time of an embodiment of the present invention annealed at 900 ° C. and a conventional technology.

FIG. 11 is a graph showing a change in the flat band voltage according to the data erasing time of the memory device according to the embodiment of the present invention and the prior art annealed at 900 ° C.

* Description of Signs of Major Parts of Drawings *

40: semiconductor substrate 42: first impurity region (source region)

44: second impurity region (drain region) 46: channel region

48, 52: first and second insulating films 50: material layer for memory node

48a, 48 ': first and second tunneling oxide films 50a: memory node layer

52a, 52a ': first and second blocking films 54a: electrode layer

54: conductive layer 62: photosensitive film pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a sonos memory device capable of improving thermal stability and a method of manufacturing the same.

The data storage capacity of the semiconductor memory device is proportional to the number of memory cells per unit area, that is, the degree of integration. BACKGROUND Semiconductor memory devices include many memory cells that are circuitry connected.

In the case of a semiconductor memory device, such as a DRAM, one memory cell is generally composed of one transistor and one capacitor. Therefore, in order to increase the density of semiconductor memory devices, the volume of transistors and / or capacitors should be reduced.

Early semiconductor memory devices with low integration had sufficient process margins in the photolithography and etching processes. Therefore, the method of reducing the volume of transistors and / or capacitors as described above may have a certain effect in increasing the degree of integration of semiconductor memory devices.

However, with the development of semiconductor technology and the related electronics industry, there is a need for a semiconductor memory device having a higher degree of integration, but the existing method is insufficient to meet this need.

Meanwhile, the degree of integration of a semiconductor memory device is closely related to a design rule applied to the manufacturing process. Therefore, in order to increase the degree of integration of semiconductor memory devices, more stringent design rules must be applied to the manufacturing process. This means that the process margins of the photolithography and etching processes are very low, that is, the photolithography and etching processes applied to the manufacture of semiconductor memory devices should be much more precise than before.

When the photo and etching process margins are low in the manufacturing process of the semiconductor memory device, the yield is also low. Therefore, there is a need to find a new way to increase the integration density of semiconductor memory devices while preventing yields.

Accordingly, a semiconductor memory device having a structure completely different from that of a conventional semiconductor memory device is introduced by including a data storage medium having a data storage function different from that of a conventional capacitor, such as GMR or TMR, above the transistor.

Sonos memory device is also one of the newly emerging semiconductor memory device, Figure 1 shows a cross-sectional view of the conventional Sonos memory device (hereinafter, a conventional memory device).

Referring to FIG. 1, in the conventional memory device, a source region 12 and a drain region 14 in which n-type conductive impurities are injected into a p-type semiconductor substrate 10 (hereinafter referred to as a semiconductor substrate) are set. The channel region 16 is set between the source and drain regions 12 and 14. The gate stack 30 is formed on the channel region 16 of the semiconductor substrate 10. The gate stack 30 is formed by sequentially stacking a tunneling oxide film 18, a nitride film (Si 3 N 4) 20, a blocking oxide film 22, and a gate electrode 24. The tunneling oxide film 18 is in contact with the source and drain regions 12 and 14. The nitride film 20 has trap sites of a predetermined density. Therefore, electrons passing through the tunneling oxide film 18 while the predetermined voltage is applied to the gate electrode 24 are trapped at the trap site of the nitride film 20.

The blocking oxide layer 22 is for blocking electrons from moving to the gate electrode 24 while the electrons are trapped.

Such a conventional memory device has a threshold voltage when electrons are trapped at the trap site of the nitride film 20 and when the electrons are not trapped. Conventional memory devices can use this property to store and read information.

However, the conventional Sonos memory device has a problem of not only having a long data erasing time but also a short time for maintaining the stored data normally, that is, a retention time.

In order to solve this problem, there has been proposed a Sonos memory device in which the nitride film 20, which is a trap layer, is replaced with an HfO2 film, which is an oxide film having a high dielectric constant, and the blocking oxide film 22, is replaced by an Al2O3 film.

As described above, when the nitride film 20 and the blocking oxide film 22 are replaced with the HfO 2 film and the Al 2 O 3 film, the above problems can be improved. However, while the crystallization temperature of the metal oxide film having a high dielectric constant is 700 ° C to 800 ° C, the temperature of a general MOS process, for example, to activate conductive impurities injected into the source and drain regions 12 and 14 is In view of the fact that it is 900 ° C. or more, even if the nitride film 20 and the blocking oxide film 22 are replaced with the metal oxide film having the high dielectric constant as described above, it is inevitable that the metal oxide film having the high dielectric constant is crystallized in the MOS process. .

Problems caused by crystallization of the metal oxide film having the high dielectric constant are as follows.

First, the surface roughness of the trap layer is increased, so that the effective distance between the metal oxide film used as the trap layer and the metal oxide film used as the blocking oxide film is not constant, and thus retention characteristics may be degraded. .

Second, the trap site density of the trap layer is highest when the trap layer is amorphous. By the way, when the trap layer is crystallized, the trap site density of the trap layer may be lowered, thereby degrading the characteristics of the trap layer as a memory node film.                         

Third, in the high temperature MOS process of 900 ° C. or higher, a material constituting the high dielectric constant metal oxide film used as the trap layer, such as HfO 2, and a material constituting the high dielectric metal oxide film used as the blocking oxide film, such as Al 2 O 3, are mixed. As a result, it is difficult to distinguish the boundary between the trap layer and the blocking oxide film.

Fourth, it is thermally unstable. This fact becomes clearer with reference to FIG. 2.

Specifically, in the C-V characteristic curve shown in FIG. 2, the first graph G1 shows the C-V characteristics immediately after sequentially forming an HfO 2 film and an Al 2 O 3 film on the tunneling oxide film SiO 2. The second graph G2 shows the C-V characteristics measured after sequentially forming an HfO 2 film and an Al 2 O 3 film on the tunneling oxide film SiO 2, and then annealing the resultant at 900 ° C. FIG. In other words, the first graph G1 shows the C-V characteristics before the HfO 2 film and the Al 2 O 3 film is crystallized, and the second graph G2 shows the C-V characteristics after the crystallization.

Comparing the first and second graphs G1 and G2, it can be seen that the C-V characteristics do not match before and after crystallization. In particular, it can be seen that the first graph G1 is severely distorted as the gate voltage Vg approaches 1V.

As such, the first and second graphs G1 and G2 do not coincide and are severely distorted because the thermal state before and after crystallization is unstable.

The technical problem to be achieved by the present invention is to improve the above-described problems of the prior art, so that the trap layer, the memory node layer can be maintained in an amorphous state in the high temperature MOS process while maintaining the retention characteristics normally To provide a device (SONOS memory device).

Another object of the present invention is to provide a method of manufacturing the sonos memory device.

In order to achieve the above technical problem, the present invention provides a sonos memory device characterized in that it comprises a semiconductor substrate and a multifunction device formed on the semiconductor substrate having both a switching function and a data storage function.

The multifunction device is formed by injecting a predetermined conductive impurity into the semiconductor substrate, and is disposed between the first and second impurity regions and the first and second impurity regions, which are spaced at predetermined intervals, and have channels formed therebetween. And a data storage stack formed on the semiconductor substrate.

In the data storage stack, a tunneling oxide layer, a memory node layer in which data is stored, a blocking layer, and an electrode layer are sequentially stacked.

The tunneling oxide film is a single layer or a multilayer.

The blocking film is a single layer or a multilayer.

The memory node layer is a MON layer or an MSiON layer. In the MON and MSiON "M" represents a metallic material.

"M" is Hf, Zr, Ta, Ti, Al, or lanthanum series element (Ln). The lanthanum-based element (Ln) is La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu.                     

In order to achieve the above another technical problem, the present invention provides a method for manufacturing a sonos memory device having a semiconductor transistor and a memory transistor having a gate stack capable of storing data on the semiconductor substrate, the gate stack silver

A first step of sequentially forming a first tunneling oxide film, a metal oxynitride layer in which data is stored, a first blocking film, and a conductive layer on the semiconductor substrate, a second step of forming a mask on a predetermined region of the conductive layer, And a third step of sequentially etching the conductive layer, the first blocking layer, the metal oxynitride layer, and the first tunneling oxide layer around the mask and the fourth step of removing the mask. It provides a method of manufacturing.

In the first step, a second tunneling oxide film is further formed between the first tunneling oxide film and the metal oxynitride layer, and a second blocking film is further formed between the first blocking film and the conductive layer.

The metal oxynitride layer is formed using ALCVD, CVD, LPCVD, PECVD, reactive sputtering.

The metal oxynitride layer is formed of a MON film or an MSiON film (M is a metal material). In this case, the MON film and the MSiON film may be formed by first forming the MO film and the MSiO film, and then nitriding the resultant. In addition, the MON film and the MSiON film may be formed by first forming an MN film and an MSiN film, respectively, and then oxidizing the resultant.

The MO film or the MSiO film is nitrided so that the nitrogen content is 1% to 80%.

Using the Sonos memory element of the present invention, the data writing time and the data erasing time can be made much shorter than the conventional Sonos memory element. Therefore, the data processing speed can be much higher than before. After the MOS process, the memory node layer can remain in an amorphous state. Therefore, the conventional problems due to the crystallization of the memory node layer, for example, the problem of decreasing the trap site density of the memory node layer, the problem of deterioration of retention characteristics due to the increase of surface roughness, the material and the barrier film forming the memory node layer It is possible to improve the problem of mixing the materials constituting the. In addition, thermal stability can be secured.

Hereinafter, a sonos memory device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity.

First, the sonos memory element will be described.

Referring to FIG. 3, a sonos memory device according to an embodiment of the present invention has first and second impurity regions 42 and 44 on a substrate 40, for example, a p-type semiconductor substrate. The first and second impurity regions 42 and 44 are formed by ion implanting a predetermined conductive impurity, for example, an n-type conductive impurity to a predetermined depth. The first and second impurity regions 42 and 44 are spaced at predetermined intervals, and a channel region 46 in which predetermined conductive impurities are injected is formed between the two regions 42 and 44. The channel region 46 is formed from the first impurity region 42 to the second impurity region 44.

Hereinafter, the first and second impurity regions 42 and 44 are referred to as source and drain regions, respectively.                     

A data storage gate stack 60 (hereinafter referred to as a gate stack) is formed on the semiconductor substrate 40, that is, the channel region 46, between the source and drain regions 42 and 44. The gate stack 60 is formed by sequentially stacking a tunneling oxide film 48a, a memory node layer 50a, a blocking film 52a, and an electrode layer 54a. The tunneling oxide film 48a is in contact with the front surface of the channel region 46 and the edge is in contact with the source and drain regions 42 and 44. The tunneling oxide film 48a is preferably a silicon oxide film (SiO 2) of 1.5 nm to 4 nm, but may be another insulating film.

Electrons that pass through the tunneling oxide film 48a by applying a proper voltage to the electrode layer 54a are trapped in the memory node layer 50a. The case where the electrons are trapped in the memory node layer 50a and the case where the electrons are not trapped may correspond to the case where data 1 is stored and the case where 0 is stored, respectively. Since the memory node layer 50a is included in the gate stack 60, the gate stack 60 may be referred to as a data storage type.

As described above, since the memory node layer 50a is used as a trap layer in which electrons are trapped, the trap site density of the memory node layer 50a is preferably as high as possible. In this aspect, the memory node layer 50a is preferably not crystallized in a high temperature MOS process of 900 ° C or higher. In view of this, it is preferable that the memory node layer 50a is a MON layer or MSiON layer having a high content of nitrogen (N). The MON layer and the MSiON layer are both amorphous, and the nitrogen (N) content is about 1% to 80%. In the MON layer and the MSiON layer, "M" is a metal material and is Hf, Zr, Ta, Ti, Al, or lanthanum-based element (Ln). The lanthanum-based element (Ln) is La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu. The blocking film 52a is for preventing carriers, in particular, electrons trapped in the memory node layer 50a from moving between the memory node layer 50a and the electrode layer 54a to the electrode layer 54a. The blocking film 52a is an insulating film having a high dielectric constant, for example, an alumina (Al 2 O 3) film or a silicon oxide film (SiO 2). The electrode layer 54a is used as a gate electrode and is a polysilicon layer doped with conductive impurities. The electrode layer 54a may be another conductive layer, such as a tungsten silicide layer.

Meanwhile, the channel region 46 between the source and drain regions 42 and 44 is turned on or turned off depending on the magnitude of the voltage applied to the electrode layer 54a of the gate stack 60. do. In other words, by applying an appropriate voltage to the electrode layer 54a, the state of the channel region 46 can be switched. Thus, the source and drain regions 42 and 44 and the gate stack 60 become devices (eg transistors) with a switching function. In addition, since the gate stack 60 includes the memory node layer 50a capable of storing data as described above, the device having the switching function may be regarded as having a data storage function. As a result, the device including the source and drain regions 42 and 44 and the gate stack 60 becomes a multifunctional device having a switching function and a data storage function. The multifunction device may be referred to as a transistor in view of its configuration. However, the multifunction device may be referred to as a data storage type or a memory type transistor because it has a switching function as well as a data storage function as described above.

4, a second tunneling oxide film 48a ′ may be further provided between the first tunneling oxide film 48a and the memory node layer 50a. In this case, the first tunneling oxide film 48a is preferably a silicon oxide film having a thickness of about 0.5 nm to 1 nm, and the second tunneling oxide film 48a 'is preferably an alumina film having a thickness of about 2 nm to 5 nm.

In FIG. 4, reference numeral 60 ′ denotes a first gate stack including a multilayer tunneling oxide film as described above.

On the other hand, as shown in FIG. 5, the second blocking film 52a ′ may be further provided between the first blocking film 52a and the electrode layer 54a in the sonos memory device shown in FIG. 3. In other words, a plurality of blocking layers may be provided between the memory node layer 50a and the electrode layer 54a. In this case, the first blocking film 52a is preferably an alumina film having a thickness of about 2 nm to 4 nm, and the second blocking film 52a 'is preferably an insulating film having a high dielectric constant having a thickness of 3 nm to 30 nm. The high dielectric constant insulating film may be a hafnium oxide film (HfO 2), a zirconium oxide film (ZrO 2), a tantalum oxide film (Ta 2 O 5), or a titanium oxide film (TiO 2).

Although not illustrated in the drawings, there may be a sonos memory device including both the cases illustrated in FIGS. 4 and 5.

Referring to the operation of the sonos memory device shown in FIG. 3, 4, or 5, a predetermined gate voltage Vg is applied to the gate stack 60 through the electrode layer 54a, and the drain region 44 is applied to the gate stack 60. A predetermined drain voltage Vd is applied to the memory node layer 50a to store data. The stored data applies a predetermined gate voltage (Vg '<Vg) to the gate stack 60, applies a predetermined drain voltage (Vd' <Vd) to the drain region 44, and then the source and drain regions ( Determine the magnitude of the current value flowing between 42 and 44) and read it.

Next, the method of manufacturing the above-described Sonos memory element will be described.                     

First, referring to FIG. 6, a first insulating film 48, a material layer 50 for a memory node, a second insulating film 52, and a conductive layer are formed on a semiconductor substrate 40 doped with a predetermined impurity, such as a p-type impurity. Layer 54 is formed sequentially. Subsequently, a photoresist pattern 62 is formed on a predetermined region of the conductive layer 54 to define a region where the gate stack is to be formed. The first insulating film 48 may be formed in a single layer or a plurality of layers. In the former case, the first insulating film 48 is formed of a silicon oxide film, but the thickness thereof is formed to be about 1.5 nm to 4 nm. In the latter case, a silicon oxide film may be formed first with a thickness of about 0.5 nm to 1 nm, and then an alumina film may be formed with a thickness of about 2 nm to 5 nm on the silicon oxide film. In this manner, the first insulating film 48 formed of a single layer or a plurality of layers is used as the tunneling oxide film. The memory node material layer 50 is formed of a MON layer or an MSiON layer having a predetermined thickness. In the MON layer and the MSiON layer, "M" represents a metal material. "M" is Hf, Zr, Ta, Ti, Al, or lanthanum series element (Ln). The lanthanum-based element (Ln) is La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu.

When the material layer 50 for the memory node is formed of the MON layer or the MSiON layer, three methods may be used.

The first method is to form the MON layer or the MSiON layer on the first insulating film 48 in one step.

The second method is to first form an MO film or an MSiO film on the first insulating film 48, and then nitride the MO film or the MSiO film.

Third, an MN film or an MsiN film is first formed on the first insulating film 48, and then the water is oxidized.

In the first method, the MON layer or the MSiON layer is formed using atomic layer chemical vapor deposition (ALCVD), CVD, low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), or reactive sputtering. However, it can also form using other apparatuses.

In the second method, nitriding of the MO film or MSiO film is performed by plasma treatment in an atmosphere of nitrogen (N 2) or ammonium (NH 3), rapid thermal treatment (RTA) in an ammonium atmosphere, and furnace of ammonium atmosphere. It can be carried out using a method of treating in, a method of ion implanting nitrogen (N). In this case, when using the RTA or using a furnace (furnace), the process temperature is preferably 200 ℃ to 1,300 ℃.

In the third method, the oxidation may be performed using a furnace in an oxygen atmosphere at 100 ° C. to 1,300 ° C. or using RTA in an oxygen atmosphere. At this time, the gas for the oxygen atmosphere uses oxygen (O2), water vapor (H20) ozone (O3) or nitrogen oxide (N2O).

Thus, when forming the said MON layer or MSiON layer, it is preferable to make nitrogen (N) content into about 1%-about 80%.

On the other hand, when the inventors formed the MON layer or the MSiON layer by the second method through an experiment, the amount of nitrogen flowing into the MON layer or the MSiON layer varies according to the process conditions (temperature), and as a result, the sonos memory It can be seen that the hysteresis characteristics of the device are different.

The present inventors formed the MON layer among the MON layer and the MSiON layer by the second method in the above experiment, and used an RTA process of a nitrogen atmosphere, that is, a Rapid Thermal Nitridation (RTN) process.

Table 1 below shows the experimental results of the present invention.

Process conditions  Hysteresis (mV) RTN 700 ℃  75 RTN 800 ℃  120 RTN 900 ℃  150

Referring to Table 1, it can be seen that hysteresis increases as the process temperature increases, which is due to the increase in the trap site density of the MON layer due to more nitrogen flowing into the MON layer as the process temperature increases.

Through this, when forming the MON layer, by adjusting the process temperature, it can be seen that the amount of nitrogen flowing into the MON layer can be adjusted, and as a result, it is possible to effectively control the thermal stability and trap site density of the MON layer.

Next, the second insulating film 52 can be formed in a single layer or a multilayer like the first insulating film 48. In the former case, the second insulating film 52 is formed of an alumina film or a silicon oxide film. An alumina film is first formed, and then a high dielectric constant insulating film is formed thereon with a thickness of about 3 nm to 20 nm. The high dielectric constant insulating film is formed of a hafnium oxide film (HfO 2), a zirconium oxide film (ZrO 2), a tantalum oxide film (Ta 2 O 5), a titanium oxide film (TiO 2), or the like. The conductive layer 54 is formed of a polysilicon layer doped with conductive impurities or from another conductive material layer, such as a tungsten silicide layer.

Subsequently, referring to FIG. 7, using the photoresist pattern 62 as an etching mask, the stacks formed on the semiconductor substrate 40 are sequentially etched until the semiconductor substrate 40 is exposed in reverse order. As a result, the gate stack 60 including the first tunneling oxide film 48a, the memory node layer 50a, the first blocking film 52a, and the electrode layer 54a is formed on the predetermined region of the semiconductor substrate 40. . The first tunneling oxide layer 48a, the memory node layer 50a, the first blocking layer 52a, and the electrode layer 54a may be formed of the first insulating layer 48, the material layer 50 for the memory node 50, and the second insulating layer 52, respectively. And the result of patterning the conductive layer 54. After the etching, the photoresist pattern 62 is removed.

Referring to FIG. 8, ion-conductive impurities of a type opposite to impurity implanted into the semiconductor substrate 40, for example, impurities implanted into the semiconductor substrate 40 using the gate stack 60 as a mask, are ionized at a predetermined depth. Inject. In this way, first and second impurity regions 42 and 44, that is, source and drain regions, are formed in the semiconductor substrate 40 around the gate stack 60.

Thereafter, a high temperature heat treatment process for activating conductive impurities in the source and drain regions 42 and 44 is performed.

On the other hand, the present inventors, after the heat treatment, through the TEM photograph analysis of the MO layer and the MON layer, it was found that the crystallization of the MO layer, while in the case of the MON layer, the amorphous state was maintained as it is.

In addition, in the surface roughness analysis using AFM (Atomic Force Microscope), the MO layer has a surface roughness of about 5.3 GPa, whereas the surface roughness of the MON layer is about 2.3 GPa, and the surface roughness of the MON layer is much smaller. Could know.

The present inventors also conducted an experiment (hereinafter referred to as a first experiment) for verifying the thermal stability of the sonos memory device according to the embodiment of the present invention described above.

The thermal stability of the Sonos memory device according to the embodiment of the present invention is directly connected to the thermal stability of the stack including the first insulating layer 48, the material layer 50 for the memory node, and the second insulating layer 52.

Accordingly, the inventor formed the first insulating film 48 with the silicon oxide film SiO 2 in the manufacturing process shown in FIG. 6. The memory layer material layer 50, that is, the MON layer, was formed as an HfON layer. In addition, the second insulating film 52 was formed of an aluminum oxide film (Al 2 O 3).

The inventor then formed a gate stack 60 as shown in FIG. As shown in FIG. 7, before the source and drain regions 42 and 44 are formed in the substrate 40, the gate stack 60 is formed by applying a gate voltage Vg to the electrode layer 54a. The CV characteristic with respect to was measured (following 1st measurement).

Subsequently, the present inventors anneal the resultant in which the gate stack 60 is formed after the first measurement to about 900 ° C., and then apply the gate voltage Vg to the electrode layer 54a to apply the gate stack 60. The CV characteristic was measured (hereinafter, 2nd measurement) with respect to the resultant which formed.

On the other hand, the inventor performed the annealing of the gate stack 60 for the second measurement through the process of forming the source and drain regions 42 and 44 in the substrate 40 as shown in FIG. Could have done.

9 shows the results for the first and second measurements.

In FIG. 9, reference numeral G3 denotes a first graph showing the result of the first measurement, and G4 denotes a second graph showing the result of the second measurement.

Comparing the third and fourth graphs G3 and G4, the first and second graphs G1 and G2 illustrated in FIG. 2, which show the CV characteristics of the Sonos memory device according to the related art, do not coincide with each other. In contrast, it can be seen that the third and fourth graphs G3 and G4 correspond exactly.

Exactly matching the third and fourth graphs G3 and G4 means that in the case of the Sonos memory device according to the embodiment of the present invention, the passion stability is the same regardless of the annealing, unlike the conventional art.

Next, the present inventors conducted an experiment (hereinafter referred to as a second experiment) to determine a change in the flat band voltage according to a programming time and a change in the flat band voltage according to an erasing time.

In the second experiment, the inventors of the present invention show a first tunneling oxide film 48a, a memory node layer 50a, and a first of a sonos memory device (hereinafter referred to as a first memory device) according to an embodiment of the present invention shown in FIG. The blocking film 52a was formed of an SiO 2 film, an HfON film, and an Al 2 O 3 film, respectively. In addition, a conventional sonos formed by forming a first tunneling oxide film 48a, a memory node layer 50a, and a first blocking film 52a as an SiO 2 film, an HfO 2 film, and an Al 2 O 3 film, respectively, for comparison with the first memory device. A memory element (hereinafter referred to as a second memory element) was prepared. In the process of preparing the first and second memory devices, the resultant including the first tunneling oxide layer 48a, the memory node layer 50a, and the first blocking layer 52a is annealed to about 900 ° C. FIG.

After preparing the first and second memory devices as described above, the present inventors measured a change in the flat band voltage according to the data writing time for the first and second memory devices (hereinafter, referred to as a third measurement). In the third measurement, a write voltage and an erase voltage of about 10V were applied.

10 shows the third measurement result.

In FIG. 10, reference numeral G5 is a fifth graph showing the third measurement result for the second memory device. Reference numeral G6 denotes a sixth graph showing the third measurement result for the first memory device.
Comparing the fifth and sixth graphs G5 and G6, it can be seen that the change in the flat band voltage Vfb or the flat band shift with the recording time is much larger in the sixth graph G6.

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The large increase in the flat band voltage or the flat band movement even though the change in the recording time is very small means that the data can be sufficiently recorded during the change in the recording time. Therefore, in the case of the first memory device, the data writing time can be much shorter than that of the second memory device.

Subsequently, the present inventors also measured the change of the flat band voltage according to the erase time (hereinafter referred to as fourth measurement) for the first and second memory elements prepared as described above.

11 shows the results for the fourth measurement.
In FIG. 11, reference numeral G8 is an eighth graph showing the fourth measurement result with respect to the first memory device. Reference numeral G7 is a seventh graph showing the fourth measurement result with respect to the second memory device.
Comparing the seventh and eighth graphs G7 and G8, it can be seen that the change of the flat band voltage according to the erase time is much larger in the eighth graph G8. In other words, in the eighth graph G8, as the erase time increases, the degree of decrease of the flat band voltage is much larger than that of the seventh graph G7.

This result means that the erase time of the memory device to which the eighth graph G8 is applied is much shorter than the erase time of the memory device to which the seventh graph G7 is applied. The erase time of the second memory device may be much shorter.

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While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, one of ordinary skill in the art may have a relationship between the first tunneling oxide layer 48a and the memory node layer 50a and / or between the memory node layer 50a and the first blocking layer 52a. It may further comprise a heterogeneous different memory node layer. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

As described above, the sonos memory device according to the embodiment of the present invention includes a MON layer or an MSiON layer having a high dielectric constant as a memory node layer. As a result, the memory node layer may remain in an amorphous state even in a high temperature MOS process. Therefore, when the Sonos memory device according to the embodiment of the present invention is used, thermal stability can be ensured as shown in FIG. 9. As can be seen from the change of the flat band voltage according to the data writing and erasing time shown in Figs. 10 and 11, the data writing time and the data erasing time can be shortened, which makes the data processing speed much higher than before. In addition, retention characteristics can be maintained normally. In addition, it is possible to increase the trap site density of the memory node layer as compared to the conventional method, and the retention property is reduced with increasing surface roughness, and the material constituting the memory node layer and the material constituting the barrier layer are mixed with each other by external diffusion. Can be prevented.

Claims (30)

Semiconductor substrates; And A multifunction device formed on the semiconductor substrate and having both a switching function and a data storage function; First and second impurity regions in which predetermined conductive impurities are injected into the semiconductor substrate, spaced at predetermined intervals, and channels are formed between the first and second impurity regions; And A data storage stack formed on the semiconductor substrate between the first and second impurity regions, wherein the data storage stack, A first tunneling oxide layer, a memory node layer in which data is stored, a first blocking layer, and an electrode layer are sequentially stacked, and the memory node layer is a MON layer or an MSiON layer (M is a metal material) device. delete delete The sonos memory device of claim 1, wherein a second tunneling oxide layer is provided between the first tunneling oxide layer and the memory node layer. The sonos memory device of claim 1, further comprising a second blocking layer between the first blocking layer and the electrode layer. delete The sonos memory device of claim 1, wherein the first tunneling oxide layer is a silicon oxide layer. 5. The sonos memory device of claim 4, wherein the second tunneling oxide film is an alumina (Al2O3) film. The sonos memory device of claim 1, wherein the first blocking layer is an alumina layer or a silicon oxide layer. The sonos memory device of claim 5, wherein the second blocking layer is an HfO ₂ , ZrO ₂ , Ta ₂ O _5, or TiO ₂ layer. The method of claim 1, wherein M is Hf, Zr, Ta, Ti, Al or lanthanum-based element (Ln), the lanthanum-based element (Ln) is La, Ce, Pr, Nd, Sm, Eu, Gd, Tb , Dy, Ho, Er, Tm, Yb or Lu. The Sonos memory device according to claim 1, wherein the nitrogen content of the MON layer or the MSiON layer is 1% to 80%. A method of manufacturing a sonos memory device comprising a semiconductor substrate and a memory transistor including a gate stack capable of storing data on the semiconductor substrate. The gate stack is A first step of sequentially forming a first tunneling oxide film, a metal oxynitride layer in which data is stored, a first blocking film, and a conductive layer on the semiconductor substrate; Forming a mask on a predetermined region of the conductive layer; A third step of sequentially etching the conductive layer, the first blocking layer, the metal oxynitride layer, and the first tunneling oxide layer around the mask; And And a fourth step of removing the mask. Claim 14 was abandoned when the registration fee was paid. 15. The method of claim 13, wherein in the first step, a second tunneling oxide film is further formed between the first tunneling oxide film and the metal oxynitride layer. Claim 15 was abandoned upon payment of a registration fee. The method of claim 13, wherein a second blocking layer is further formed between the first blocking layer and the conductive layer in the first step. Claim 16 was abandoned upon payment of a setup registration fee. 15. The method of claim 13, wherein the first tunneling oxide film is formed of a silicon oxide film. Claim 17 has been abandoned due to the setting registration fee. 15. The method of claim 14, wherein the second tunneling oxide film is formed of an Al ₂ O ₃ film. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 13, wherein the first blocking layer is formed of an Al ₂ O ₃ film or an SiO ₂ film. Claim 19 was abandoned upon payment of a registration fee. The method of claim 15, wherein the second blocking layer is formed of an HfO ₂ , ZrO ₂ , Ta ₂ O _5, or TiO ₂ film. Claim 20 was abandoned upon payment of a registration fee. The method of claim 13, wherein the metal oxynitride layer is formed using ALCVD, CVD, LPCVD, PECVD, or reactive sputtering. 15. The method of claim 13, wherein the metal oxynitride layer is formed of a MON film or an MSiON film (M is a metal material). 22. The method of claim 21, wherein the MON film and the MSiON film are formed by first forming an MO film and an MSiO film, and then nitriding the resultant. Claim 23 was abandoned upon payment of a set-up fee. 23. The method of claim 22, wherein the MO film and the MSiO film are nitrided and then the resultant is oxidized. Claim 24 is abandoned in setting registration fee. The method of claim 22, wherein the MO film and the MSiO film, Plasma treatment in nitrogen (N2) or ammonium (NH3) atmosphere, rapid thermal treatment (RTA) in ammonium atmosphere, furnace treatment in ammonium atmosphere, or ion implantation of nitrogen (N) A method of manufacturing a sonos memory element, characterized in that the nitriding. Claim 25 is abandoned in setting registration fee. 25. The method of claim 24, wherein in the case of using the RTA or the furnace, the process temperature is 200 ° C to 1,300 ° C. Claim 26 is abandoned in setting registration fee. 24. The method of claim 23, wherein the oxidation is performed at 100 ° C to 1,300 ° C by using a furnace in an oxygen atmosphere or by using an RTA in an oxygen atmosphere. Claim 27 was abandoned upon payment of a registration fee. 27. The method of claim 26, wherein oxygen (O 2), water vapor (H 20), or nitrogen oxide (N 2 O) is used as a gas for the oxygen atmosphere. 23. The method of claim 22, wherein the MO film or the MSiO film is nitrided so that the nitrogen content is 1% to 80%. The method of claim 21, wherein M is Hf, Zr, Ta, Ti, Al or lanthanum-based elements (Ln), the lanthanum-based elements (Ln) is La, Ce, Pr, Nd, Sm, Eu, Gd, Tb , Dy, Ho, Er, Tm, Yb or Lu. 22. The method of claim 21, wherein the MON film and the MSiON film are formed by first forming an MN film and an MsiN film, and then oxidizing the resultant.

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