KR100971209B1 - Method for fabricating of CMOS Image sensor - Google Patents

Abstract

The present invention relates to a CMOS image sensor, and more particularly, to a method for manufacturing a CMOS image sensor that can reduce the loss of light,

A method of manufacturing a CMOS image sensor according to the present invention includes forming a gate insulating film and a gate electrode on a portion of a semiconductor substrate on which a first epitaxial layer is formed; Forming and planarizing an interlayer insulating film over the semiconductor substrate including the gate insulating film and the gate electrode; Etching the interlayer insulating film to expose a portion of the first epitaxial layer adjacent to the gate electrode and growing the exposed first epitaxial region to form a second epitaxial layer; Removing the interlayer insulating film and forming a photoresist on the gate electrode while exposing the second epitaxial layer; And implanting ion into the first and second epitaxial layers using the photoresist as a mask to form first and second conductivity type diffusion regions for the photodiode.

Epi layer, ion implantation

Description

Method for fabricating CMOS image sensor

The present invention relates to a CMOS image sensor, and more particularly, to a method for manufacturing a CMOS image sensor that can reduce the loss of light.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and is generally classified into a charge coupled device (CCD) and a CMOS image sensor. A charge coupled device (CCD) has a structure in which MOS capacitors are disposed adjacent to each other, and a charge carrier is stored in an arbitrary MOS capacitor and then transferred to a later MOS capacitor. . The charge coupling device has disadvantages such as a complicated driving method, a large power consumption, and a complicated manufacturing process due to many photoprocess steps. In addition, the charge coupling device has a disadvantage in that it is difficult to integrate a control circuit, a signal processing circuit, an analog-to-digital conversion circuit (A / D converter), and the like into a charge coupling device chip, which makes it difficult to miniaturize a product.

Recently, CMOS image sensors have attracted attention as next-generation image sensors to overcome the disadvantages of charge-coupled devices. The CMOS image sensor uses CMOS technology that uses a control circuit and a signal processing circuit as a peripheral circuit to form MOS transistors corresponding to the number of unit pixels on a semiconductor substrate, thereby outputting each unit pixel by the MOS transistors. It is a device that employs a switching method that detects sequentially. That is, the CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel. CMOS image sensor has advantages such as low power consumption, simple manufacturing process according to few photo process steps because of CMOS technology. In addition, since the CMOS image sensor can integrate a control circuit, a signal processing circuit, an analog / digital conversion circuit, and the like into the CMOS image sensor chip, the CMOS image sensor has an advantage of easy miniaturization. Therefore, the CMOS image sensor is currently widely used in various application parts such as a digital still camera, a digital video camera, and the like.

Hereinafter, a CMOS image sensor will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a conventional CMOS image sensor.

As shown in FIG. 1, a P-type epitaxial layer 11 is formed on a P ++ type semiconductor substrate 10. In order to define an active region of the semiconductor substrate 10, a device isolation layer 13 is formed in a portion of the epi layer 11 for the device isolation region of the semiconductor substrate 10. The gate insulating film 14 and the gate electrode 15 are formed on the portion of the epi layer 11 for the transistor, and the spacer 17 of the insulating film is formed on both sidewalls of the gate electrode 15. An n-type diffusion region 18 and a Po-type diffusion region 19 of the photodiode PD are formed in the portion of the epi layer 11 for the photodiode region of the active region. Po-type diffusion region 19 is formed on n-type diffusion region 18. In addition, the floating diffusion region FD is formed in the epi layer 11 and spaced apart from the n- / Po type diffusion regions 18 and 19 with the gate electrode 15 of the transistor interposed therebetween.

However, since the conventional CMOS image sensor forms a photodiode and then forms a plurality of metal wiring layers, much light loss occurs due to scattering while light passes through the microlenses and reaches the photodiode. Due to the light loss, there is a problem in that the number of electrons generated by light is reduced, thereby degrading the performance of the CMOS image sensor.

Accordingly, in order to solve the above problems, an object of the present invention is to provide a method for manufacturing CMOS image sensor that can reduce the loss of light.

A method of manufacturing a CMOS image sensor according to the present invention includes forming a gate insulating film and a gate electrode on a portion of a semiconductor substrate on which a first epitaxial layer is formed; Forming and planarizing an interlayer insulating film over the semiconductor substrate including the gate insulating film and the gate electrode; Etching the interlayer insulating film to expose a portion of the first epitaxial layer adjacent to the gate electrode and growing the exposed first epitaxial region to form a second epitaxial layer; Removing the interlayer insulating film and forming a photoresist on the gate electrode while exposing the second epitaxial layer; And implanting ion into the first and second epitaxial layers using the photoresist as a mask to form first and second conductivity type diffusion regions for the photodiode.

As described above, in the method of manufacturing the CMOS image sensor according to the present invention, light loss may be reduced by growing a selective epitaxial layer in the region where the photodiode is to be formed, thereby narrowing the distance between the microlens and the photodiode.

Hereinafter, a manufacturing method of the CMOS image sensor according to the present invention will be described with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a manufacturing process of the CMOS image sensor according to the present invention.

First, as shown in FIG. 2A, a low-concentration first conductivity type, eg, P-type epi, grown by an epitaxial process on a surface for forming an element of the P ++ type semiconductor substrate 100. Layer 110 is formed. This is to increase the ability of low voltage photodiodes to collect photocharges and further improve light sensitivity by forming large and deep depletion regions in the photodiodes.

Subsequently, an isolation layer (not shown) is formed on the portion of the epi layer 110 for the isolation region of the semiconductor substrate 100 by an STI process to define the active region. Of course, it is also possible to form the device isolation film by a LOCOS process or the like. Next, the gate insulating film 120 and the gate electrode 130 are formed to a desired thickness on the epi layer 110 of the entire active region including the active region of the photodiode PD.

Next, the surface of the active region for the photodiode and the floating diffusion region is exposed by leaving the gate insulating layer 120 and the gate electrode 130 for the transistor and removing the remaining portion by using a photolithography process. Thereafter, TEOS is deposited on the entire surface of the semiconductor substrate 100 including the gate insulating layer 120 and the gate electrode 130 to form the interlayer insulating layer 140.

Then, as shown in FIG. 2B, a first photoresist (not shown) is deposited on the interlayer insulating film 140, and the photodiode is formed by exposure and development, that is, for a photodiode to be described in a process to be described later. The interlayer insulating layer 140 of the region where the first and second conductivity type diffusion regions are to be formed is exposed. Then, the interlayer insulating layer 140 exposed using the first photoresist as a mask is etched using a predetermined etching process to expose the epi layer 110 of the semiconductor substrate 100, and the exposed epi layer 110 is exposed. Is grown by injecting gas. At this time, the grown epitaxial layer 110 is preferably grown to a thickness of 1500 ~ 2500Å.

After that, as shown in FIG. 2C, the interlayer insulating layer 140 is removed by wet etching, and the semiconductor substrate including the gate insulating layer 120, the gate electrode 130, and the grown epitaxial layer 110 is formed. 100) deposit the second photoresist 150 on the entire surface. Then, the deposited second photoresist 150 is exposed and developed to expose the region where the photodiode is to be formed, that is, the region where the first and second conductivity type diffusion regions for the photodiode to be described later will be formed.

Next, as illustrated in FIG. 2D, ion implantation for forming a photodiode is performed using the second photoresist 150 as a mask. In this case, ion implantation is performed at an angle of 15 to 25 degrees so that ion implantation for forming the first and second conductivity type diffusion regions 180 and 190 of the photodiode may also be implanted into the sidewall of the grown epitaxial layer 110. The implantation energy and implantation conditions follow known ion implantation conditions. Here, the first conductivity type diffusion region 180 is a Po type diffusion region, the second conductivity type diffusion region 190 is an n-type diffusion region, and the first conductivity type diffusion region 180 is a second conductivity type diffusion region. It is formed on the region 190.

Thereafter, the CMOS image sensor is completed through a well-known subsequent process such as forming a spacer.

Therefore, the method of manufacturing the CMOS image sensor according to the present invention can reduce the loss of light by narrowing the distance between the microlens and the photodiode by selectively growing an epitaxial layer in the region where the photodiode is to be formed.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a cross-sectional view showing a conventional CMOS image sensor.

2A to 2D are cross-sectional views illustrating a manufacturing process of the CMOS image sensor according to the present invention.

Claims (8)

Forming a gate insulating film and a gate electrode on a portion of the semiconductor substrate on which the first epitaxial layer is formed; Forming and planarizing an interlayer insulating film over the semiconductor substrate including the gate insulating film and the gate electrode; Etching the interlayer insulating layer to expose a portion of the first epitaxial layer adjacent to the gate electrode and growing the exposed first epitaxial region to form a second epitaxial layer; Removing the interlayer insulating film and forming a photoresist on the gate electrode while exposing the second epitaxial layer; And implanting the first and second epitaxial layers into the first and second epitaxial layers using the photoresist as a mask to form first and second conductivity type diffusion regions for the photodiode. Way. The method of claim 1, And the photoresist is formed on the semiconductor substrate except for regions where the first and second conductivity type diffusion regions are to be formed. The method of claim 1, The interlayer insulating film is a method of manufacturing a CMOS image sensor, characterized in that for etching the region where the first and second conductivity type diffusion region is to be formed. The method of claim 1, The interlayer insulating film is a method of manufacturing a CMOS image sensor, characterized in that formed by TEOS. The method of claim 1, The ion implantation method of the CMOS image sensor, characterized in that the implant at an angle of 15 to 25 degrees. The method of claim 1, And the second epitaxial layer is ion implanted into the sidewall. The method of claim 1, And the first conductivity type diffusion region is formed on the second conductivity type diffusion region. The method of claim 1, And the first conductivity type diffusion region is a Po type diffusion region, and the second conductivity type diffusion region is an n-type diffusion region.

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