KR100955722B1 - 사이클당 복수의 액세스를 지원하는 캐시 메모리를 구비한마이크로프로세서 - Google Patents

사이클당 복수의 액세스를 지원하는 캐시 메모리를 구비한마이크로프로세서 Download PDF

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KR100955722B1
KR100955722B1 KR1020057009466A KR20057009466A KR100955722B1 KR 100955722 B1 KR100955722 B1 KR 100955722B1 KR 1020057009466 A KR1020057009466 A KR 1020057009466A KR 20057009466 A KR20057009466 A KR 20057009466A KR 100955722 B1 KR100955722 B1 KR 100955722B1
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KR20050085150A (ko
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미첼 앨서프
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020057009466A 2002-11-26 2003-11-06 사이클당 복수의 액세스를 지원하는 캐시 메모리를 구비한마이크로프로세서 Expired - Fee Related KR100955722B1 (ko)

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US10/304,605 US7073026B2 (en) 2002-11-26 2002-11-26 Microprocessor including cache memory supporting multiple accesses per cycle
US10/304,605 2002-11-26

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KR20050085150A KR20050085150A (ko) 2005-08-29
KR100955722B1 true KR100955722B1 (ko) 2010-05-03

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US (1) US7073026B2 (enExample)
EP (1) EP1565827B1 (enExample)
JP (1) JP4425798B2 (enExample)
KR (1) KR100955722B1 (enExample)
CN (1) CN1717664B (enExample)
AU (1) AU2003287522A1 (enExample)
TW (1) TWI307476B (enExample)
WO (1) WO2004049171A2 (enExample)

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US8347034B1 (en) * 2005-01-13 2013-01-01 Marvell International Ltd. Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access
KR20070105779A (ko) * 2006-04-27 2007-10-31 엠텍비젼 주식회사 프로세스 기능을 갖는 메모리 장치 및 그 프로세스 방법
KR100782594B1 (ko) * 2006-07-14 2007-12-06 엠텍비젼 주식회사 데이터 처리 기능을 구비한 메모리 장치
US8909872B1 (en) 2006-10-31 2014-12-09 Hewlett-Packard Development Company, L. P. Computer system with coherent interconnection
CN101212488B (zh) * 2006-12-26 2011-08-24 梁国恩 双通道的网络储存管理装置与方法
JP4327863B2 (ja) * 2007-03-19 2009-09-09 株式会社東芝 映像蓄積装置とその制御方法
US20090006756A1 (en) * 2007-06-29 2009-01-01 Donley Greggory D Cache memory having configurable associativity
US9442846B2 (en) * 2009-03-17 2016-09-13 Cisco Technology, Inc. High speed memory systems and methods for designing hierarchical memory systems
US8433880B2 (en) 2009-03-17 2013-04-30 Memoir Systems, Inc. System and method for storing data in a virtualized high speed memory system
JP5482145B2 (ja) * 2009-11-25 2014-04-23 富士通株式会社 演算処理装置および演算処理装置の制御方法
WO2011075167A1 (en) * 2009-12-15 2011-06-23 Memoir Systems,Inc. System and method for reduced latency caching
US8843690B2 (en) 2011-07-11 2014-09-23 Avago Technologies General Ip (Singapore) Pte. Ltd. Memory conflicts learning capability
KR20140072276A (ko) * 2012-11-29 2014-06-13 삼성전자주식회사 불휘발성 메모리 및 불휘발성 메모리의 동작 방법
JP2015104045A (ja) * 2013-11-27 2015-06-04 株式会社日立製作所 通信装置、通信方法、および、記録媒体
US9753667B2 (en) * 2015-02-19 2017-09-05 Avago Technologies General Ip (Singapore) Pte. Ltd. High bandwidth memory and glitch-less differential XOR
US10073786B2 (en) * 2015-05-28 2018-09-11 Micron Technology, Inc. Apparatuses and methods for compute enabled cache
KR101727407B1 (ko) * 2015-10-29 2017-04-14 주식회사 넥서스칩스 렌즈 왜곡 교정 장치 및 동작 방법
CN107526691B (zh) * 2016-06-21 2020-06-02 深圳市中兴微电子技术有限公司 一种缓存管理方法及装置
US10031834B2 (en) 2016-08-31 2018-07-24 Microsoft Technology Licensing, Llc Cache-based tracing for time travel debugging and analysis
US10915453B2 (en) 2016-12-29 2021-02-09 Intel Corporation Multi level system memory having different caching structures and memory controller that supports concurrent look-up into the different caching structures
TWI650640B (zh) * 2017-07-14 2019-02-11 瑞昱半導體股份有限公司 用於處理器的資料存取裝置與方法
US10642737B2 (en) * 2018-02-23 2020-05-05 Microsoft Technology Licensing, Llc Logging cache influxes by request to a higher-level cache
US11914518B1 (en) * 2022-09-21 2024-02-27 Arm Limited Apparatus and method for operating a cache storage

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EP1565827A2 (en) 2005-08-24
AU2003287522A1 (en) 2004-06-18
WO2004049171A2 (en) 2004-06-10
US20040103250A1 (en) 2004-05-27
CN1717664A (zh) 2006-01-04
CN1717664B (zh) 2010-10-27
EP1565827B1 (en) 2016-06-15
JP4425798B2 (ja) 2010-03-03
JP2006507602A (ja) 2006-03-02
US7073026B2 (en) 2006-07-04
KR20050085150A (ko) 2005-08-29
WO2004049171A3 (en) 2004-11-04
TW200417913A (en) 2004-09-16
TWI307476B (en) 2009-03-11

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