KR100954671B1 - Apparatus and method for encoding/decoding using signal division - Google Patents

Abstract

The present invention relates to a signal splitting encoding / decoding apparatus and a method thereof, wherein a binary signal (binary signal sequence) is divided and encoded according to a predetermined ratio, and then mapped to the most significant bit and the least significant bit, thereby implementing DPC (Dirty Paper Coding). An apparatus and method for encoding / decoding a signal division scheme are provided to enable a grid having a low time complexity and a high coding gain.

To this end, the present invention provides a signal splitting encoding apparatus comprising: signal distribution means for distributing a binary signal into first and second binary signals according to a predetermined ratio; First encoding means for encoding and combining the first binary signal and the virtual bit distributed from the signal distribution means, respectively; Second encoding means for encoding a second binary signal distributed from said signal distribution means; And mapping means for mapping the operation result from the first encoding means and the signal encoded by the second encoding means, respectively.

Dirty Paper Coding (DPC), Low Density Parity-Check Code (LDPC), LDPC Lattice, Most Significant Bit, Least Significant Bit, Encoding, Decoding

Description

Apparatus and method for encoding / decoding using signal division}

The present invention relates to a signal splitting encoding / decoding apparatus and a method thereof, and more particularly, by dividing a binary signal (binary signal string) according to a predetermined ratio and encoding each of them, and then mapping them into the most significant bit and the least significant bit, thereby performing DPC (Dirty). It relates to a signal splitting encoding / decoding apparatus and a method for designing a grid having a low complexity and a high coding gain when implementing paper coding.

Recently, multiple input multiple output (MIMO) schemes have attracted attention in the wireless communication domain. In particular, in the case of one-to-many communication, a DCP (Dirty Paper Coding) method of removing an interference signal in advance has attracted attention.

In the DCP scheme, when a transmitting end transmits two different signals a and b to two different users A and B, a signal a 'such as noise is generated using the correlation between the signals a and b, and then the signal b In addition to and transmit to the channel. User B, who receives this signal, then considers both noise from the channel and signal a 'as noise and restores signal b. Of course, user A restores signal a from the processed signal a '.

In addition, knowing about a signal b that can act as an interference when restoring the original signal a to a 'is like writing on dirty paper, and user A has perfected the signal a even though the interference of signal b is very large. No matter how dirty the paper is, it can be restored, so it is called DPC.

The DPC method was introduced in 1983 in 'M. First mentioned in a paper by Costa's proposal, "Writing on Dirty Paper" (IEEE Transactions On Information Theory, vol. IT-239, No. 3, May 1983), where channel capacity is interfering under DPC transmission power limitations. It showed the same as if it did not exist.

As a result, the DPC scheme may be referred to as an interference canceling technique at the transmitting end that prevents the receiving end from being affected by the interference signal when the transmitting end is known in advance.

When the DPC method is actually implemented, the interference signal is removed after the interference signal is removed. Therefore, the original power allocation requirement is not satisfied due to the interference signal from which the transmission signal power is removed. Therefore, a lattice operation is performed to reshape the transmission signal set. In this case, the lattice calculation is usually performed through a shaping code.

Two error correction codes may be used as an implementation structure of the DPC. One is literally used as an error correction code and the other is a canonical code that changes the shape of the transmitted signal set. In order to approach the ideal channel capacity, an error correction code with a high coding gain and a formal code with a high shaping gain should be used.

An example of implementing a DPC using two error correction codes is "A Close-to-Capacity Dirty Paper Coding Scheme" (IEEE Transactions On Information Theory, vol. 51) proposed by Uri Erez and Stenphan ten Brink. , No. 10, Oct 2005).

Meanwhile, in wireless communication, channel coding is used to reliably recover noise-received received signals from a channel. Therefore, current channel coding techniques have been focused on error correction performance. If the channel coded transmission is influenced by another signal in the channel and interference is added like noise, techniques for eliminating interference at the transmitter or the receiver are used accordingly.

That is, the transmitter applies an interference cancellation technique such as 'TDM' or 'Zero-Forcing' to the channel coded signal and transmits, or the receiver uses an interference cancellation technique such as Successive Interference Cancellation (SIC).

On the other hand, DPC is a channel coding method that can perform not only error correction but also interference cancellation, and processes signals that may cause interference at the transmitting end in advance, so that the receiving end does not know the interference signal. Allow the signal to be recovered.

This DPC is required to be more sophisticated for the shape of the transmission signal due to interference cancellation, there is a problem that is difficult to apply to the actual system due to the high implementation complexity.

It is an object of the present invention to solve this problem.

Therefore, the present invention divides a binary signal (binary signal string) according to a predetermined ratio and encodes each of them, and then maps them into the most significant bit and the least significant bit, so that a low complexity and high coding gain can be designed when implementing DPC (Dirty Paper Coding). An object of the present invention is to provide an encoding device and a method thereof.

Another object of the present invention is to provide a signal division decoding apparatus and method for dividing and decoding a signal encoded in the above manner into the most significant bit and the least significant bit.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention which are not mentioned above can be understood by the following description, and will be more clearly understood by the embodiments of the present invention. Also, it will be readily appreciated that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

An apparatus of the present invention for achieving the above object comprises: a signal splitting apparatus, comprising: signal distribution means for distributing a binary signal into first and second binary signals according to a predetermined ratio; First encoding means for encoding and combining the first binary signal and the virtual bit distributed from the signal distribution means, respectively; Second encoding means for encoding a second binary signal distributed from said signal distribution means; And mapping means for mapping the operation result from the first encoding means and the signal encoded by the second encoding means, respectively.

In addition, the method of the present invention for achieving the above object comprises the steps of: splitting a binary signal into a first binary signal and a second binary signal; A first encoding step of encoding and combining the divided first binary signal and the received virtual bit, respectively; A second encoding step of encoding the divided second binary signal; And a mapping step of mapping the operation result of the first encoding step and the encoding result of the second encoding step, respectively.

On the other hand, the apparatus of the present invention for achieving the above object, the decoding apparatus of the signal division method, the least significant bit decoding means for decoding the least significant bit of the received signal; Subtraction means for extracting the most significant bit by removing the least significant bit decoded by the least significant bit decoding means from the received signal; Most significant bit decoding means for decoding the most significant bit extracted by said subtraction means; And signal assembling means for assembling the least significant bit decoded by the least significant bit decoding means and the most significant bit decoded by the most significant bit decoding means.

In addition, the method of the present invention for achieving the above object, the decoding method of the signal division method, Decoding the least significant bit of the received signal; Extracting the most significant bit by removing the decoded least significant bit from the received signal; Decoding the extracted most significant bit; And assembling the decoded least significant bit and the decoded most significant bit.

In addition, the present invention is composed of a top lattice generated using a convolutional code and a Low Density Parity-check Code (LDPC) grid generated by a "Construction D '" method. By using two different grid operators at the same time, you can design a better grid.

In addition, the present invention generates a good-looking transmission signal by using a LDPC grid, which is a multi-level grid, and code bit shaping.

In addition, the present invention reduces the complexity of DPC (Dirty Paper Coding), which is an optimal channel coding scheme in multi-user wireless communication.

As described above, the present invention divides a binary signal (binary signal sequence) according to a predetermined ratio and encodes the respective signals and maps them to the most significant bit and the least significant bit, thereby designing a grid having low complexity and high coding gain when implementing DPC (Dirty Paper Coding). It has the effect of making it possible.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, It can be easily carried out. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of an embodiment of a DPC transmission / reception apparatus used in the present invention.

As shown in FIG. 1, the transmitter includes an interference canceling unit 11 and a lattice operator 12, and the receiver includes a scaling unit 14, a dither adder 15, and a lattice operator 16. Include.

Here, the interference canceling unit 11 removes the interference signal from the transmitter so that the receiver can receive the signal without interference.

The lattice operators 12 and 16 are modular operators that adjust the transmission power by changing the shape of the set of signals from which the interference is removed by the interference canceling unit 11.

In this case, the signal X passing through the interference canceling unit 11 and the lattice operator 12 is as shown in Equation 1 below.

는 격자(lattice)를 각각 나타낸다.Where W is the source message, S is the interference signal, α is the scaling factor, U is the dithering signal,

Represents a lattice, respectively.

Hereinafter, the grating, the dither signal, and the magnification will be described in more detail.

는 n차원 유클리드(Euclidean) 공간의 이산 부분군(discrete subgroup)이다. 즉,

이면 집합

를 n차원 공간에서 격자

의 잉여류(coset)라고 한다. 이때, 격자

의 기본 보르노이 영역(fundamental Voronoi region) v는 격자

의 잉여류 중 유클리드 놈(norm)이 가장 작은 잉여류를 나타낸다.First, lattice

Is a discrete subgroup of n-dimensional Euclidean space. In other words,

Back side set

Grid in n-dimensional space

It is called coset of. At this time, the grid

Fundamental Voronoi region v of the lattice

The surplus of Euclidean norm represents the smallest surplus.

는 유일하게

로 표현할 수 있다. 이때, r은

로 표현할 수 있다. 이때, Q(x)는

를 만족하는 x에서 가장 가까운 n차원 점을 나타낸다.random

Is the only one

Can be expressed as Where r is

Can be expressed as Where Q (x) is

Represents the nearest n-dimensional point in x that satisfies.

로 표현할 수 있다. 이는 기본 보르노이 영역의 모양이 전송신호 집합의 모양을 결정하며, 전송신호의 파워를 결정한다는 것을 의미한다.In addition, the basic Bornoi domain

Can be expressed as This means that the shape of the basic Bornoi region determines the shape of the transmission signal set and determines the power of the transmission signal.

Next, the dither signal U is a random variable uniformly distributed in the basic Bornoir region v known to both the transmitter and the receiver. Normally, when the interference signal S is biased in one place without being sufficiently random, the transmission signal is not uniform in the basic Bornoir region v.

In this case, when decoding the received signal, the interference signal, which is regarded as noise, is biased into one place, making it difficult to recover the original signal. To avoid this, the dither signal U is added so that the transmission signal X is uniform in the basic Bornoi region. That is, the disordered nature of the dither signal U makes the source message W and the transmitted signal X independent of each other when passing through the channel.

Next, the magnification α is a value known to both the transmitter and the receiver. This is set to minimize the effective noise. In this case, the magnification α is generally expressed as SNR / (SNR + 1). Here, SNR represents a signal to noise ratio obtained through the channel.

On the other hand, if the signal (Y = X + S + Z, Z is a noise signal) received through the channel 13 passes through the scaling unit 14, the dither adder 15 and the lattice operator (16) 2].

Modification of [Equation 2] is the same as the following [Equation 3].

는 유효잡음을 나타낸다. 이때, 전송신호 X는 디더신호 U로 인해 W와는 서로 독립되어 유효잡음으로 보이게 된다.here,

Denotes effective noise. At this time, the transmission signal X is independent of the W due to the dither signal U and appears to be effective noise.

FIG. 2 is a block diagram of an encoding / decoding apparatus according to an embodiment of the present invention. Components except for the encoding apparatus 200 and the decoding apparatus 300 may include the above-described DPC transmission / reception apparatus. Indicates.

As shown in FIG. 2, the encoding apparatus 200 according to the present invention includes a signal distribution unit 210 for distributing a binary signal (binary signal string) at a predetermined ratio (first and second binary signals) and the signal. The first encoder 220 and the signal distributor 210 for performing an exclusive OR operation after encoding the binary signal (the first binary signal) and the virtual bit distributed from the distributor 210, respectively. Low Density Parity-Check Code (LDPC) lattice encoder 230 for encoding a binary signal (second binary signal) distributed from the first encoder 220 and a first bit (MSB): It includes a mapping unit 240 for mapping to Most Significant Bit, and the signal encoded by the LDPC lattice encoder 230 to the least significant bit (LSB).

Here, the least significant bit means the remaining bits except the most significant bit, and the number of most significant bits is arbitrarily set according to the applied system. That is, the most significant bit may be a signal string consisting of several bits rather than one bit (for example, most significant bit 0 1 and least significant bit: 1 0 2 2 4 7 0).

In addition, the code consisting of the most significant bit and the least significant bit is the source message W in FIG. 1 and is transmitted through the channel through the interference canceling unit 11 and the lattice operator 12. In this case, the modular operation performed by the grid operator 12 is a modular operation considering the highest lattice and the LDPC grid at the same time.

In addition, the signal output from the LDPC trellis encoder 230 is a 'non-binary' signal sequence.

Also, it is preferable that the virtual bit select a signal that minimizes the power of the transmission signal X.

In addition, the signal distributor 210 distributes one bit to a predetermined ratio, for example, the first encoder 220 and two bits to the LDPC grid encoder 230. At this time, the ratio can be arbitrarily set by the designer.

In addition, the first encoder 220 encodes a convolutional encoder 221 for receiving and encoding a virtual bit and a binary signal (first binary signal) distributed from the signal distributor 210. LDPC encoder 222, an inverse syndrome generator 223 for adjusting the output bits of the LDPC encoder 222 according to the number of output bits of the convolutional encoder 221, and an output bit of the convolutional encoder 221. And an exclusive OR operator 224 for performing an exclusive OR operation on the output bit adjusted by the inverse syndrome generator 223.

Here, since the LDPC encoder 222 has a high coding gain of the LDPC grid encoder 230, the LDPC encoder 222 serves to provide a corresponding coding gain.

The signal output from the LDPC encoder 222 is a binary signal string.

In addition, the inverse syndrome generator 223 adjusts an output bit so that the signal sequence from the LDPC encoder 222 can be computed in a bit-by-bit manner with the signal sequence from the convolutional encoder 221.

Meanwhile, the decoding apparatus 300 according to the present invention removes the least significant bit decoded by the LDPC lattice decoding unit 310 and the LDPC lattice decoding unit 310 to decode the least significant bit of the received signal from the received signal. A subtractor 320 for extracting the most significant bit, a first decoder 330 for decoding the most significant bit extracted by the subtractor 320, and a least significant bit decoded by the LDPC trellis decoder 310 and the first bit; 1 includes a signal assembly unit 300 for assembling (combining) the most significant bit decoded by the decoder 330.

The first decoder 330 may include a convolutional decoder 331 for decoding the most significant bit extracted by the subtractor 320, and an LDPC decoder for decoding the most significant bit extracted by the subtractor 320. 332). In this case, the convolutional decoder 331 includes a syndrome generator corresponding to the inverse syndrome generator in the encoding process.

In addition, since the binary signal sequence encoded by the LDPC encoder 222 passes through the inverse syndrome generator 223 and is generated through an exclusive OR operation with the signal sequence encoded by the convolutional encoder 221, the convolutional decoder during encoding is performed. 331 and LDPC decoder 332 iteratively decode each other.

In other words, messages must be exchanged with each other when decrypted. At this time, the LDPC decoder 332 decodes using the "Sum-product algorithm", and the convolutional decoder 331 decodes using the BCJR algorithm. All of these are generally well known techniques and will not be described in detail.

In addition, the LDPC lattice has channel coding at multi-level and convolutional codes have a canonical function.

을 한다. 이때, LDPC 격자 복호화부(310)에서 수행하는 모듈러 연산은

이다. 즉,

이다. 다만, 부호비트 세이핑으로 만들어진 최상위비트 때문에 전체 모듈러 연산에서는

을 한다.In addition, since the received signal is composed of the most significant bit and the least significant bit, and the most significant bit and least significant bit constitute one codeword, the modular operation

Do it. At this time, the modular operation performed by the LDPC grid decoding unit 310 is

to be. In other words,

to be. However, because of the most significant bit created by sign bit shaping,

Do it.

In addition, the receiver 300 decodes the least significant bit from the LDPC lattice decoder 310. At this time, the decoding method is the same as the decoding method of the LDPC code. That is, the decoding may be performed in a "Sum Product Algorithm" method using a tanner graph. However, the difference from the binary case is that the operations performed at each parity node are multilevel modular operations, not exclusive OR operations. 6 shows a Tanner graph when decoding an LDPC grid.

Hereinafter, the components will be described in more detail.

The LDPC code is a binary linear block code and has a parity check matrix with a very low density of code " 1. " The binary linear block code (codeword) c and the corresponding parity check matrix H have a relationship as shown in Equation 4 below.

When the LDPC code is decoded on the user side, Equation 4 may be a rule for decoding.

The LDPC encoder 222 may be implemented with a Tanner graph. At this time, the Tanner graph is a kind of factor graph, in which Equation 4 is expressed as a graph.

As shown in FIG. 3, each symbol constituting a codeword is represented by a symbol node, and an intermediate parity check relationship is represented by a parity check node.

When the Maximum A Posteriori (MAP) algorithm is implemented through a Tanner graph, decoding is performed through a Sum Product Algorithm (SPA) algorithm. At this time, the technique in which the "SPA" algorithm operates through a factor graph is "Factor Graphs and the Sum-Product Algorithm" of 'Fank R. Kschischang', 'Brendan J. Frey' and 'Hans-Andrea Loeliger'. (IEEE Transactions on Information Theory, Vol. 47, No. 2, Feb 2001).

Meanwhile, the LDPC lattice encoder 230 encodes using the construction D 'method. The construction D 'method is one of methods for making a grid from codes, and the methods of making a grid from codes include construction A, B, C, D, and D'.

The Construction A method cannot produce a grid whose code gain is greater than four. The construction A method is described in 'J.H. Conway "and" N.J.A. Sloane's "Sphere Packings, Lattices and Groups" (3nd ed. New York: Springer-Verlag, 1998).

The Construction B method is only applicable to codes with a 'minimum Hamming Distance' of 8. A description of the Construction B method is described in detail in "Some sphere packings in higher space" by J. Leech (Canad. J. Math., Vol. 16, pp. 657-682, 1964).

Construction C produces 'non-lattice packing'. A description of the Construction C method is described in detail in "Some sphere packings in higher space" by J. Leech (Canad. J. Math., Vol. 16, pp. 657-682, 1964).

The Construction D method can design a grid having a high sign gain from a generator set of codes. Techniques for the Construction D method are described in detail in "New lattice packings of spheres" by ESBarnes and NJASloane (Canad. J. Math., Vol. 35, pp. 824-882, Feb. 2001). have.

The Construction D 'method is a way to build a grid from a set of parity checks. Construction D 'technique is described in' A. Bos', 'J.H.Conway' and 'N.J.A.Sloane', "Further lattice packings in high dimensions" (Mathematika, vol. 29, pp. 171-180, 1982).

를 선형 바이너리 부호(linear binary code)의 집합이라고 하고, 부호

은

와 같은 매개변수를 갖는다.In addition, LDPC grids are created through 'multilevel construction' of the parity check matrix.

Is called a set of linear binary codes

silver

It has the same parameters as

는 필드

에서 선형 독립(linearly independent)적인 벡터이며, 부호

은 패리티 검사 벡터

에 의해서 정의되며, 여기서

을 만족한다. 이때, construction D'을 2의 거듭제곱으로 모듈러 연산식에 곱하는 형태로 구현할 수 있다.

The field

Is a linearly independent vector in

Silver parity check vector

Defined by where

To satisfy. In this case, the construction D 'may be implemented by multiplying the modular expression by a power of two.

가 성립하려면 하기의 [수학식 5]를 만족해야 한다.n dimensional vector

To satisfy Equation 5, Equation 5 below must be satisfied.

Modification of [Equation 5] is the same as the following [Equation 6].

Equation 6 is a parity check equation of the lattice.

5 is an example of the LDPC grating thus made. Techniques for LDPC lattice are described in "Low-Density Parity-Check Lattices: Construction and Decoding Algorithm" by Mohammad-Reza Sadeghi, Amir H. Banihashemi and Daniel Panario (IEEE Transactions on Information Theory, Vol. 52, No. 10, Oct 2006).

On the other hand, the process of making the top grid with convolutional code is called sign-bit shaping.

FIG. 4 is an exemplary view for explaining code bitsafety using a syndrome generator and an inverse syndrome generator used in the present invention.

인 패리티 검사 매트릭스이다. 임의의 코드워드

는 신드롬 형성기를 통해 영벡터(all zero vector)가 된다. 즉,

를 만족한다.The syndrome former of binary linear convolutional code C with a coding rate of k / n is

In parity check matrix. Any codeword

Becomes an all zero vector through the syndrome generator. In other words,

.

로 신드롬 형성기의 좌역(left inverse)을 취해서 얻을 수 있다. 즉,

를 만족한다. 임의의 n차원 바이너리 벡터 z의 신드롬 벡터는

이다. 이때, z가 코드 C에 속하지 않는다면 그 신드롬 벡터는

를 만족한다. 또한,

이면

이므로 z와 z'은 같은 신드롬을 갖는다.Inverse syndrome former 223

This can be obtained by taking the left inverse of the syndrome generator. In other words,

. The syndrome vector of any n-dimensional binary vector z is

to be. If z does not belong to code C, then the syndrome vector is

. Also,

Back side

Z and z 'have the same syndrome.

이므로 신호 z의 신드롬은 s이다.As shown in FIG. 4, the syndrome signal s generates a z signal through the inverse syndrome generator 223. At this time,

Since the signal z's syndrome is s.

The generated signal z is mapped to the most significant bit after the exclusive OR operation with the convolutional code generated by the convolutional encoder 221. Here, the signal v input to the convolutional encoder 221 is called a virtual bit. The virtual bit is selected as an input signal that minimizes the power of the final code consisting of the most significant bit and the least significant bit.

는 신드롬 형성기를 지나 신드롬 신호 s의 추정신호(estimated signal)

가 된다.When the final codeword x, which consists of the most significant bit z 'and the least significant bit, is passed through the channel to the receiver 300, the most significant bit

Is the estimated signal of the syndrome signal s past the syndrome former.

Becomes

7 is a flowchart illustrating an encoding method of a signal division method according to the present invention.

First, a binary signal is divided into a first binary signal and a second binary signal (701).

Subsequently, an exclusive OR operation is performed after encoding the distributed first binary signal and the received virtual bit, respectively, in operation 702.

That is, the virtual bits are received and encoded.

And encode the distributed first binary signal.

The output bit of the encoded first binary signal is adjusted according to the number of output bits of the encoded virtual bit.

An exclusive OR operation is performed on the output bit of the encoded virtual bit and the output bit of the encoded first binary signal.

Thereafter, LDPC lattice coding of the distributed second binary signal is performed (703).

Thereafter, the exclusive OR operation result is mapped to the most significant bit, and the LDPC lattice coded signal is mapped to the least significant bit (704).

8 is a flowchart illustrating an embodiment of a signal division decoding method according to the present invention.

First, the least significant bit of the received signal is decoded (801).

Thereafter, the decoded least significant bit is removed from the received signal to extract the most significant bit (802).

Thereafter, the extracted most significant bit is decoded (803).

Thereafter, the decoded least significant bit and most significant bit are assembled (804).

On the other hand, the method of the present invention as described above can be written in a computer program. And the code and code segments constituting the program can be easily inferred by a computer programmer in the art. In addition, the written program is stored in a computer-readable recording medium (information storage medium), and read and executed by a computer to implement the method of the present invention. The recording medium may include any type of computer readable recording medium.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by the drawings.

1 is a configuration diagram of an embodiment of a DPC transmission / reception apparatus used in the present invention;

2 is a configuration diagram of an encoding / decoding apparatus of a signal division method according to an embodiment of the present invention;

3 is an exemplary diagram illustrating a general LDPC bipartite graph and a parity check matrix corresponding thereto;

4 is an exemplary view for explaining code bitsafety using a syndrome generator and an inverse syndrome generator used in the present invention;

5 is an exemplary view of a typical LDPC lattice,

6 is an exemplary diagram illustrating a Tanner graph when decoding a general LDPC grid;

7 is a flowchart illustrating an encoding method of a signal division method according to the present invention;

8 is a flowchart illustrating an embodiment of a signal division decoding method according to the present invention.

* Explanation of symbols for the main parts of the drawings

200: transmitting device 210: signal distribution unit

220: first encoder 230: LDPC grid encoder

240: mapping unit 300: receiving device

310: LDPC grid decoding unit 320: subtraction unit

330: First decoding unit 340: Signal assembly unit

Claims (20)

In the encoding apparatus of the signal division method, Signal distributing means for distributing a binary signal into first and second binary signals according to a predetermined ratio; First encoding means for encoding and combining the first binary signal and the virtual bit distributed from the signal distribution means, respectively; Second encoding means for encoding a second binary signal distributed from said signal distribution means; And Mapping means for mapping the operation result from said first encoding means and the signal encoded by said second encoding means, respectively A signal splitting encoding apparatus comprising a. The method of claim 1, The first encoding means, And encoding the respective first binary signals and the virtual bits, respectively, through an exclusive-OR operation. The method according to claim 1 or 2, The mapping means, And the result of the calculation from the first encoding means to the most significant bit, and the signal encoded by the second encoding means to the least significant bit. The method of claim 3, wherein The second encoding means, And a second binary signal distributed from the signal distribution means to output a non-binary signal. The method of claim 3, wherein The least significant bit is, And a bit remaining except for the most significant bit. The method of claim 3, wherein The first encoding means, Convolutional encoding means for receiving and encoding the virtual bits; LDPC encoding means for encoding the first binary signal distributed from the signal distribution means; Inverse syndrome forming means for adjusting the output bits of the LDPC encoding means in accordance with the number of output bits of the convolutional encoding means; And Exclusive OR operation means for performing an exclusive OR operation on the output bit of the convolutional encoding means and the output bit adjusted by the inverse syndrome forming means. A signal splitting encoding apparatus comprising a. The method of claim 6, The LDPC encoding means, And encoding a first binary signal distributed from the signal distribution means to provide a gain corresponding to an encoding gain of the second encoding means. The method of claim 6, The LDPC encoding means, And encoding the first binary signal distributed from the signal distribution unit to output an encoded binary signal. The method of claim 6, The reverse syndrome forming means, And an output bit adjusted so that the binary signal sequence from the LDPC encoding unit can be combined with the binary signal sequence from the convolutional encoding unit in a bit-by-bit manner. The method of claim 6, The virtual bit, A signal division method encoding apparatus, characterized in that the signal to minimize the power of the transmission signal. In the decoding apparatus of the signal division method, Least significant bit decoding means for decoding the least significant bit of the received signal; Subtraction means for extracting the most significant bit by removing the least significant bit decoded by the least significant bit decoding means from the received signal; Most significant bit decoding means for decoding the most significant bit extracted by said subtraction means; And Signal assembling means for assembling the least significant bit decoded by the least significant bit decoding means and the most significant bit decoded by the most significant bit decoding means. Signal splitting decoding apparatus comprising a. The method of claim 11, The least significant bit decoding means, Low density parity-check code (LDPC) lattice decoding means. The method of claim 11, The most significant bit decoding means, Convolutional decoding means for decoding the most significant bit extracted by the subtraction means; And LDPC decoding means for decoding the most significant bit extracted by the subtraction means Signal splitting decoding apparatus comprising a. The method of claim 13, The convolutional decoding means and the LDPC decoding means, The decoding apparatus of the signal division method characterized by decoding the most significant bit through the mutual message transmission. In the coding method of the signal division method, Dividing the binary signal into a first binary signal and a second binary signal; A first encoding step of encoding and combining the divided first binary signal and the received virtual bit, respectively; A second encoding step of encoding the divided second binary signal; And A mapping step of mapping the operation result of the first encoding step and the encoding result of the second encoding step, respectively Encoding method of the signal division method comprising a. The method of claim 15, The first encoding step, A method of encoding a signal division method, comprising combining through an exclusive OR operation. 17. The method according to claim 15 or 16, The mapping step, And a mapping result of the first encoding step to the most significant bit and a mapping result of the second encoding step to the least significant bit. The method of claim 17, The first encoding step, Receiving and encoding a virtual bit; Encoding the split first binary signal; Adjusting an output bit of the encoded first binary signal according to the number of output bits of the encoded virtual bit; And Performing an exclusive OR operation on the output bits of the encoded virtual bits and the output bits of the adjusted first binary signal. Encoding method of the signal division method comprising a. The method of claim 18, The virtual bit, A signal division method encoding method, characterized in that the signal to minimize the power of the transmission signal. In the decoding method of the signal division method, Decoding the least significant bit of the received signal; Extracting the most significant bit by removing the decoded least significant bit from the received signal; Decoding the extracted most significant bit; And Assembling the decoded least significant bit and the decoded most significant bit Decoding method of the signal division method comprising a.

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