KR100946601B1 - Driver of display unit - Google Patents

Abstract

According to an aspect of the present invention, a latch circuit for holding gray scale information, a D / A converter for outputting an analog signal based on the gray scale information held by the latch circuit, and a test circuit provided between the latch circuit and the D / A converter , A test circuit for inputting or outputting a test signal related to a latch circuit, a switch connecting the voltage output of the D / A converter and the driver output terminal in normal operation, and connecting the test circuit and the driver output terminal in the test operation and testing in normal operation. A driver for a display unit is provided that includes a test switch that disconnects circuitry from the driver output terminals.

Display unit, gradation information, driver

Description

Driver of display unit {DRIVER OF DISPLAY UNIT}

The present invention relates to a driver of a liquid crystal display, an organic light emitting display, a plasma display or such a display unit. More particularly, the present invention relates to a column driver, a source driver, a horizontal driver or a driver of such a display unit.

BACKGROUND OF THE INVENTION A display unit is increasing in size in recent years due to the development of manufacturing technology. Display units with large sizes require the ability to drive large capacitance loads on the driver outputs. That means the output impedance of the driver should be reduced. If the output impedance is not substantially small, problems arise, such as lack of driving capability, increased power consumption or heat generation.

Moreover, recent display units perform multi-gradation display, and multi-bit drivers of display units have been developed. In addition, the drivers of typical display units have hundreds of driving outputs and include latch circuits, level shifters, D / A converters and buffer amplifiers.

Fig. 13 shows an example of a driving output circuit inside a driver of a driver unit according to the prior art.

The driver shown in FIG. 13 is an output circuit having two outputs. The driver 10 of the display unit includes a latch circuit 11, a level shifter 12, a D / A converter 13, an output amplifier 15, an output switch 16, and an output pin 17. . In this example, it is assumed that the display unit is a liquid crystal display and includes a polarity switching circuit 14 and an output switch 16. In this example, the polarity switching circuit 14 is provided between the D / A converter 13 and the output amplifier 15. However, the polarity switching circuit 14 may be provided between the output amplifier 15 and the output pin 17. In this case, the polarity switching circuit may function as an output switch.

In the following, the operation of the driver of the display unit shown in Fig. 13 is briefly described. The latch circuit 11 holds digital gradation information for each driving output and outputs the digital gradation information to the level shifter 12 as an output signal. The level shifter 12 performs voltage level conversion between the latch circuit 11 which is a low voltage circuit and the D / A converter 13 which is a high voltage circuit. The digital tone information output from the level shifter 12 is converted by the D / A converter 13 into a tone information signal having an analog value corresponding to the digital value. The gray scale information signal having an analog value that is an output from the D / A converter 13 is alternately switched by the polarity switching circuit 14 in a predetermined cycle and input to the output amplifier 15. The output amplifier 15 amplifies the analog gradation information signal and outputs the amplified signal to the output pin 17 when the output switch 16 is ON.

As noted above, testing with a multi-bit driver can take a long time and is not very accurate. To solve these problems, Japanese Unexamined Patent Application Publication No. 2006-227168 discloses a technique for providing a driver of a display unit with reduced inspection time and improved inspection accuracy.

The driver in the prior art disclosed in Japanese Unexamined Patent Application Publication No. 2006-227168 includes a selector for selecting an output of a latch circuit to output latch data from a predetermined bit, and includes a predetermined bit and a gradation voltage. And an output selector for switching the level shifter output corresponding to the output. In normal operation, the selector is switched to output a gray voltage to the driving output pin. In the test operation, the selector is switched to output a voltage (test output voltage) in accordance with the level shifter output corresponding to the predetermined bit.

As noted above, a display unit having a large size requires the ability to drive a large capacitance load of the driver's output. If the output impedance of the driver is not substantially small, problems arise such as lack of driving capability, increased power consumption or heat generation.

In the prior art of Japanese Unexamined Patent Application Publication No. 2006-227168, an output selector is provided in which a gradation voltage is output to a driving output pin of a driver in normal operation, and a test output voltage is output in a test operation. This output selector must be configured as a transistor because the output selector is implemented in an integrated circuit. Switches made of transistors have an impedance according to their size. Therefore, if a transistor with a lower impedance is used to retain large driving capability, the size of the integrated circuit constituting the selector becomes large. On the other hand, if the selector is configured with a small transistor to prevent its size from increasing, the output impedance will increase and the output load driving capability will be insufficient. In addition, if the amplifier's driving capability is enhanced to compensate for the lack of driving capability, other problems will arise, such as increased power consumption and heat generation.

Therefore, it is necessary to connect the driving output pin and the test signal without directly adding a selector which is one of the causes of increasing the impedance to the driving output pin requiring driving capability.

As a prior art, there is Japanese Unexamined Patent Application Publication No. 2006-053480.

BACKGROUND OF THE INVENTION A display unit is increasing in size in recent years due to the development of manufacturing technology. Display units with large sizes require the ability to drive large capacitance loads on the driver outputs. That means the output impedance of the driver should be reduced. If the output impedance is not substantially small, problems arise, such as lack of driving capability, increased power consumption or heat generation.

Moreover, recent display units perform multi-gradation display, and multi-bit drivers of display units have been developed. In addition, the drivers of typical display units have hundreds of driving outputs and include latch circuits, level shifters, D / A converters and buffer amplifiers.

Testing with a multi-bit driver can take a long time and is not very accurate. To solve these problems, Japanese Unexamined Patent Application Publication No. 2006-227168 discloses a technique for providing a driver of a display unit with reduced inspection time and improved inspection accuracy.

In the prior art of Japanese Unexamined Patent Application Publication No. 2006-227168, an output selector is provided in which a gradation voltage is output to a driving output pin of a driver in normal operation, and a test output voltage is output in a test operation. This output selector must be configured as a transistor because the output selector is implemented in an integrated circuit. Switches made of transistors have an impedance according to their size. Therefore, if a transistor with a lower impedance is used to retain large driving capability, the size of the integrated circuit constituting the selector becomes large. On the other hand, if the selector is configured with a small transistor to prevent its size from increasing, the output impedance will increase and the output load driving capability will be insufficient. In addition, if the amplifier's driving capability is enhanced to compensate for the lack of driving capability, other problems will arise, such as increased power consumption and heat generation.

It is necessary to connect the driving output pin and the test signal without adding a selector, which is one of the causes of the impedance increase to the driving output pin requiring driving capability.

According to an aspect of the present invention, a latch circuit for holding gray scale information, a D / A converter for outputting an analog signal based on the gray scale information held by the latch circuit, and a test circuit provided between the latch circuit and the D / A converter , A test circuit for inputting or outputting a test signal related to a latch circuit, a switch connecting the voltage output of the D / A converter and the driver output terminal in normal operation, and connecting the test circuit and the driver output terminal in the test operation, and testing in normal operation. A driver for a display unit is provided that includes a test switch that disconnects circuitry from the driver output terminals.

According to the driver of the display unit of the present invention, outputting the test result of the internal circuit from the output terminal of the driver with little or no change in the output performance of the driver of the display unit, and inputting a test signal to the output terminal of the driver It is possible.

According to the driver of the display unit of the present invention, the test can be performed without substantially reducing the performance of the driver. Therefore, the test can be performed in an easier way, and both test time and test cost can be reduced.

According to an aspect of the present invention, a latch circuit for holding gray scale information, a D / A converter for outputting an analog signal based on the gray scale information held by the latch circuit, and a test circuit provided between the latch circuit and the D / A converter , A test circuit for inputting or outputting a test signal with respect to the latch circuit, a switch connecting the voltage output and the driver output terminal of the D / A converter in normal operation, and connecting the test circuit and the driver output terminal in the test operation, A driver for a display unit is provided that includes a test switch that disconnects the test circuit from the driver output terminals.

According to the driver of the display unit of the present invention, it is possible to output the test result of the internal circuit from the output terminal of the driver and to input the test signal to the output terminal of the driver with little or no change in the output performance of the driver of the display unit. Do.

According to the driver of the display unit of the present invention, the test can be performed without substantially reducing the performance of the driver. Therefore, the test can be performed in an easier way, and both test time and test cost can be reduced.

The present invention will be described herein with reference to exemplary embodiments. Those skilled in the art will recognize that many alternative embodiments can be made using the teachings of the present invention, and that the present invention is not limited to the embodiments illustrated for illustrative purposes.

1st Embodiment

Hereinafter, a specific first embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the first embodiment, the present invention is applied to a driver of a display unit.

1 shows an example of the configuration of a driver of a display unit according to the first embodiment of the present invention. It should be noted that the driver shown in Fig. 1 is applied with the liquid crystal display as the display unit. 1 shows an example of an output circuit having only two outputs, for the sake of simplicity.

The driver 100 includes a latch circuit 101, a test circuit 102, a D / A converter 103, a polarity switching circuit 104, an output amplifier 105, an output switch 106, an output pin 107. , A test switch 108, a test controller 109, and a test signal line 110. As described above, the driver 100 of the first embodiment has two outputs. Thus, depending on the necessity of discrimination, each signal in the configuration is given a symbol of a or b.

The latch circuit 101 holds digital gradation information for each driving output and outputs the digital gradation information as an output signal to the test circuit 102. The output signal of the digital gradation information is input to the test circuit via the data buses DB0 to DB7.

The test circuit 102 tests the output signal of the latch circuit 101 and is connected to the test signal line 110. The test circuit 102 performs normal operation when the test switching signal is at the low level, and directly outputs the signal from the latch circuit 101 to the D / A converter 103. The test circuit 102 performs a test operation when the test switching signal is at a high level, and outputs a test signal, which is test information of the output signal of the latch circuit 101, to the test signal line 110. The test signal of the test circuit 102 is determined by the configuration of the test circuit 102, and the test signal may be an input signal or an output signal. The test data controls the operation of the test circuit 102. This test data is typically input to the driver 100 from a test device (not shown).

The latch circuit 101 and the D / A converter 103 are connected by data buses DB0 to DB7. For convenience, the symbols " DB0 to DB7 " indicate both the name of the data bus and the output (with a value of 0 or 1) to the data bus.

2 shows a specific configuration example 1 of the test circuit 102. For simplicity, FIG. 2 only shows the configuration of the portion of the test circuit 102 in which the test operation is performed. Thus, although not specifically illustrated, the test circuit 102 outputs the signal from the latch circuit 101 directly to the D / A converter 103 in the normal operation as described above.

As shown in FIG. 2, the test circuit 102 includes switches of SW151 to SW157. Each switch SW151 to SW157 has two input terminals a and b and one output terminal c. The eight data buses DB0 to DB7 are connected to the first stage switches of the SW151 to SW154. For example, DB0 is connected to the input terminal a of SW151 and DB1 is connected to the input terminal b of SW151. The output terminals of the first stage switches SW151 to SW154 are further connected to the input terminals of the second stage switches SW155 and SW156. The output terminals of the second stage switches SW155 and SW156 are further connected to the third stage switches SW157. These switches SW151 to SW157 are controlled by the test data TB0 to TB2 to connect the output terminal c and the input terminal a or b. For example, when the test data TB0 is 0, the test data is low level, and the switch SW151 It means that the input terminal a and the output terminal c of SW154 are connected. On the other hand, when the test data TB0 is 1, it means that the test data is at a high level, and the input terminal b and the output terminal c are connected. This can be applied to the test data TB1 and the switches SW155 and SW156, or to the test data TB2 and the switch SW157.

As shown in Fig. 3, the switches SW151 to SW157 include CMOS transfer gates TG151 and TG152 and an inverter Inv151. The transfer gates TG151 and TG152 are connected in parallel, the input terminal a and the transfer gate TG151 are connected, and the input terminal b and the transfer gate TG152 are connected. Both outputs of the transfer gates TG151 and TG152 are connected to the output terminal c. Furthermore, the test data input terminal d and the input of the inverter Inv151 are connected to each other. One of the transmission gates is selected only by the input signal of the test data input terminal d and the output signal of the inverter Inv151. The input signal to inverter Inv151 is test data.

The first stage switches SW151 to SW154, the second stage switches SW155 and SW156, and the third stage switch SW157 are controlled by the test data TB0, TB1 and TB2. Note that each test data TB0, TB1 and TB2 are binary signals. As shown in Fig. 4, the test circuit 102 outputs one of the eight signals output from the latch circuit 101 as one of the eight test signals DB0 to DB7 by eight combinations made from the test data TB0 to TB2. do.

The D / A converter 103 converts the digital signal output from the test circuit 102 into an analog signal and outputs an analog signal. The analog output signal output from the D / A converter 130a or 130b is a positive voltage output signal or a negative voltage output signal. For example, if the D / A converter 103a outputs a positive voltage output signal, the D / A converter 103b outputs a negative voltage output signal.

The polarity switching circuit 104 is a switch for inverting the polarity of the voltage sent between the liquid crystal pixel electrode and the counter electrode in a specific cycle, to prevent gradation due to the characteristics of the liquid crystal material. Therefore, the positive voltage output of the D / A converter 103a and the negative voltage output of the D / A converter 103b are switched by a specific cycle by the polarity switching circuit 104 such that it is an output to the output amplifier in the next stage. do.

The output amplifier 105 amplifies the signal from the polarity switching circuit 104 to output the amplified signal to the output switch 106. Note that the output amplifier 105a or 105b may be a positive voltage or a negative voltage.

5 shows a specific configuration of the output amplifier 105. As shown in FIG. 5, the output amplifier 105 includes an input stage 161 and an output stage 162. Input stage 161 includes PMOS transistors M161 and M162, NMOS transistors M163 to M165, and capacitance element C161. Output stage 162 includes PMOS transistor M166 and NMOS transistor M167. The input stage 161 forms a differential amplifier, and the output of the D / A converter 103a or 103b is sent to the input IN + of FIG. 5 via the polarity switching circuit 104. The output of the output 162 is sent to the input IN-. Although the output amplifier 105 shown in FIG. 5 has a differential input configuration, the output amplifier 105 may be replaced with an amplifier having a single-phase input.

The test switch 108 connects the test signal line 110 to the output pin 107 in a test operation. The test switch 108 may use a CMOS transfer gate, for example.

The output switch 106 is a switch that disconnects the output amplifier 105 of the driver and the output pin 107. The output switch 106 is connected when the mode is not the test mode (when the test switching signal is low level) and when the output control signal is high level, and disconnected when the output control signal is low level. The output control signal is high level while the output is being driven. Note that the connection between panel terminals is shortened to accumulate the charge of the panel pixels immediately before the polarity of the data line is inverted. At this time, the output control signal is set to the low level, and the output switch 106 is turned off. Thus, the output switch 106 also has a function to effectively collect the charge of the panel during this period.

The test controller 109 causes the output switch 106 to be disconnected in the test operation in which the output switch 106 is provided. In the first embodiment the output switch 106 should also be disconnected when the test switching signal is high level. Therefore, the test controller 109 is composed of an inverter INV 111 for inverting the test switching signal, and an AND circuit AND 111 for inputting an output control signal and a signal from the inverter INV 111.

In the present invention, the level shifter described in the prior art is omitted for simplicity. This is because some test circuits require a level shifter between the latch circuit and the test circuit, and other circuits require a level shifter between the test circuit and the D / A converter. Such a combination is irrelevant to the essential parts of the present invention, and thus the level shifter is not shown in the present invention.

Now, the operation of the driver of the display unit according to the first embodiment is described. The description of the operation of the latch circuit, the D / A converter, the polarity switching circuit, and the output amplifier is omitted because it has already been described in the prior art.

The following describes the case (normal state) when the test switching signal is at the low level. In the steady state, the test switching signal is at a low level, so the test circuit 102 outputs the signal from the latch circuit 101 directly to the D / A converter 103. At this time, the test switch 108 is disconnected. In the steady state, there is an output driving period and a panel charge accumulation period. During the output driving period, the output control signal is at a high level and the output switch 106 is in a conducting state. Thus, the output amplifier 105 and the output pin 107 are connected. The rest of the operation is a driver operation, which is the same as that described in the prior art.

In the first embodiment, it is assumed that the test signal is an output signal from the test circuit 102. This is because the test switch 108 is disconnected and the test signal output from the test circuit 102 may be in an output state or a high-impedance state. On the other hand, when the test signal is in the input state, the test signal may be fixed at the high level or the low level, since the high-impedance state caused by disconnecting the test switch is not preferred. If the test switching signal is low level (normal operation), the test switch may be in a connected state if the test circuit is not affected by the test signal and the test signal does not affect the output pin 107. If the test signal of the test circuit 102 has a resistance voltage that can withstand the gradation voltage output from the output amplifier, the above-described connection state may be a conducting state. The connection state referred to here is a state in which a signal can be transmitted. The level may change in transmission. The conduction state mentioned here is a connection state made with a relatively low impedance.

The case where the test switching signal is at a high level (test state) will now be described. In the test state, the test switching signal is high level, the output of the latch circuit 101 is input to the test circuit 102, the test circuit 102 performs the test and outputs the test signal to the test signal line 110 do. At the same time, the output switch 106 is disconnected by the test controller 109 regardless of the state of the output control signal. At this time, the test switch 108 is connected. Thus, the output pin 107 outputs a test signal without outputting the output gray voltage from the output amplifier 105. Alternatively, it is possible to input a test control signal from an external device via the output pin 107.

FIG. 6 shows the operation of the specific configuration example 1 of the test circuit 102 shown in FIG. 2. Each of the test data TB0, TB1 and TB2 is connected to the input terminal a or b and the output terminal c of the first stage switches SW151 to SW154, the second stage switches SW155 and the SW156 and the third stage switches SW157, which form the test circuit 102, respectively. To control. Here, in the switches SW151 to SW157, it is assumed that the input terminal a and the output terminal c are connected when the test data is 0, which means that the test data is at the low level, and the input terminal b and the output terminal c when the test data is at the high level, which is 1; Assume that is connected.

The test data TB0 repeats 0 and 1 binary data in a predetermined clock cycle. Test data TB1 repeats binary data of 0 and 1 in clock cycles twice as long as test data TB0. Test data TB2 repeats binary data of 0 and 1 in clock cycles three times longer than test data TB0. By periodic changes of the test data TB0, TB1 and TB2, the values of the data buses DB0 to DB7 (output data of the latch circuit 101 under test) are sequentially output from the test circuit 102 to the test signal line 110. do.

Instead of periodically changing the test data TB0 to TB2, it is also possible to output the values of the data buses DB0 to DB7 to the test signal line 110 by specific bit combinations. In this case, the test circuit 102 may specify one of the output data of the latch circuit 101 selected by the three bits of the test data TB0 to TB2 to output the data as the test signal. For example, when all the test data TB0 to TB2 are zero, the data bus DB0 is output as a test signal.

FIG. 7 shows a specific configuration example 2 of the test circuit 102 shown in FIG. 1. An example of test circuit 102 configuration detects whether there is a match or mismatch between two sets of 8-bit data. The test circuit 102 of this example includes XOR circuits XOR 161 to 168 and NOR circuit NOR 161. As shown in FIG. 7, the XOR circuits XOR 161 to 168 include one terminal to which 8-bit data of the latch circuit 101 outputted to the data buses DB0 to DB7 is input, and a driver 100 from a test device (not shown). ) Has another terminal to which 8-bit test data TB0 to TB7 to be inputted. The outputs of the XOR circuits XOR 161 to 168 are input to the NOR circuit NOR 161 and output from the test circuit 102 to the test signal line 110 as test signals. If the 8-bit data (measured value) and the 8-bit data (expected value) of the test data are perfectly matched from the latch circuit 101, the test circuit 102 outputs "true", otherwise, " False " In the second example, it is possible to reduce the test time since 8-bit data are compared in parallel.

The connection of the data buses DB0 to DB7 and the connection of the test circuit 102 are controlled by the test switching signal of the test circuit 102 shown in both FIGS. 2 and 7. Although the controller is not specifically shown in FIGS. 2 and 7, the connection can be realized by providing another switch between the data buses DB0 to DB7 and the input portion of the test circuit 102. The switch is closed when the test switching signal is high level, and the switch is opened when the test switching signal is low level.

In the driver 100 according to the first embodiment, the switch between the output amplifier and the output pin does not affect the driving capability of the driver even when a test circuit is added to the driver. Therefore, there is no problem that the driving capability is insufficient due to the increase of the output impedance. In addition, since there is no need to improve the driving capability of the output amplifier to compensate for the lack of driving capability, there is no problem of increased power consumption or heat generation.

2nd Embodiment

Hereinafter, the driver of the display unit according to the second embodiment of the present invention will be described with reference to FIG. 8 shows an example of the configuration of a driver of the driver unit according to the second embodiment. The configuration of the same symbol as that of FIG. 1 is the same as or similar to that of FIG. The difference between the first embodiment and the second embodiment is that in the second embodiment, the output amplifier has an output enable function, and there are differences in the configurations of the output amplifier 120 and the test controller 124.

The test controller 124 puts the output of the output amplifier 120 in a high-impedance state in a test operation when the output amplifier 120 has an output enable function. That is, the output terminal of the amplifier 120 in the test operation becomes a deactivation state. The test controller 124 is formed with an inverter INV 121 that inverts the test switching signal to put the output of the amplifier 120 in a high-impedance state when the test switching signal is high level (test operation).

From now on, the amplifier 120 will be described. 9 shows an example of an amplifier with an output enable function. As shown in FIG. 9, the amplifier 120 includes an input terminal 121, a test switching circuit 122, and an output terminal 123.

The signal from the D / A converter 103 is input to the input terminal 121. It should be noted that the specific configuration of the input terminal 121 is the same as that of the amplifier input terminal 161 shown in FIG.

The test switching circuit 122 includes switches SW121 and SW122. The SW121 switches the signal output from the input terminal 121 and the V _DD voltage according to the test switching signal, and the SW122 switches the signal and ground voltage output from the input terminal 121. The switch SW121 is connected to the output side of the input terminal 121 when the test switching signal is at the low level, and is connected to the V _DD side when the test switching signal is at the high level. Similarly, the switch SW122 is connected to the output side of the input terminal 121 when the test switching signal is low level, and is grounded when the test switching signal is high level.

Output stage 123 includes PMOS transistor M121 and NMOS transistor M122 connected in series between V _DD and ground. The output from the switch SW121 is input to the gate of the PMOS transistor M121. Similarly, the output from switch SW122 is the input to the gate of NMOS transistor M122. An output terminal of the amplifier 120 is provided between the PMOS transistor M121 and the NMOS transistor M122.

Hereinafter, the operation of the driver of the display unit according to the second embodiment will be described. The description of the configuration other than the amplifier 120 and the test controller 124 is omitted since it is the same as those of the first embodiment. The specific configuration and description of the operation of the test circuit 102 is also omitted.

In the test operation, the test switching signal is high level and the signal output from the test controller 124 is low level. Therefore, the switch SW121 of the test switching circuit 122 is connected across V _DD, the switch SW122 is connected to the ground side. Therefore, the high level signal is input to the gate of the PMOS transistor M121 of the output terminal 123, and the PMOS transistor M121 is turned off. On the other hand, the low level signal is input to the gate of the NMOS transistor M122, and the NMOS transistor M122 is likewise turned off. Therefore, the two transistors of output stage 123 are in a blocking state and the amplifier output terminal is in a high-impedance state. In other words, the output stage 123 is in an inactive state in the test operation. At this time, the test switch 108 is connected, and the test signal is connected to the output pin 107. Therefore, the output pin 107 can be used as the pin for the test signal.

On the other hand, in normal operation the test switching signal is at a low level, and the signal output from the test controller 124 is at a high level. Therefore, the switches SW121 and SW122 of the test switching circuit 122 are connected to the output side of the input terminal 121. Therefore, the output signal of the input terminal 121 is input to the output terminal 123, and the output terminal 123 functions as an inverter amplifier. The signal input from the D / A converter 103 to the output amplifier 120 is output to the amplifier output terminal with a predetermined driving capability. The rest of the operation is the same as the normal operation in the first embodiment.

In the driver 100 according to the second embodiment, the switch between the output amplifier and the output pin does not affect the driving capability of the driver even if the test circuit is added to the driver as well as the first embodiment. Therefore, there is no problem that the driving capability is reduced due to the increase of the output impedance. In addition, since there is no need to improve the driving capability of the output amplifier to compensate for the lack of driving capability, there is no problem of increased power consumption or heat generation.

Third embodiment

The driver of the display unit according to the third embodiment of the present invention is described with reference to FIG. 10 shows an example of the configuration of a driver of a display unit according to the third embodiment. 1 and 8 indicate the same or similar configuration as that of FIGS. 1 and 8. The specific configuration and description of the test circuit 102 is similarly the same. The difference between the second embodiment and the third embodiment is that in the third embodiment, the circuit of the output terminal of the output amplifier is configured with the output buffer of the test signal. There is a difference in the configuration of the output amplifier 130 and the test controller 134. However, the third embodiment is effective only when the test signal of the test circuit 102 is an output signal.

When the test switching signal is high level (test operation), the test controller 134 connects the test signal line 110 to the output terminal of the output amplifier 130. Therefore, the test controller 134 is formed by the inverter INV 131 which inverts the test switching signal.

11 shows an example of the amplifier 130 according to the third embodiment. In FIG. 11, the amplifier 130 includes an input stage 131, a test switching circuit 132 and an output stage 133. Since the input terminal 131 and the output terminal 133 have the same configuration as the input terminal 121 and the output terminal 123 shown in the second embodiment, description thereof is omitted.

The test switching circuit 132 includes switches SW131 and SW132. According to the signal obtained by inverting the test switching signal using the inverter INV 131, the switches SW131 and SW132 switch the test signal and the output signal from the input terminal 131. When the test switching signal is low level (normal operation), the switch SW131 is connected to the output side of the input terminal 131. When the test switching signal is high level (test operation), the switch SW131 is connected to the test signal line 110 side. Similarly, the switch SW132 is connected to the output side of the input terminal 131 when the test switching signal is low level (normal operation). When the test switching signal is high level (test operation), the switch SW132 is connected to the test signal line 110.

Next, the operation of the driver of the display unit according to the third embodiment will be described. However, the configuration other than the test switching circuit 132 constituting the amplifier 130 is the same as those in the second embodiment. Therefore, duplicate descriptions are omitted. Since the operation in the normal operation is the same as that in the second embodiment, the overlapping description is omitted.

In the test operation, the test switching signal is high level and the signal output from the test controller 134 is low level. Therefore, the switch SW131 of the test switching circuit 132 is connected to the test signal line 110 side. Similarly, the switch SW132 is connected to the test signal line 110 side. Therefore, the output stage 133 functions as a logic output buffer for outputting a test signal, and the signal is output to the amplifier output terminal having a predetermined driving capability.

Therefore, in the driver according to the third embodiment of the present invention, it is possible to connect the test signal and the output pin 107 during the test operation. In normal operation, the relationship between the output amplifier 130 and the output pin 107 is the same as the configuration without the test circuit 102. Therefore, there is no problem that the output impedance increases. Moreover, the test signal is output through a strong logic output buffer configured by the output stage 133 of the output amplifier 130. Therefore, since there is no test switch having the same impedance as the driver of the first and second embodiments, it is possible to output a high-speed test signal in the test operation. Accordingly, test time can be reduced.

Fourth embodiment

The driver of the display unit according to the fourth embodiment of the present invention will be described with reference to FIG. 12 shows an example of the configuration of a driver of a display unit according to the fourth embodiment. The configuration of the same symbol as that of FIG. 1 indicates the same or similar configuration as that of FIG. Specific configurations and descriptions of the operation of the test circuit 102 are similarly the same. The difference between the first and fourth embodiments is that when there is a switch circuit provided between the D / A converter 103 and the output amplifier 105 (in this example, the polarity switching circuit 104), the switch is disconnected in the test operation. Is forced to block. Therefore, the configurations of the test controller 141 and the test switch 142 are different from those of the first embodiment. But. The fourth embodiment is effective only when the test signal of the test circuit is an output signal.

The test controller 141 turns off the polarity switching circuit (the control signal of the polarity switching circuit is low level) when the test switching signal is high level (test operation). Therefore, the test controller 141 includes an inverter INV 141, an inverter INV 142, an AND circuit AND 141 and an AND circuit AND 142. Inverter INV 141 inverts the test switching signal and inverter INV 142 inverts the polarity switching signal. AND circuit AND 141 outputs the output signal of the inverter INV 142 and the polarity switching signal as input signals to the polarity switching circuit, and AND circuit AND 142 polarizes the output signal of the inverter INV 141 and the output signal of the inverter INV 142 as input signals. Output to the circuit.

The test switch 142 connects the test signal line 110 to the input of the output amplifier 105 when the test switching signal is high level (test operation).

The operation of the driver of the display unit according to the fourth embodiment will now be described. When the test switching signal is low level (normal operation), the high level signal inverted by the inverter INV 141 is input to the AND circuits AND 141 and AND 142. Therefore, the polarity switching signal and the signals obtained by inverting the polarity switching signal are output directly from the test controller 141, and the operation is the same as in the prior art. Similarly, the test switch 142 is turned off and the inputs of the test signal line 110 and the output amplifier 105 are disconnected from each other.

On the other hand, when the test switching signal at the test controller 141 is high level (test operation), the low level signal inverted by the inverter INV 141 is input to the AND circuits AND 141 and AND 142. Therefore, AND circuits AND 141 and AND 142 both output low level signals, and all polarity inverting switches 104 are in a blocked state. At the same time, the test switch 142 is ON, so that the input of the test signal line 110 and the output amplifier 105 is connected. Therefore, the test signal is output to the output pin 107 with the predetermined driving capability by the output amplifier 105.

Therefore, since the relationship between the output amplifier 105 and the output pin 107 is the same as the structure without a test circuit in normal operation, there is no problem that the output impedance increases. Moreover, the test signal is also output through the output amplifier. Therefore, unlike the driver in the first and second embodiments, there is no test switch having an impedance between the test signal and the output pin. Therefore, it is possible to output a high-speed test signal that makes it possible to reduce the test time in the test operation.

It is apparent that the present invention is not limited only to the above embodiments, but modifications and variations are possible without departing from the scope and spirit of the present invention. For example, the driver may be applied to an organic light emitting display, plasma display, SED or the like.

The above and other details, advantages, and shapes of the present invention will become more apparent from the following description of particular preferred embodiments in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The example which shows the driver structure of the display unit which concerns on 1st Embodiment of this invention.

2 is an example showing a specific configuration of a test circuit according to the first embodiment of the present invention.

3 is an example showing a specific configuration of a switch of a test circuit according to the first embodiment of the present invention.

4 is a table showing a relationship between test data and a test signal according to the first embodiment of the present invention;

5 is an example showing a specific configuration of an output amplifier according to the first embodiment of the present invention.

6 is a time chart of the operation of a test circuit according to the first embodiment of the present invention.

7 is another example showing the specific configuration of a test circuit according to the first embodiment of the present invention.

8 is an example showing the configuration of a driver of a display unit according to a second embodiment of the present invention.

9 is an example showing the configuration of an output amplifier of a display unit according to a second embodiment of the present invention.

10 is an example showing the configuration of a driver of a display unit according to the third embodiment of the present invention.

11 is an example showing the configuration of an output amplifier of a display unit according to a third embodiment of the present invention.

12 is an example showing the configuration of a driver of a display unit according to the fourth embodiment of the present invention.

13 is an example showing a driver configuration of a display unit according to the prior art.

Claims (15)

A latch circuit for holding gradation information; A D / A converter for outputting an analog signal based on the gradation information held by the latch circuit; A test circuit provided between the latch circuit and the D / A converter, wherein the test circuit inputs or outputs a test signal relating to the latch circuit; A switch connecting the voltage output and the driver output terminal of the D / A converter in normal operation; And And a test switch connecting the test circuit and the driver output terminal in a test operation and disconnecting the test circuit and the driver output terminal in a normal operation. The method of claim 1, And an amplifier for amplifying the analog signal, And the output stage of the amplifier is switched to a deactivation stage in response to a test switching signal in a test operation. The method of claim 1, And an amplifier for amplifying the analog signal, The test switch sends the test signal to an output of the amplifier in a test operation. The method of claim 1, The switch switches the polarity of the output voltage of the D / A converter to output a signal to the driver output terminal. The method of claim 1, The conduction state of the switch is controlled in accordance with an output control signal. The method of claim 1, The conduction state of the test switch is controlled in accordance with a test switching signal. A latch circuit for holding gradation information; A D / A converter for outputting an analog signal based on the gradation information held by the latch circuit; A test circuit provided between the latch circuit and the D / A converter, wherein the test circuit inputs or outputs a test signal relating to the latch circuit; In normal operation, the switch for connecting the positive voltage output and the first driver output terminal of the D / A converter and the negative voltage output and the second driver output terminal; And A test switch connecting the test circuit, the first driver output terminal and the second driver output terminal in a test operation, and disconnecting the test circuit, the first driver output terminal and the second driver output terminal in normal operation; And a driver of the display unit. The method of claim 7, wherein And an amplifier for amplifying the analog signal, And the switch sets the output stage to an inactive stage in a test operation. The method of claim 7, wherein And an amplifier for amplifying the analog signal, The test switch sends the test signal to an output of the amplifier in a test operation. The method of claim 7, wherein The switch is a switching circuit which outputs the positive voltage output of the D / A converter to the first driver output terminal and the negative voltage output of the D / A converter to the second driver output terminal. A latch circuit for holding gradation information; A D / A converter for outputting an analog signal based on the gradation information held by the latch circuit; A bus wiring connecting the latch circuit and the D / A converter; A test circuit connected to the bus wiring and outputting a test signal; An amplifier for amplifying the analog signal and outputting the amplified analog signal; A test switching signal line controlling a connection between the test circuit and the bus wiring; And And a test switch for controlling the supply of the test signal to the amplifier in response to a test switching signal. The method of claim 11, The test circuit is further connected to a test data line, And a test signal is output based on data of the bus wiring and data of the wiring of the test data. The method of claim 11, The test circuit is further connected to a test data line, And a result of comparing the data of the bus wiring with the data of the test data wiring as a test signal. The method of claim 11, The test switch is provided between the test circuit and the output terminal of the amplifier. The method of claim 11, The test switch is provided between the test circuit and the input terminal of the amplifier.

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