KR100944351B1 - Semiconductor and resistance error test method of the same - Google Patents

Abstract

The present invention discloses a semiconductor memory device and a resistivity failure test method thereof.

A semiconductor memory device according to the present invention includes a sense amplifier for sensing and amplifying a voltage difference between a bit line and a bit bar line to output cell data; A precharge unit configured to precharge the bit line and the bit bar line with a precharge voltage according to an equalization signal; And a precharge control unit controlling the output of the equalization signal such that the precharged bit line and the bit bar line float from the precharge voltage for a predetermined time before the word line is enabled. As such, the resistive defects can be more easily screened by screening the resistive defects using the precharge voltage, and can be applied to the open bit line structure as well as the folded bit line structure.

Description

Semiconductor memory device and its resistance error test method {Semiconductor and resistance error test method of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method for testing a resistive defect in the semiconductor memory device, and more particularly, to a semiconductor memory device and a resistive defect test for easily screening a resistive defect occurring in a cell region. It is about a method.

In general, semiconductor memory devices are classified into a folded bit line structure and an open bit line structure according to a structure of a memory cell array.

In a semiconductor memory device having a folded bit line structure, a bit line and a bit bar line for each sense amplifier exist in the same memory block. In contrast, in a semiconductor memory device having an open bit line structure, bit lines and bit bar lines exist in different memory blocks disposed above and below the sense amplifier. Therefore, the structure of the bit line sense amplifier used in the folded bit line structure semiconductor memory device and the open bit line structure semiconductor memory device has a slight difference.

In such a semiconductor memory device, a micro-bridge may fail between a word line and a storage node, or between a word line and a bit line. In order to screen this, an unlimited sensing delay (USD) is used. The test is in progress.

This USD test enables the word line to a high level and then delays the start time of the sense amplifier drive enough to screen the micro-bridge between the word line and the bit line.

1 is a circuit diagram schematically illustrating a semiconductor memory device having a folded bit line structure.

The mats 11 and 12 include a plurality of memory cells (not shown) and a plurality of bit line pairs BL and BLB to store or output data in the memory cells.

The sense amplifier 13 senses and amplifies data carried on the bit line pairs BL and BLB according to the control signals RTO and SB and outputs the data to a local input / output line (not shown).

The equalization and precharge unit 14 equalizes and precharges the bit line BL and the bit bar line BLB to the precharge voltage VBLP according to the equalization signal BLEQ.

The bit line separation unit 15 selectively connects the mat 11 to the sense amplifier 13 according to the separation signal BISH, and the bit line separation unit 16 connects the mat 12 to the sense amplifier according to the separation signal BISL. 13).

FIG. 2 is a timing diagram for a USD test of a semiconductor memory device having a folded bit line structure shown in FIG. 1.

When the word line WL is enabled at a high level according to the active command ACT, and a cell is selected, the capacitance of the selected cell and the bit line BL (or bit bar line BLB) is applied to the precharged bit line pair BL and BLB. The cell data is loaded in the form of charge sharing, and a voltage difference of ΔV is generated between the bit line BL and the bit bar line BLB.

Next, when the core voltage and the ground voltage are applied to the pull-up node RTO and the pull-down node SB according to the sense amplifier enable signal SAEN, the voltages of the bit line BL and the bit bar line BLB are amplified to the core voltage and the ground voltage level, respectively. do.

In the USD test, however, the charge distribution time is lengthened by sufficiently delaying the sense amplifier enable signal SAEN with an external control command. In this case, when the charge distribution time is increased, a voltage difference between the bit line BL and the bit bar line BLB is greater than ΔV due to leakage current due to such a resistive cell failure in case of a resistive cell defect D1 such as micro-bridge in the mat. Much smaller.

Therefore, the sense amplifier 13 cannot accurately amplify the data, causing a failure, and screening the resistance failure through such a failure.

However, in recent years, the threshold voltage Vt of a transistor used in a sense amplifier is set to be very low in order to improve the operation speed of a memory device, which causes a decrease in the reliability of the USD test result.

In other words, a transistor with a low threshold voltage may help to improve the operating speed. However, if the delay time of the sense amplifier is delayed during the USD test due to the weakness of the off leakage characteristic, the transistor between the word line and the bit line is delayed. Even without a bridge, leakage current from the transistor in the sense amplifier can result in a test result that a failure has occurred.

To solve this problem, in the folded bit line structure, the isolation transistors T1, T2 (or T3, T4) are turned off using the bit line isolation signal BISH (or BISL), and then the isolation is performed again after sufficient time has elapsed. Turn on the transistors. That is, by sufficiently separating the bit line pairs BL, BLB and the sense amplifier 13 during charge distribution, the sense amplifier 13 may be operated to prevent a failure due to off-recovery of transistors having low threshold voltages.

However, in the semiconductor memory device having the open bit line structure as shown in FIG. 3, since the isolation transistor does not exist, there is a problem that the method using the isolation transistor described above cannot be used.

Of course, the isolation transistor may be artificially added to the open bit line structure, but in this case, the area of the sense amplifier is increased, which may cause new problems such as an increase in cost and a deterioration in characteristics.

The present invention is to improve the resistance failure test method to more easily test the resistance failure in the open bit line structure as well as the semiconductor memory device of the folded bit line structure.

The semiconductor memory device according to the present invention

A sense amplifier for sensing and amplifying a voltage difference between the bit line and the bit bar line to output cell data;

A precharge unit configured to precharge the bit line and the bit bar line with a precharge voltage according to an equalization signal; And

And a precharge control unit controlling the output of the equalization signal such that the precharged bit line and the bit bar line float from the precharge voltage for a predetermined time before the word line is enabled.

In the semiconductor memory device of the present invention, the precharge controller is configured such that, during the predetermined time, the voltage level of the bit line in which the failure occurs is lowered by at least the voltage difference between the bit line and the bit bar line due to voltage sharing. And controlling the output of the equalization signal.

In the semiconductor memory device of the present invention, the bit line and the bit bar line have an open bit line structure.

In the semiconductor memory device of the present invention, the bit line and the bit bar line have a folded bit line structure.

The resistivity failure test method in the semiconductor memory device according to the present invention

Precharging the bit line and the bit bar line to a predetermined precharge voltage;

Floating the precharged bit line and the bit bar line from the precharge voltage for a predetermined time before a word line is enabled; And

And sensing and amplifying the voltage difference between the bit line and the bit line.

In the resistive failure test method of the present invention, the step of floating may cause the voltage level of the bit line in which the failure occurs to be floated for at least a time when the voltage difference between the bit line and the bit bar line is reduced by voltage sharing. It is characterized by.

The present invention can screen the resistive defects more easily by screening the resistive defects using the precharge voltage, and can be applied not only to the open bit line structure but also to the folded bit line structure.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

Figure 4 is a block diagram showing the configuration of a resistivity failure test apparatus according to an embodiment of the present invention.

The semiconductor memory device of FIG. 4 includes mats 110 and 120, a sense amplifier 200, a precharge unit 300, and a precharge control unit 400.

The mats 110 and 120 include a plurality of memory cells (not shown) and a plurality of bit lines BL and BLB, and store or output data in the memory cells. Here, an example in which the mat 110 is selected to read data of the mat 110 will be described.

The sense amplifier 200 senses and amplifies the voltage difference between the bit line BL and the bit bar line BLB and outputs cell data. At this time, the bit bar line BLB is used as a reference bit line.

The precharge unit 300 connects the precharge voltage VBLP to the bit line BL and the bit bar line BLB according to the equalization signal BLEQ to precharge and equalize the bit line pairs BL and BLB to the precharge voltage.

The precharge control unit 400 outputs the equalization signal BLEQ to the precharge unit 300, and controls the output of the equalization signal BLEQ according to the operation mode. The precharge control unit 400 outputs the equalization signal BLEQ at a high level in the test mode for screening the resistance failure, and then precharges the bit line pairs BL and BLB, for example, before the word line is sufficiently enabled. According to the command BST (Burst Stop), the equalization signal BLEQ is converted to a low level, thereby floating the bit line pairs BL and BLB from the precharge voltage. That is, the precharge control unit 400 controls the output of the equalization signal BLEQ so that sufficient floating time is secured between the precharge period and the word line enable time. For example, in the test mode, the precharge control unit 400 maintains the same precharge section as in the normal mode, and performs the precharge earlier than in the normal mode, or performs the precharge at the same time as the normal mode, but maintains the precharge section. Shorter reduction in normal mode ensures sufficient time between the time the wordline is enabled after precharge. In this case, the sufficient time means a time when the bit line in which the resistive failure occurs is precharged with a precharge voltage and the voltage level can be down so that the sense amplifier 200 cannot normally sense and amplify it due to the resistive defect. .

FIG. 5 is a diagram illustrating in detail the configuration of the precharge control unit 400 in FIG. 4.

The precharge control unit 400 includes NAND gates ND1, ND2, NOR gate NOR, and inverters INV1 to INV3.

The NAND gate ND1 performs a NAND operation on the test signal Testmode and the external command BST, and the inverter INV1 outputs the inverted output signal of the NAND gate ND1.

The inverter INV2 inverts and outputs the precharge command PRECHARGE, and the NAND gate ND2 performs a NAND operation on the output signal of the inverter INV2 and the active command ACT. The inverter INV3 inverts the output signal of the NAND gate ND2 and outputs the inverted signal.

The NOR gate NOR performs an NOR operation on the output signals of the inverters INV1 and INV3 and outputs an equalization signal BLEQ.

6 is a timing diagram for explaining a resistive failure test method (in test mode) according to the present invention.

In normal mode, the test signal Testmode and external command BST remain low. Therefore, the equalization signal BLEQ is selectively activated according to the active command ACT and the precharge command PRECHARGE. That is, during the precharge operation, the precharge command PRECHARGE is applied at a high level while the active command ACT is applied at a low level, and the equalization signal BLEQ is activated at a high level. Next, after a predetermined time, when the precharge command PRECHARGE is converted to the low level and the active command ACT is activated to the high level to enable the word line WL, the equalization signal BLEQ is converted to the low level and the precharge operation is terminated.

In the test mode, the test signal Testmode is maintained at a high level, and the external command BST is selectively activated at any time to control the floating operation according to the present invention. The active command ACT and the precharge command PRECHARGE are controlled in the same manner as in the normal mode.

That is, while the test signal Testmode is activated at the high level, the active command ACT is applied at the low level, and the precharge command PRECHARGE is applied at the high level, and the equalization signal BLEQ is activated at the high level and output to the precharge unit 300. .

As a result, the NMOS transistors T5 to T7 are turned on so that the bit line BL and the bit bar line BLB are precharged and equalized to the precharge voltage (1.25V).

Next, if the external command BST is activated to a high level before a time enough for the word line WL to be enabled, the equalization signal BLEQ is forcibly converted to the low level regardless of the state of the precharge command PRECHARGE. When the equalization signal BLEQ is converted to the low level, the NMOS transistors T5 to T7 of the precharge unit 300 are turned off to forcibly stop the precharge operation. Accordingly, the bit line pairs BL and BLB float from the precharge voltage. ) do.

When the bit line pairs BL and BLB are floated, and there is a bad resistance (D1) at a specific bit line BL of the mat 110, the leakage current caused by the leakage current causes the voltage level of the corresponding bit line BL to be different from that of the other normal bit line BL. It falls faster than the voltage level. As a result, the voltage levels of the bit line BL and the bit bar line BLB do not coincide.

After that, when the word line WL is enabled at a high level according to the active command ACT and the cell is selected, the cell data is charged in the form of charge sharing by the capacitance of the selected cell and the capacitance of the precharged bit line BL. Since it is loaded on the BL, a voltage difference of ΔV is generated between the bit line BL and the bit bar line BLB.

However, when the voltage level of the corresponding bit line BL is sufficiently lowered (for example, higher than ΔV) during the floating period, the sense amplifier 200 may develop during the sensing and amplification of the sense amplifier 200. (Develop) will cause badness. That is, even though the core voltage and the ground voltage are applied to the pull-up node RTO and the pull-down node SB of the sense amplifier 200, the bit line BL and the bit bar line BLB are not normally amplified to the core voltage level and the ground voltage level, respectively.

Therefore, such a fail can be screened for poor resistance.

In the above-described embodiment, an open bitline structure has been described to emphasize that the test method of the present invention can be used in an open bitline structure, but it is obvious that the test method can be applied to a folded bitline structure.

That is, the present invention can be applied to the folded bit line structure having the isolation transistor as well as the open bit line structure without the isolation transistor because the method can test the resistance failure without using the isolation transistor.

1 is a circuit diagram schematically illustrating a semiconductor memory device having a folded bit line structure.

FIG. 2 is a timing diagram for a USD test of a semiconductor memory device having a folded bit line structure shown in FIG.

3 is a circuit diagram schematically illustrating a semiconductor memory device having an open bit line structure.

Figure 4 is a block diagram showing the configuration of a resistivity failure test apparatus according to an embodiment of the present invention.

5 is a timing diagram for explaining a resistance failure test method according to the present invention.

Claims (6)

A sense amplifier for sensing and amplifying a voltage difference between the bit line and the bit bar line to output cell data; A precharge unit configured to precharge the bit line and the bit bar line with a precharge voltage according to an equalization signal; And And a precharge control unit controlling an output of the equalization signal such that the precharged bit line and the bit bar line float from the precharge voltage for a predetermined time before a word line is enabled. The method of claim 1, wherein the precharge control unit And controlling the output of the equalization signal such that the voltage level of the bit line in which the failure occurs during the predetermined time is reduced by at least the voltage difference between the bit line and the bit bar line by voltage sharing. Memory device. The method of claim 1, wherein the bit line and the bit bar line A semiconductor memory device having an open bit line structure. The method of claim 1, wherein the bit line and the bit bar line And a folded bit line structure. Precharging the bit line and the bit bar line to a predetermined precharge voltage; Floating the precharged bit line and the bit bar line from the precharge voltage for a predetermined time before a word line is enabled; And And sensing the voltage difference between the bit line and the bit bar line. The method of claim 5, wherein the floating step Resistive defect test in a semiconductor memory device, characterized in that for the time that the voltage level of the bit line in which the failure occurs can be down by at least the voltage difference between the bit line and the bit bar line by voltage sharing (Charge Sharing). Way.

Images