KR100942959B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR100942959B1
KR100942959B1 KR1020070044160A KR20070044160A KR100942959B1 KR 100942959 B1 KR100942959 B1 KR 100942959B1 KR 1020070044160 A KR1020070044160 A KR 1020070044160A KR 20070044160 A KR20070044160 A KR 20070044160A KR 100942959 B1 KR100942959 B1 KR 100942959B1
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semiconductor device
forming
substrate
gate pattern
silicon germanium
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KR20080098820A (en
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조흥재
장세억
김용수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 PMOSFET의 동작속도를 향상시키기 위해 큰 압축성 변형을 형성하기 위한 반도체 소자의 제조방법을 제공하기 위한 것으로, 본 발명은 기판 상에 게이트패턴을 형성하는 단계, 상기 게이트패턴을 포함하는 기판 상에 분리보호막을 형성하는 단계, 상기 게이트패턴 측벽의 상기 분리보호막 상에 더미스페이서를 형성하는 단계, 상기 더미스페이서를 이용하여 상기 기판을 제1리세스하는 단계, 상기 더미스페이서를 제거하는 단계, 상기 분리보호막을 이용하여 상기 기판을 제2리세스하는 단계, 상기 제1 및 제2리세스에 실리콘게르마늄을 성장시키는 단계를 포함하여 소스/드레인영역 및 LDD영역에 실리콘게르마늄을 형성하여 큰 압축성변형을 채널영역에 형성함으로써 소자의 동작 속도를 향상시킬 수 있는 효과가 있다.The present invention is to provide a method for manufacturing a semiconductor device for forming a large compressive strain to improve the operating speed of the PMOSFET, the present invention is to form a gate pattern on a substrate, on the substrate comprising the gate pattern Forming a separation protection film on the substrate, forming a dummy spacer on the separation protection film on the sidewall of the gate pattern, first recessing the substrate using the dummy spacer, removing the dummy spacer, and Forming a large compressive strain by forming a silicon germanium in the source / drain region and the LDD region including a second recess of the substrate using a separation protection film and growing silicon germanium in the first and second recesses. The formation in the channel region has the effect of improving the operation speed of the device.

실리콘게르마늄, 압축성 변형, 소스/드레인영역, LDD영역 Silicon Germanium, Compressible Strain, Source / Drain Area, LDD Area

Description

반도체 소자의 제조방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

도 1은 종래 기술에 따른 반도체 소자를 설명하기 위한 단면도,1 is a cross-sectional view for explaining a semiconductor device according to the prior art,

도 2는 게이트와 소스/드레인 거리에 따른 채널 스트레인 변화를 나타내는 그래프,2 is a graph showing channel strain variation according to gate and source / drain distances,

도 3a 내지 도 3g는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

31 : 반도체기판 32 : 소자분리막31: semiconductor substrate 32: device isolation film

33 : 게이트패턴 34 : 분리보호막33: gate pattern 34: separation protective film

35 : 더미스페이서 36 : 제1리세스35: dummy spacer 36: the first recess

37 : 제2리세스 38 : 실리콘게르마늄37: second recess 38: silicon germanium

39 : 스페이서39: spacer

본 발명은 반도체 소자 제조 기술에 관한 것으로, 특히 반도체 소자의 PMOSFET 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device manufacturing technology, and more particularly, to a PMOSFET manufacturing method of a semiconductor device.

최근 반도체 소자의 동작 전류를 증가시키기 위해서 소자에 기계적 스트레스를 가하여 채널 영역에 스트레인(Strain)을 조절하는 방법이 연구되고 있다. 즉,채널영역에 일정한 스트레인이 형성되면 캐리어(Carrier)들의 이동성(mobility)이 영향 받는 것을 이용하여 동작 전류를 향상시키는 것이다. Recently, in order to increase the operating current of a semiconductor device, a method of controlling strain in a channel region by applying mechanical stress to the device has been studied. That is, when a constant strain is formed in the channel region, the mobility of the carriers is affected to improve the operating current by using the influence of the mobility of the carriers.

특히, PMOS채널 영역에 압축성 변형(Compressive Strain)이 형성되면 정공 캐리어(Hole carrier)들의 이동성이 향상된다. In particular, when compressive strain is formed in the PMOS channel region, mobility of hole carriers is improved.

도 1은 종래 기술에 따른 반도체 소자의 제조방법을 나타내는 단면도이다.1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the prior art.

도 1에 도시된 바와 같이, 기판(11)에 소자분리막(12)이 형성되어 활성영역이 정의되고, 기판(11) 상에 게이트패턴(13)이 형성된다. 여기서, 게이트패턴(13)은 폴리실리콘전극(13A), 텅스텐전극(13B) 및 게이트하드마스크(13C)의 적층구조로 형성된다. 그리고, 게이트패턴(13)을 포함하는 전면에 절연막(14)이 형성되고, 게이트패턴(13)의 측벽의 절연막(14) 상에 스페이서(15)이 형성된다. 그리고, 스페이서(15)과 소자분리막(12) 사이의 기판이 일부 리세스되고, 실리콘게르마늄(16)이 형성된 소스/드레인영역이 형성된다.As shown in FIG. 1, an isolation region 12 is formed on a substrate 11 to define an active region, and a gate pattern 13 is formed on the substrate 11. Here, the gate pattern 13 is formed in a stacked structure of the polysilicon electrode 13A, the tungsten electrode 13B, and the gate hard mask 13C. The insulating film 14 is formed on the entire surface including the gate pattern 13, and the spacer 15 is formed on the insulating film 14 on the sidewall of the gate pattern 13. The substrate between the spacer 15 and the device isolation layer 12 is partially recessed to form a source / drain region in which the silicon germanium 16 is formed.

위와 같이, 종래 기술은 스페이서(15)을 배리어로 소스/드레인 영역의 기판을 리세스한 후, 실리콘게리마늄(SiGe)를 성장시켜 압축성 변형을 채널에 형성한다.As described above, the prior art recesses the substrate of the source / drain region with the spacer 15 as a barrier, and then grows silicon germanium (SiGe) to form compressive strain in the channel.

그러나, 소스/드레인 영역에만 한정적으로 실리콘게르마늄을 형성하면 채널(Channel)영역에 가해지는 압축성 변형이 게이트 채널영역과 소스/드레인에 형성된 실리콘게르마늄 사이의 거리에 따라 의존하게 되어 압축성 변형을 향상시키는데 한계가 있다.However, if silicon germanium is formed only in the source / drain region, the compressive strain applied to the channel region depends on the distance between the gate channel region and the silicon germanium formed in the source / drain, which limits the compressive strain. There is.

도 2는 게이트와 소스/드레인 거리에 따른 채널 스트레인 변화를 나타내는 그래프이다.2 is a graph showing channel strain variation according to gate and source / drain distances.

도 2를 참조하면, 게이트와 소스/드레인 간의 거리가 10㎚에서 30㎚로 올라가면 채널 스트레인(Channel Strain)이 -830에서 -750으로 줄어드는 것을 알 수 있다.Referring to FIG. 2, it can be seen that as the distance between the gate and the source / drain increases from 10 nm to 30 nm, the channel strain decreases from -830 to -750.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 소자의 동작속도를 향상시키기 위해 채널영역에 큰 압축성 변형을 형성하기 위한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device for forming a large compressive strain in the channel region in order to improve the operation speed of the device.

본 발명에 의한 반도체 소자의 제조방법은 기판 상에 게이트패턴을 형성하는 단계, 상기 게이트패턴을 포함하는 기판 상에 분리보호막을 형성하는 단계, 상기 게이트패턴 측벽의 상기 분리보호막 상에 더미스페이서를 형성하는 단계, 상기 더미스페이서를 이용하여 상기 기판을 제1리세스하는 단계, 상기 더미스페이서를 제거하는 단계, 상기 분리보호막을 이용하여 상기 기판을 제2리세스하는 단계, 상기 제1 및 제2리세스에 실리콘게르마늄을 성장시키는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention includes forming a gate pattern on a substrate, forming a separation protective film on a substrate including the gate pattern, and forming a dummy spacer on the separation protection film on the sidewall of the gate pattern. And first recessing the substrate using the dummy spacers, removing the dummy spacers, and second recessing the substrate using the separation protection layer, the first and second recesses. And growing silicon germanium in the seth.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 3a 내지 도 3g는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

도 3a에 도시된 바와 같이, 기판(31)에 소자분리막(32)을 형성한다. 여기서, 기판(31)은 DRAM공정이 진행되는 기판일 수 있고 특히, PMOS영역의 기판일 수 있다. 또한, 소자분리막(32)은 STI(Shallow Trench Isolation) 공정으로 형성할 수 있다.As shown in FIG. 3A, the device isolation layer 32 is formed on the substrate 31. Here, the substrate 31 may be a substrate on which a DRAM process is performed, and in particular, may be a substrate of a PMOS region. In addition, the device isolation layer 32 may be formed by a shallow trench isolation (STI) process.

이어서, 소자분리막(32) 형성된 기판(31) 상에 게이트패턴(33)을 형성한다. 여기서, 게이트패턴(33)은 폴리실리콘전극(33A), 금속계 전극(33B)과 게이트하드마스크(33C)의 적층구조로 형성할 수 있는데, 금속계 전극은 금속 또는 금속실리사이드일 수 있고, 금속은 텅스텐, 금속실리사이드는 텅스텐실리사이드일 수 있으며, 게이트하드마스크(33C)는 질화막일 수 있다.Subsequently, a gate pattern 33 is formed on the substrate 31 on which the device isolation film 32 is formed. Here, the gate pattern 33 may be formed of a laminated structure of the polysilicon electrode 33A, the metal electrode 33B, and the gate hard mask 33C. The metal electrode may be metal or metal silicide, and the metal may be tungsten. The metal silicide may be tungsten silicide, and the gate hard mask 33C may be a nitride film.

이어서, 게이트패턴(33)을 포함하는 결과물의 전면에 분리보호막(34)을 형성한다. 여기서, 분리보호막(34)은 LDD(Lightly Doped Drain) 확장영역(Extension)을 게이트패턴(33)의 에지(edge)와 물리적으로 분리시키기 위한 것으로, 후속 더미스페이서와 식각선택비를 갖는 절연물질로 형성하되 Si3N4, SiBN 및 SiON의 그룹 중에서 선택된 어느 하나로 형성할 수 있다. Subsequently, a separation protective film 34 is formed on the entire surface of the resultant product including the gate pattern 33. Here, the isolation protection layer 34 is to physically separate the LDD (Lightly Doped Drain) extension from the edge of the gate pattern 33, and is an insulating material having an etching selectivity with a subsequent dummy spacer. To form, but may be formed of any one selected from the group of Si 3 N 4 , SiBN and SiON.

또한, 분리보호막(34)은 화학기상증착법(Chemical Vapor Deposition) 또는 원자층증착법(Atomic Layer Deposition)으로 형성할 수 있다. 그리고, 분리보호막(34)의 두께는 최적의 LDD(Low Doped Drain) 확장영역 및 채널(Channel)영역의 압축성변형(Compressive Strain)을 조절할 수 있는 두께로 형성하되 25Å∼250Å의 두께로 형성할 수 있다.In addition, the separation protective layer 34 may be formed by chemical vapor deposition or atomic layer deposition. In addition, the thickness of the separation protective layer 34 may be formed to a thickness that can adjust the compressive strain of the optimal low doped drain (LDD) extension region and the channel region, but may be formed to a thickness of 25 μs to 250 μs. have.

도 3b에 도시된 바와 같이, 게이트패턴(33)의 측벽의 분리보호막(34) 상에 더미스페이서(35)를 형성한다. 여기서, 더미스페이서(35)는 후속 LDD영역과 소스/드레인영역의 제1 및 제2리세스 깊이를 다르게 형성하여 최적의 압축성 변형을 형성하기 위한 것으로, 100Å∼800Å의 두께로 형성할 수 있다.As shown in FIG. 3B, a dummy spacer 35 is formed on the separation protection layer 34 on the sidewall of the gate pattern 33. Here, the dummy spacer 35 is formed to form an optimal compressive strain by differently forming the first and second recess depths of the subsequent LDD region and the source / drain region.

더미스페이서(35)는 분리보호막(34) 상에 실리콘산화막(SiO2)을 형성하고 에치백(Etch back)을 실시하여 게이트패턴(33) 측벽의 분리보호막(34) 상에 잔류시킴으로 형성할 수 있다.The dummy spacer 35 may be formed by forming a silicon oxide film (SiO 2 ) on the separation protective film 34 and etching the same, and remaining on the separation protection film 34 on the sidewall of the gate pattern 33. have.

도 3c에 도시된 바와 같이, 더미스페이서(35)를 배리어로 소자분리막(32)과 더미스페이서(35) 사이의 기판(31)을 제1리세스(36)한다.As shown in FIG. 3C, the substrate 31 between the device isolation layer 32 and the dummy spacer 35 is first recessed 36 using the dummy spacer 35 as a barrier.

여기서, 제1리세스(36)는 소스/드레인영역에 해당하는 것으로, 압축성 변형 및 단채널효과(Short Channel Effect)를 고려하여 100Å∼2000Å의 깊이로 형성한 다.Here, the first recess 36 corresponds to a source / drain region, and is formed to have a depth of 100 μs to 2000 μs in consideration of compressive deformation and short channel effects.

도 3d에 도시된 바와 같이, 더미스페이서(35)를 제거한다. 여기서, 더미스페이서(35)는 습식식각으로 제거할 수 있다. 이때, 분리보호막(34)은 더미스페이서(35)와 식각선택비를 갖고 형성되었기 때문에 제거되지 않고 그대로 잔류한다.As shown in FIG. 3D, the dummy spacer 35 is removed. Here, the dummy spacer 35 may be removed by wet etching. At this time, since the separation protective layer 34 is formed with the dummy spacer 35 and the etching selectivity, the separation protective layer 34 is not removed and remains as it is.

도 3e에 도시된 바와 같이, 게이트패턴(33)을 배리어로 기판(31)을 식각하여 제2리세스(37)를 형성한다. 이때, 게이트패턴(33)의 측벽은 분리보호막(34)이 형성되어 있기 때문에 제2리세스(37) 형성시 게이트패턴(33)의 에지(Edge)와 LDD영역인 제2리세스(37)를 물리적으로 분리할 수 있다.As shown in FIG. 3E, the substrate 31 is etched using the gate pattern 33 as a barrier to form the second recess 37. In this case, since the isolation protection layer 34 is formed on the sidewall of the gate pattern 33, the edge of the gate pattern 33 and the second recess 37, which is an LDD region, are formed when the second recess 37 is formed. Can be physically separated.

여기서, 제2리세스(37)는 제1리세스(36)보다 얕은 깊이로 형성하되, 압축성 변형 및 단채널효과(Short Channel Effect)를 고려하여 20Å∼500Å의 깊이로 형성한다. 즉, 소스/드레인영역의 제1리세스(36)는 깊게 형성함으로써 후속 실리콘게르마늄의 성장이 많이 되도록 하여 압축성 변형을 크게 하고, LDD영역의 제2리세스(37)는 얕은 깊이로 형성함으로써 얕은 접합을 형성해줄 수 있다.Here, the second recess 37 is formed to be shallower than the first recess 36, but is formed to a depth of 20 μs to 500 μs in consideration of compressive deformation and a short channel effect. That is, the first recess 36 of the source / drain regions is deeply formed to increase the growth of subsequent silicon germanium to increase the compressive deformation, and the second recess 37 of the LDD region is shallow to form shallow. It can form a junction.

특히, 게이트패턴(33)을 배리어로 제2리세스(37)를 형성하는 공정에서 게이트패턴(33) 상부의 분리보호막(34)은 기판(31) 상부에 형성된 분리보호막(34)의 식각시 함께 식각되지만, 게이트패턴(33)의 측벽에는 분리보호막(34)이 잔류하기 때문에 게이트패턴(33)의 에지(Edge)와 LDD영역인 제2리세스(37)를 물리적으로 분리할 수 있다.In particular, in the process of forming the second recess 37 using the gate pattern 33 as a barrier, the separation protection layer 34 on the gate pattern 33 may be formed during etching of the separation protection layer 34 formed on the substrate 31. Although etched together, the isolation protective layer 34 remains on the sidewall of the gate pattern 33, so that the edge of the gate pattern 33 and the second recess 37, which is an LDD region, may be physically separated.

도 3f에 도시된 바와 같이, 제1 및 제2리세스(36, 37)에 실리콘게르마늄(SiGe, 38)을 성장시킨다. 여기서, 실리콘게르마늄(38)은 에피택셜 성 장(Epitaxial growth)으로 형성하는데, 압축성 변형을 조절하기 위해 실리콘게르마늄(38) 막 내의 게르마늄 농도를 5％∼50％로 조절할 수 있다.As shown in FIG. 3F, silicon germanium (SiGe) 38 is grown in the first and second recesses 36 and 37. Here, the silicon germanium 38 is formed by epitaxial growth, and in order to control compressive deformation, the germanium concentration in the silicon germanium 38 film may be adjusted to 5% to 50%.

또한, 단채널효과 마진을 향상시키기 위해 실리콘게르마늄(38)의 성장과 동시에 인시튜(In-Situ)로 보론(B)을 도핑할 수 있다. 이때, 보론(B)은 1E18/㎠∼4E20/㎠의 농도를 도핑할 수 있다.In addition, in order to improve the short channel effect margin, the growth of the silicon germanium 38 may be simultaneously doped with boron (B) in-situ (In-Situ). At this time, the boron (B) may be doped with a concentration of 1E18 / cm 2 ~ 4E20 / cm 2.

위와 같이, 채널영역에 체적이 실리콘(Silicon)에 비하여 상대적으로 큰 실리콘게르마늄(38)을 에피택셜 성장시킴으로써 채널영역에 압축성 변형을 형성하여 소자의 동작 속도를 향상하고, 더욱이 소스/드레인영역 뿐 아니라 LDD영역에 까지 실리콘게르마늄(38)을 형성함으로써 게이트패턴(33)과 소스/드레인영역 간의 거리에 의존하는 압축성 변형 특성이 향상되어 소자의 동작 속도를 향상시킬 수 있다.As described above, by epitaxially growing silicon germanium 38 having a larger volume in the channel region than silicon, a compressive strain is formed in the channel region to improve the operation speed of the device, and furthermore, not only the source / drain region but also By forming the silicon germanium 38 up to the LDD region, the compressive deformation characteristic depending on the distance between the gate pattern 33 and the source / drain region can be improved, thereby improving the operation speed of the device.

도 3g에 도시된 바와 같이, 게이트패턴(33)의 측벽에 스페이서(39)를 형성한다. 여기서, 스페이서(39)는 질화막으로 형성할 수 있다.As shown in FIG. 3G, spacers 39 are formed on sidewalls of the gate pattern 33. Here, the spacer 39 may be formed of a nitride film.

본 발명은 실리콘게르마늄(38)을 소스/드레인영역 뿐 아니라 LDD영역까지 성장시킬 수 있어서 높은 압축성 변형을 채널 영역에 형성할 수 있으며, 이로 인해 소자의 동작 속도를 향상시킬 수 있는 장점이 있다.According to the present invention, the silicon germanium 38 can be grown not only in the source / drain region but also in the LDD region, so that a high compressive strain can be formed in the channel region, thereby improving the operation speed of the device.

또한, 분리보호막(34)과 더미스페이서(35)의 두께를 조절하여 LDD영역과 소스/드레인영역의 제1 및 제2리세스(36, 37)의 깊이 및 간격을 조절할 수 있기 때문에 최적의 소자 특성을 얻을 수 있는 장점이 있다.In addition, it is possible to adjust the thickness of the separation protective layer 34 and the dummy spacer 35 to control the depth and spacing of the first and second recesses 36 and 37 of the LDD region and the source / drain region. There is an advantage to get the characteristics.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으 나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 소스/드레인영역 및 LDD영역에 실리콘게르마늄을 형성하여 큰 압축성변형을 채널영역에 형성함으로써 소자의 동작 속도를 향상시킬 수 있는 효과가 있다.The present invention described above has the effect of improving the operation speed of the device by forming silicon germanium in the source / drain region and the LDD region to form a large compressive strain in the channel region.

Claims (14)

기판 상에 게이트패턴을 형성하는 단계;Forming a gate pattern on the substrate; 상기 게이트패턴을 포함하는 기판 상에 분리보호막을 형성하는 단계;Forming a separation protection film on the substrate including the gate pattern; 상기 게이트패턴 측벽의 상기 분리보호막 상에 더미스페이서를 형성하는 단계;Forming a dummy spacer on the separation protective layer on the sidewalls of the gate pattern; 상기 더미스페이서를 이용하여 상기 기판을 제1리세스하는 단계;First recessing the substrate using the dummy spacer; 상기 더미스페이서를 제거하는 단계;Removing the dummy spacer; 상기 분리보호막을 이용하여 상기 기판을 제2리세스하는 단계; 및Second recessing the substrate using the separation protection film; And 상기 제1 및 제2리세스에 실리콘게르마늄을 성장시키는 단계Growing silicon germanium in the first and second recesses 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 더미스페이서를 형성하는 단계는,Forming the dummy spacer, 상기 분리보호막을 포함하는 결과물의 전면에 실리콘산화막을 형성하는 단계; 및Forming a silicon oxide film on the entire surface of the resultant including the separation protective film; And 에치백을 실시하여 상기 실리콘산화막을 상기 게이트패턴 측벽의 상기 분리보호막 상에 잔류시키는 단계Etching back to leave the silicon oxide layer on the isolation protective layer on the sidewall of the gate pattern 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제2항에 있어서,The method of claim 2, 상기 실리콘산화막은 100Å∼800Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The silicon oxide film is a semiconductor device manufacturing method, characterized in that formed in a thickness of 100 ~ 800Å. 제1항에 있어서,The method of claim 1, 상기 제2리세스는 상기 제1리세스보다 얕은 깊이로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.And the second recess is formed to have a depth shallower than that of the first recess. 제4항에 있어서,The method of claim 4, wherein 상기 제1리세스는 100Å∼2000Å의 깊이로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The first recess is formed in a depth of 100 ~ 2000Å, the manufacturing method of a semiconductor device. 제5항에 있어서,The method of claim 5, 상기 제2리세스는 20Å∼500Å의 깊이로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.And the second recess is formed to a depth of 20 kPa to 500 kPa. 제1항에 있어서,The method of claim 1, 상기 더미스페이서를 제거하는 단계는,Removing the dummy spacer, 습식식각으로 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, characterized in that the wet etching. 제1항에 있어서,The method of claim 1, 상기 실리콘게르마늄을 성장시키는 단계는,The step of growing the silicon germanium, 상기 제1 및 제2리세스에 실리콘게르마늄을 에피택셜 성장시키는 것을 특징으로 하는 반도체 소자의 제조방법.And epitaxially grow silicon germanium in the first and second recesses. 제8항에 있어서,The method of claim 8, 상기 실리콘게르마늄에서 게르마늄(Ge)의 농도는 5％∼50％인 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device, characterized in that the concentration of germanium (Ge) in the silicon germanium is 5% to 50%. 제9항에 있어서,The method of claim 9, 상기 실리콘게르마늄을 성장시키는 단계는,The step of growing the silicon germanium, 상기 실리콘게르마늄의 형성과 동시에 인시튜(In-Situ)로 보론을 도핑하고, 보론은 1E18/㎠∼4E20/㎠의 농도를 도핑하는 것을 특징으로 하는 반도체 소자의 제조방법.Forming a silicon germanium and simultaneously doping boron in-situ, and boron doping a concentration of 1E18 / cm 2 to 4E20 / cm 2. 제1항에 있어서,The method of claim 1, 상기 실리콘게르마늄을 성장시키는 단계 후,After growing the silicon germanium, 게이트패턴의 측벽에 스페이서를 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.And forming a spacer on sidewalls of the gate pattern. 제1항에 있어서,The method of claim 1, 상기 분리보호막은 실리콘산화막과 식각선택비를 갖는 물질로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The separation protective film is a semiconductor device manufacturing method, characterized in that formed with a material having a silicon oxide film and an etching selectivity. 제12항에 있어서,The method of claim 12, 상기 분리보호막은 Si3N4, SiBN 및 SiON의 그룹 중에서 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The separation protective film is a semiconductor device manufacturing method, characterized in that formed in any one selected from the group of Si 3 N 4 , SiBN and SiON. 제13항에 있어서,The method of claim 13, 상기 분리보호막은 화학기상증착법(Chemical Vapor Deposition) 또는 원자층증착법(Atomic Layer Deposition)으로 형성하고 20Å∼250Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The separation protective film is formed by a chemical vapor deposition (Chemical Vapor Deposition) or atomic layer deposition (Atomic Layer Deposition) method of manufacturing a semiconductor device, characterized in that formed in a thickness of 20 ~ 250Å.
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KR20060005259A (en) * 2004-07-12 2006-01-17 삼성전자주식회사 Method of forming a mos transistor having fully silicided metal gate electrode
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KR100632465B1 (en) 2005-07-26 2006-10-09 삼성전자주식회사 Semiconductor device and fabrication method thereof

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