KR100939154B1 - Non-volatile latch circuit and system on chip with the same - Google Patents

Abstract

The present invention relates to a nonvolatile latch circuit and a system-on-chip including the same, and discloses a technique of a latch circuit requiring no separate data storage time by detecting a change in latch data in an active period and storing new data in the latch. The present invention detects whether the latch data is changed in the active period without having a separate data storage section, and when a change in the latch data is detected, the new data is stored in the nonvolatile latch in a nonvolatile state, thereby providing power at any moment. When the off occurs, new data is always stored in the nonvolatile latch unit, thereby preventing data loss and improving the operation speed by eliminating the need for booting time for data recovery.

Description

Non-volatile latch circuit and system on chip comprising the same

1 is a graph for explaining a change in power consumption of a conventional semiconductor chip.

2 is a circuit diagram of a conventional nonvolatile latch circuit.

3 is a view for explaining a data storage / recall method of a conventional nonvolatile latch circuit.

4 is a system-on-chip configuration including a nonvolatile latch circuit in accordance with the present invention.

5 is a diagram for explaining a data storage / recall method of a nonvolatile latch circuit according to the present invention;

6 is a block diagram of a nonvolatile latch circuit according to the present invention;

FIG. 7 is a detailed circuit diagram of the nonvolatile latch unit of FIG. 6. FIG.

FIG. 8 is a detailed circuit diagram of the nonvolatile storage of FIG. 7. FIG.

9 and 10 are detailed circuit diagrams and operation timing diagrams of the input control unit of FIG. 8;

11 and 12 illustrate another embodiment of the input control unit of FIG. 8.

FIG. 13 is a detailed circuit diagram illustrating a storage unit of FIG. 8. FIG.

14 is another embodiment of the storage of FIG. 8;

15 and 16A and 16B are detailed circuit diagrams and operation timing diagrams of the storage / recall control section of FIG. 6;

Fig. 17 is an operation timing diagram during a power-on reset operation of the nonvolatile latch circuit according to the present invention.

18 is an operation timing diagram at the time of data storage of the nonvolatile latch circuit according to the present invention;

The present invention relates to a nonvolatile latch circuit and a system on chip including the same, and to detect a change in latch data in an active period and store new data in a latch so that a separate system booting process is unnecessary at power off.

1 is a graph illustrating a change in power consumption of a chip due to a conventional nanoscale device shrink.

Referring to the graph of FIG. 1, when a technology node representing a design rule of a device is large, an active current which is an operating current of a system on a chip (SOC) is in a standby state of an inoperative state. It can be seen that the current consumption is much higher than the current (Standby).

However, as the device size decreases, the active current shows a gentle increase while the standby current (e.g., 90nm) shows a sharp increase. This aspect means that the leakage current component on the sub-threshold voltage (Vt) that is the non-switching current increases more rapidly than the increase of the switching current that is the main component of the active current. That is, the leakage current penetrating through the CMOS rapidly increases in a standby state where power is applied and the chip does not operate.

Therefore, in the standby mode, shutting off the power supply of the chip is one method of reducing the power consumption of the chip. In this case, when the power of the chip is cut off, a circuit capable of storing and recalling the previous circuit state is needed in order to restore the circuit state before the block.

The conventional circuit which stores the previous state of the circuit at the time of power off of the chip is the nonvolatile latch circuit shown in FIG.

The conventional nonvolatile latch circuit includes a plurality of inverters IV1 to IV8, NMOS transistors SW1 and SW2 and a capacitor unit 10.

Here, inverter IV1 inverts data D in synchronization with clock CK. Latch R1 includes inverters IV2 and IV3 having a latch structure to latch the output of inverter IV1 in synchronization with clock / CK. Inverter IV4 inverts the output of latch R1 in synchronization with clock / CK. The latch R2 includes inverters IV5 and IV6 having a latch structure to latch the output of the inverter IV4 to output data Q.

The NMOS transistors SW1 and SW2 selectively connect the latch R1 and the capacitor unit 10 according to the switching signal SS. The capacitor unit 10 includes a plurality of nonvolatile ferroelectric capacitors FC1 to FC4. At this time, the nonvolatile ferroelectric capacitors FC1 and FC2 store the output of the plate line / PL1 inverted by the inverter IV7. The nonvolatile ferroelectric capacitors FC3 and FC4 store the output of the plate line / PL2 inverted by the inverter IV8.

The conventional nonvolatile latch circuit having such a configuration is provided in each circuit functional region in the system on chip to store nonvolatile data in the turn-on state of the power supply switch at power off. That is, the data is stored in the capacitor unit 10 through separate latches R1 and R2 before the power switch is turned off, or the previous data is restored during the power-on operation.

3 is a view for explaining a data storage / recall method of a conventional nonvolatile latch circuit.

The conventional nonvolatile latch circuit stores the states of the latches R1 and R2 in the storage unit during the storage period when entering the power-off mode, and restores the data stored in the latches R1 and R2 during the recall period during the power-on mode entering. do.

However, such a conventional nonvolatile latch circuit stores previous data only in a preset power off mode. Accordingly, when an accidental power-off state occurs during the active period, the latch data in the active state is lost and data recovery is impossible.

The present invention has been made to solve the above problems, and has the following object.

First, the present invention does not have a separate data storage section, and detects a change in latch data in the active section and stores new data in the latch so that a separate system booting process is unnecessary at power off.

Second, the purpose of the present invention is to reduce the boot time for data recovery by changing the latch structure inside the system on chip (SOC) to a nonvolatile structure.

According to an aspect of the present invention, there is provided a nonvolatile latch circuit including: an input driver configured to sequentially invert an input signal to output first and second control signals having different phases; A precharge processor for equalizing both ends of the output node when the clock is inactivated; An input processor for generating a voltage difference across the output node according to the first and second control signals when the clock is activated; An amplifier for amplifying the voltage level of the output node when the input processor is activated; And an output latch processing unit for storing a pull-up or pull-down voltage level according to the voltage level of the output node, and storing the data of the output node in a non-volatile state according to the latch transition detection signal. A pull-up driving device for selectively supplying a power supply voltage by switching according to an output signal of one terminal; A pull-down driving device for selectively supplying a ground voltage by switching according to the inversion signal of the second terminal of the output node; And a nonvolatile storage unit for storing the output of the pull-up driving device or the pull-down driving device in a non-volatile state according to the latch transition detection signal, wherein the nonvolatile storage unit includes an output of the pull-up driving device and the pull-down driving device, a latch transition detection signal, An input control unit outputting a data control signal according to a power-on reset signal; And a storage unit which stores the data control signal in the nonvolatile ferroelectric capacitor according to the state of the latch transition detection signal and the storage control signals.

In addition, the system-on-chip including the nonvolatile latch circuit of the present invention detects whether or not the latch data stored in the latch is transitioned during the active period in which the clock is activated, generates a latch transition detection signal, and generates a latch transition detection signal and a power-on. A nonvolatile latch circuit for storing and restoring changed latch data in the nonvolatile ferroelectric capacitor according to a reset signal; And a plurality of nonvolatile latch circuits in respective circuit functional regions in the chip to hold the logic state of the latch data regardless of whether power is supplied or not, and the nonvolatile latch circuit inverts the input signal sequentially and phases. An input driver for outputting different first and second control signals; A precharge processor for equalizing both ends of the output node when the clock is inactivated; An input processor for generating a voltage difference across the output node according to the first and second control signals when the clock is activated; An amplifier for amplifying the voltage level of the output node when the input processor is activated; And an output latch processing unit for storing a pull-up or pull-down voltage level according to the voltage level of the output node, and storing the data of the output node in a non-volatile state according to the latch transition detection signal. A pull-up driving device for selectively supplying a power supply voltage by switching according to an output signal of one terminal; A pull-down driving device for selectively supplying a ground voltage by switching according to the inversion signal of the second terminal of the output node; And a nonvolatile storage unit for storing the output of the pull-up driving device or the pull-down driving device in a non-volatile state according to the latch transition detection signal, wherein the nonvolatile storage unit includes an output of the pull-up driving device and the pull-down driving device, a latch transition detection signal, An input control unit outputting a data control signal according to a power-on reset signal; And a storage unit which stores the data control signal in the nonvolatile ferroelectric capacitor according to the state of the latch transition detection signal and the storage control signals.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4 is a block diagram illustrating a system on chip including a nonvolatile latch circuit according to the present invention.

The nonvolatile latch NVL of the present invention is provided in each circuit function region in a system on a chip (SOC), and is a logic state in a turn-on state of a power supply switch during a power-off operation in which the power supply switch is turned off. Will be saved.

5 is a view for explaining a data storage / recall method of a nonvolatile latch circuit according to the present invention.

The present invention does not include a data storage section before entering the power off mode. Then, the latch transition detection signal LTD is generated by detecting the change of the latch data in the active section, and new data is frequently stored in the nonvolatile latch NVL. In addition, the data stored in the latch is recovered during the recall period.

Accordingly, even when an accidental power-off occurs at any moment, new data is always stored in the nonvolatile latch NVL so that a separate data storage time is not consumed.

6 is a configuration diagram of a nonvolatile latch circuit NVL according to the present invention.

The present invention includes a nonvolatile latch unit 100, a latch transition detection unit 200, and a storage and recall control unit 300.

Here, the nonvolatile latch unit 100 latches the input signal LAT_IN according to the clock CLK, the pull-up enable signal ENP, the pull-down enable signal ENN, and the cell plate signal CPL to output the output signal LAT_OUT. Here, the clock CLK is an activation signal for latching data input to the nonvolatile latch unit 100.

The latch transition detection unit 200 detects whether the output signal LAT_OUT has transitioned, and generates a latch transition detection signal LTD that is a single pulse signal when the latch data transitions. The storage / recall control unit 300 pull-up enable signal ENP and pull-down enable signal ENN for controlling data storage and recall operation of the nonvolatile latch unit 100 according to the power-on reset signal POR and the latch transition detection signal LTD. And the cell plate signal CPL.

FIG. 7 is a detailed circuit diagram illustrating the nonvolatile latch unit 100 of FIG. 6.

The nonvolatile latch unit 100 includes an input driver 110, a precharge processor 120, an amplifier 130, an input processor 140, and an output latch processor 150.

Here, the input driver 110 includes inverters IV9 and IV10. The inverter IV9 inverts the input signal LAT_IN and outputs the control signal SB. The inverter IV10 inverts the control signal SB and outputs the control signal S. FIG.

The precharge processor 120 includes pull-up PMOS transistors P1 and P2 and precharge PMOS transistor P3 for equalization. Here, the PMOS transistors P1 and P2 are connected between the power supply voltage VDD applying terminal and the nodes LN1 and LN2, respectively, and the clock CLK is applied through the common gate terminal. The PMOS transistor P3 is connected between the nodes LN1 and LN2 so that the clock CLK is applied through the gate terminal.

The amplifier 130 includes PMOS transistors P4 and P5 and NMOS transistors N1 and N2 connected in a cross-coupled form to amplify the output of the input processor 140. Here, the PMOS transistors P4 and P5 are connected between the supply voltage VDD terminal and the nodes LN1 and LN2, respectively, the gate terminal of the PMOS transistor P4 is connected to the node LN2, and the gate terminal of the PMOS transistor P5 is connected to the node LN1.

The NMOS transistors N1 and N2 are connected between the nodes LN1, LN2 and the NMOS transistors N3 and N4, respectively, the gate terminal of the NMOS transistor N1 is connected to the node LN2, and the gate terminal of the NMOS transistor N2 is connected to the node LN1. Here, the output nodes LN1 and LN2 are precharged to a high level when the clock CLK becomes low by the precharge processor 120.

The input processor 140 includes a plurality of NMOS transistors N3 to N5.

Here, the NMOS transistors N3 and N4 are connected between the NMOS transistors N1 and N2 and the NMOS transistor N5, and the control signals S and SB are applied through the respective gate terminals. The NMOS transistor N5 is connected between the NMOS transistors N3 and N4 and the ground voltage terminal, and a specific frequency clock CLK is continuously applied through the gate terminal. The NMOS transistor N5 adjusts the activation states of the amplifier 130 and the input processor 140.

The output latch processor 150 includes inverters IV11 and IV12, a PMOS transistor P6, an NMOS transistor N6, and a nonvolatile storage unit 151.

Here, the PMOS transistor P6 is connected between the power supply voltage terminal and the node LN4 so that the gate terminal is connected to the node LN1. Accordingly, the PMOS transistor P6 adjusts the pullup of the node LN4 according to the voltage level of the node LN1. The NMOS transistor N6 is connected between node LN4 and the ground voltage terminal, and the output of inverter IV11 is applied through the gate terminal. Accordingly, the NMOS transistor N6 adjusts the pull-down of the node LN4 according to the voltage level of the node LN3.

The nonvolatile storage unit 151 stores the pullup / pulldown voltage of the node LN4 in a nonvolatile latch state and outputs the pullup / pulldown voltage to the node LN5. The inverter IV12 inverts the output of the node LN5 and outputs the output signal LAT_OUT.

8 is a detailed configuration diagram illustrating the nonvolatile storage unit 151 of FIG. 7.

The nonvolatile storage unit 151 includes an input control unit 152 and a storage unit 153.

Here, the input control unit 152 outputs the data control signals data_d and data_db according to the output of the node LN4, the latch transition detection signal LTD and the power-on reset signal POR. The data control signal data_db is an inversion signal of the data control signal data_d.

In addition, the storage unit 153 stores the data control signals data_d and data_db in a nonvolatile state according to the latch transition detection signal LTD, the pull-up enable signal ENP, the pull-down enable signal ENN, and the cell plate signal CPL. Will output

FIG. 9 is a detailed circuit diagram of the input controller 152 of FIG. 8.

The input control unit 152 includes NOR gates NOR1 and NOR2, an inverter IV13, and an NMOS transistor N7.

Here, the NOA gate NOR1 performs a NO operation on the output of the node LN4 inverted by the inverter IV13, the latch transition detection signal LTD and the power-on reset signal POR, and outputs the data control signal data_d. The NOA gate NOR2 performs a NO operation on the output of the node LN4, the latch transition detection signal LTD and the power-on reset signal POR, and outputs the data control signal data_db.

The operation of the input control unit 152 of FIG. 8 having such a configuration will be described below with reference to the operation timing diagram of FIG. 10.

First, the power-on reset signal POR rises to a high level. When the latch transition detection signal LTD is at a high level, the NMOS transistor N7 is turned on to maintain the data control signals data_d and data_db at a low level. Accordingly, the output node LN5 of the storage unit 153 maintains the low voltage level.

Thereafter, the power-on reset signal POR transitions to the low level. At this time, when the level of the node LN4 does not change while the latch transition detection signal LTD is at the high level, the data control signals data_d and data_db maintain the low level. Accordingly, the data of the node LN4 is transferred to the storage unit 153 so that the output node LN5 transitions to the high voltage level.

Subsequently, while the power-on reset signal POR maintains the low level, the latch transition detection signal LTD transitions to the low level. At this time, the level of the node LN4 is changed so that the data control signals data_d and data_db transition to the high level and the low level, respectively. Accordingly, the data of the node LN4 is transferred to the storage unit 153, so that the data of the output node LN5 transitions.

Next, while the power-on reset signal POR maintains a low level, the latch transition detection signal LTD transitions to a high level. At this time, when the level of the node LN4 does not change, the data control signals data_d and data_db all transition to a low level. Accordingly, the data of the node LN4 is transferred to the storage unit 153 to keep the data of the output node LN5 as it is.

FIG. 11 is another embodiment of the input control unit 152 of FIG. 8.

The input control unit 152 includes NAND gates ND1 and ND2, inverters IV14 to IV17, and an NMOS transistor N8.

Here, the NAND gate ND1 performs a NAND operation on the output of the node LN4 and the power-on reset signal POR inverted by the latch transition detection signal LTD and the inverter IV15. The inverter IV16 inverts the output of the NAND gate ND1 and outputs a data control signal data_d.

The NAND gate ND2 performs an NAND operation on the output of the node LN4 inverted by the inverter IV14 and the power-on reset signal POR inverted by the latch transition detection signal LTD and the inverter IV15. The inverter IV17 inverts the output of the NAND gate ND2 and outputs a data control signal data_db.

An operation of the input control unit 152 of FIG. 11 having such a configuration will be described below with reference to the operation timing diagram of FIG. 12.

First, when the power-on reset signal POR rises to a high level, and the latch transition detection signal LTD is at a low level, the NMOS transistor N7 is turned on to maintain the data control signals data_d and data_db at a low level. Accordingly, the output node LN5 of the storage unit 153 maintains the low voltage level.

Thereafter, the power-on reset signal POR transitions to the low level. At this time, when the level of the node LN4 does not change while the latch transition detection signal LTD is at the low level, the data control signals data_d and data_db maintain the low level. Accordingly, the data of the node LN4 is transferred to the storage unit 153 so that the output node LN5 transitions to the high voltage level.

Subsequently, while the power-on reset signal POR maintains the low level, the latch transition detection signal LTD transitions to the high level. At this time, the level of the node LN4 is changed so that the data control signals data_d and data_db transition to the high level and the low level, respectively. Accordingly, the data of the node LN4 is transferred to the storage unit 153, so that the data of the output node LN5 transitions.

Next, while the power-on reset signal POR maintains the low level, the latch transition detection signal LTD transitions to the low level. At this time, when the level of the node LN4 does not change, the data control signals data_d and data_db all transition to the low level. Accordingly, the data of the node LN4 is transferred to the storage unit 153 to keep the data of the output node LN5 as it is.

FIG. 13 is a detailed circuit diagram illustrating the storage unit 153 of FIG. 8.

The storage unit 153 includes a pull-up unit 400, a PMOS latch unit 410, an input / output unit 420, a nonvolatile ferroelectric capacitor unit 430, an NMOS latch unit 440, and a pull-down unit 450. do.

Here, the pull-up unit 400 includes a PMOS transistor P7. The PMOS transistor P7 is connected between the power supply voltage VCC applying terminal and the PMOS latch unit 410 to receive the pull-up enable signal ENP through the gate terminal.

The PMOS latch unit 410 includes PMOS transistors P8 and P9. The PMOS transistors P8 and P9 are connected between the PMOS transistor P7 and the input / output unit 420 so that the gate terminals are cross coupled.

The input / output unit 420 includes PMOS transistors P10 and P11. Here, the PMOS transistor P10 is connected between the node LN6 and the data control signal data_d applying end, and the latch transition detection signal LTD is applied through the gate terminal. The PMOS transistor P11 is connected between the node LN5 and the data control signal data_db applying end, and the latch transition detection signal LTD is applied through the gate terminal.

The nonvolatile ferroelectric capacitor unit 430 includes a plurality of nonvolatile ferroelectric capacitors FC5 to FC8. Here, the nonvolatile ferroelectric capacitors FC5 and FC6 are connected between the cell plate signal CPL applying terminal and the nodes LN6 and LN5, respectively, and the nonvolatile ferroelectric capacitors FC7 and FC8 are respectively connected between the nodes LN6, LN5 and the ground voltage terminal.

The NMOS latch unit 440 includes NMOS transistors N8 and N9. Here, the NMOS transistors N8 and N9 are connected between the NMOS transistor N10 and the nodes LN6 and LN5 so that the gate terminals are cross coupled. The pull-down unit 450 includes an NMOS transistor N10 connected between the NMOS latch unit 440 and the ground voltage terminal to which the pull-down enable signal ENN is applied through the gate terminal.

14 is another embodiment of the storage unit 153 of FIG. 8.

The storage unit 153 includes a pull-up unit 500, a PMOS latch unit 510, an input / output unit 520, a nonvolatile ferroelectric capacitor unit 530, an NMOS latch unit 540, and a pull-down unit 550. do.

Here, the pull-up unit 500 includes a PMOS transistor P12. The PMOS transistor P12 is connected between the power supply voltage VCC supply terminal and the PMOS latch unit 510 to receive the pull-up enable signal ENP through the gate terminal.

The PMOS latch unit 510 includes PMOS transistors P13 and P14. The PMOS transistors P13 and P14 are connected between the PMOS transistor P12 and the input / output unit 520 so that the gate terminals are cross coupled.

The input / output unit 520 includes NMOS transistors N11 and N12. Here, the NMOS transistor N11 is connected between the node LN6 and the data control signal data_d applying end, and the latch transition detection signal LTD is applied through the gate terminal. The NMOS transistor N12 is connected between the node LN5 and the data control signal data_db applying end, and the latch transition detection signal LTD is applied through the gate terminal.

The nonvolatile ferroelectric capacitor unit 530 includes a plurality of nonvolatile ferroelectric capacitors FC9 to FC12. Here, the nonvolatile ferroelectric capacitors FC9 and FC10 are connected between the cell plate signal CPL applying end and the nodes LN6 and LN5, respectively, and the nonvolatile ferroelectric capacitors FC11 and FC12 are respectively connected between the nodes LN6, LN5 and the ground voltage terminal.

The NMOS latch unit 540 includes NMOS transistors N13 and N14. Here, the NMOS transistors N13 and N14 are connected between the NMOS transistor N15 and the nodes LN6 and LN5 so that the gate terminals are cross coupled. The pull-down unit 550 includes an NMOS transistor N15 connected between the NMOS latch unit 540 and the ground voltage terminal to which the pull-down enable signal ENN is applied through the gate terminal.

FIG. 15 is a detailed circuit diagram of the storage and recall control unit 300 of FIG. 6.

The storage / recall control unit 300 includes delay units 310 and 320, NAND gates ND3 and ND4, and a plurality of inverters IV18 and IV21. Here, the delay unit 310 includes inverters IV19 and IV20. The delay unit 320 includes a plurality of inverters IV22 to IV25.

Inverter IV18 outputs the inverted power-on reset signal POR. The delay unit 310 delays the output of the inverter IV18 by a predetermined time and outputs the pull-down enable signal ENN. Inverter IV21 inverts pull-down enable signal ENN and outputs pull-up enable signal ENP.

The NAND gate ND3 performs a NAND operation on the power-on reset signal POR inverted by the inverter IV18 and the delay signal POR_d which is an output of the delay unit 320. The NAND gate ND4 performs a NAND operation on the output of the NAND gate ND3 and the latch transition detection signal LTD to output the cell plate signal CPL.

The operation of the storage and recall control unit 300 having such a configuration will be described below with reference to the timing diagrams of FIGS. 16A and 16B.

First, as shown in FIG. 16A, when the power-on reset signal POR transitions to a low voltage level, the delay signal POR_d delayed by the delay time of the delay unit 320 maintains a high level. At this time, the cell plate signal CPL transitions to the high level when the power-on reset signal POR transitions to the low level, and transitions to the low level when the delay signal POR_d transitions to the low level.

When the delay time of the delay unit 310 passes after the power-on reset signal POR transitions to the low voltage level, the pull-down enable signal ENN transitions to the high level. When the pull-down enable signal ENN transitions to a high level, the pull-up enable signal ENP transitions to a low level.

On the other hand, while the power-on reset signal POR maintains the low voltage level as shown in FIG. 16B, the latch transition detection signal LTD transitions to the low level. At this time, the cell plate signal CPL transitions to a high level.

When the latch transition detection signal LTD transitions to the high level again, the cell plate signal CPL transitions to the low level. At this time, the pull-down enable signal ENN maintains a high level, and the pull-up enable signal ENP maintains a low level.

17 is an operation timing diagram during a power-on reset operation of the nonvolatile latch circuit according to the present invention.

When the initial power-on power supply reaches the stable power supply voltage VCC level, the power-on reset signal POR is activated low. When the power-on reset signal POR is activated, the cell plate signal CPL detects this and transitions to a high level.

Therefore, the charge stored in the nonvolatile ferroelectric capacitors FC5 and FC6 of the storage unit 153 generates a voltage difference at the nodes LN6 and LN5 across the cell by the capacitance loads of the nonvolatile ferroelectric capacitors FC7 and FC8.

Subsequently, when a sufficient voltage difference is generated across the nodes LN6 and LN5, the pull-up enable signal ENP is activated low to turn on the PMOS transistor P7, and the pull-down enable signal ENN is activated high to turn on the NMOS transistor N10. . As a result, the PMOS latch unit 410 and the NMOS latch unit 440 amplify data of the nodes LN6 and LN5 across the cell.

Subsequently, when the amplification of the data is completed, the cell plate signal CPL transitions back to low to recover high data of the nonvolatile ferroelectric capacitor FC5 or the nonvolatile ferroelectric capacitor FC6.

18 is an operation timing diagram at the time of data storage of the nonvolatile latch circuit according to the present invention.

First, the latch transition detection unit 200 detects whether the content is changed in the output signal LAT_OUT of the nonvolatile latch unit 100 and generates a latch transition detection signal LTD in the form of a pulse when a change in the content is detected.

Thereafter, the storage / recall control unit 300 outputs the cell plate signal CPL and the pull-down enable signal ENN high to control the data storage and recovery operation according to the latch transition detection signal LTD, and pulls the pull-up enable signal ENP low. Will output

Meanwhile, when the clock is at the low level, the precharge processor 120 of the nonvolatile latch unit 100 equalizes the nodes LN1 and LN2 to the power supply voltage VDD level. When the clock CLK is at the high level, the input processor 140 operates to amplify the voltage levels of the output nodes LN1 and LN2 according to the levels of the control signals S and SB.

Next, the PMOS transistor P6 or the NMOS transistor N6 is selectively turned on according to the voltage levels of the output nodes LN1 and LN2 to determine the voltage level of the node LN4. The nonvolatile storage unit 151 stores the voltage level of the node LN4 in the nonvolatile ferroelectric capacitor unit 430 according to the cell plate signal CPL, the pull-down enable signal ENN, and the pull-up enable signal ENP.

The present invention stores the new data in the nonvolatile latch unit 100 when the change of the data is detected by detecting the change of the latch data in the active period without having a separate data storage section. Accordingly, when a power-off occurs at any moment, new data is always stored in the nonvolatile latch unit 100 to prevent data loss, and a boot time for data recovery is unnecessary.

The higher the performance of the system, the greater the utility of the nonvolatile latch circuit. Since the current system mainly utilizes the volatile latch, the latch structure of the system on chip (SOC) itself also uses the volatile characteristic. The present invention changes the latch structure inside the current system-on-chip (SOC) to a nonvolatile structure to reduce the boot time for data recovery.

As described above, the present invention allows the latch structure inside the system on chip (SOC) to be changed to a nonvolatile structure.

In addition, it does not have a separate data storage section, and detects a change in latch data in the active section and stores new data in the latch, thereby eliminating the need for a separate system booting process when powering off, thereby improving operation speed. To provide.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (18)

An input driver for sequentially inverting the input signal and outputting first and second control signals having different phases; A precharge processor for equalizing both ends of the output node when the clock is inactivated; An input processor for generating a voltage difference across the output node according to the first and second control signals when the clock is activated; An amplifier for amplifying a voltage level of the output node when the input processor is activated; And An output latch processor configured to store a pull-up or pull-down voltage level according to a voltage level of the output node, and to store data of the output node in a non-volatile state according to a latch transition detection signal, The output latch processing unit A pull-up driving element configured to switch according to an output signal of the first terminal of the output node to selectively supply a power supply voltage; A pull-down driving device for selectively supplying a ground voltage by switching according to an inversion signal of the second terminal of the output node; And A nonvolatile storage unit configured to store an output of the pull-up driving device or the pull-down driving device in a non-volatile state according to the latch transition detection signal, The nonvolatile storage unit An input control unit outputting a data control signal according to an output of the pull-up driving device and the pull-down driving device, and the latch transition detection signal and a power-on reset signal; And And a storage unit which stores the data control signal in a nonvolatile ferroelectric capacitor according to the state of the latch transition detection signal and the storage control signals. The method of claim 1, wherein the input driver First driving means for outputting the first control signal in accordance with the input signal; And And second driving means for driving an output of said first driving means to output said second control signal in phase opposite to said first control signal. The method of claim 1, wherein the precharge processing unit A pull-up transistor configured to pull up the output node to a power supply voltage level when the clock is inactivated; And And a precharge transistor for equalizing both ends of the output node when the clock is inactivated. The method of claim 1, wherein the amplification unit First and second driving devices connected between a power supply voltage supply terminal and both ends of the output node, respectively, and having a gate terminal cross coupled; And And third and fourth driving devices each having a coupling gate terminal cross-coupled between both ends of the output node and the input processing unit. The method of claim 1, wherein the input processing unit A fifth driving element selectively supplying a ground voltage according to the state of the clock; And And a sixth and seventh driving device connected between the amplifying unit and the fifth driving device to receive the first and second control signals through a gate terminal, respectively. The method of claim 1, wherein the output latch processing unit And a eighth driving device for driving an output of the nonvolatile storage unit. delete The nonvolatile latch circuit of claim 1, wherein the input controller outputs the data control signal at a ground voltage level in a section in which the latch transition detection signal becomes nonvolatile. The method of claim 1, wherein the input control unit A nonvolatile latch for activating and outputting the data control signal when the output of the pull-up driving device and the pull-down driving device is changed in a section in which the latch transition detection signal is generated after the power-on reset signal is activated Circuit. The method of claim 1 or 9, wherein the input control unit A first logical combination that logically combines the inverted signal of the first node to which the output of the pull-up driving device and the pull-down driving device are applied, the latch transition detection signal, and the power-on reset signal; Way; Second logical combining means for logically combining the output of the first node, the latch transition detection signal, and the power on reset signal to output a second data control signal that is in phase with the first data control signal; And And switching means for connecting an application node of the first data control signal and the second data control signal according to the power on reset signal. The method of claim 1, wherein the storage unit A pull-up unit configured to supply a power voltage when the pull-up enable signal is activated; A PMOS latch part connected between the pull-up part and both nodes of the cell, and having a gate terminal cross-coupled thereto; A pull-down unit configured to supply a ground voltage when the pull-down enable signal is activated; An input / output unit selectively supplying the data control signal to both ends of the cell according to the latch transition detection signal; A nonvolatile ferroelectric capacitor unit generating a voltage difference between nodes of the cell according to a cell plate signal; And And an NMOS latch portion connected between the nonvolatile ferroelectric capacitor portion and the pull-down portion, the gate terminal being cross coupled. 12. The nonvolatile latch circuit of claim 11, wherein the cell plate signal maintains an activation state during an activation period of a power-up detection signal when the latch transition detection signal is activated. The nonvolatile latch circuit of claim 1, wherein the storage control signals generate a cell plate signal, a pull-up enable signal, and a pull-down enable signal according to the latch transition detection signal. The nonvolatile latch circuit of claim 1, wherein the latch transition detection signal is generated in a pulse form when a level change of the output node occurs. It detects whether or not the latch data stored in the latch transitions during the active period when the clock is activated, generates a latch transition detection signal, and stores the changed latch data in the nonvolatile ferroelectric capacitor according to the latch transition detection signal and the power-on reset signal. A nonvolatile latch circuit for recovering this; And A plurality of nonvolatile latch circuits are provided in respective circuit functional regions in a chip to hold a logic state of the latch data regardless of whether power is supplied; The nonvolatile latch circuit An input driver for sequentially inverting the input signal and outputting first and second control signals having different phases; A precharge processor for equalizing both ends of an output node when the clock is inactivated; An input processor for generating a voltage difference across the output node according to the first and second control signals when the clock is activated; An amplifier for amplifying a voltage level of the output node when the input processor is activated; And An output latch processor configured to store a pull-up or pull-down voltage level according to a voltage level of the output node, and to store data of the output node in a non-volatile state according to the latch transition detection signal, The output latch processing unit A pull-up driving element configured to switch according to an output signal of the first terminal of the output node to selectively supply a power supply voltage; A pull-down driving device for selectively supplying a ground voltage by switching according to an inversion signal of the second terminal of the output node; And A nonvolatile storage unit configured to store an output of the pull-up driving device or the pull-down driving device in a non-volatile state according to the latch transition detection signal, The nonvolatile storage unit An input control unit for outputting the pull-up driving device and the pull-down driving device, and a data control signal according to the latch transition detection signal and the power-on reset signal; And And a storage unit configured to store the data control signal in the nonvolatile ferroelectric capacitor according to the state of the latch transition detection signal and the storage control signals. The method of claim 15, A latch transition detector for detecting whether a transition of an output signal output from the nonvolatile latch circuit is output and outputting the latch transition detection signal; And And a storage / recall control unit for storing data in the nonvolatile latch circuit and outputting the storage control signals for recovering the stored data according to the latch transition detection signal and the power on reset signal. A system on chip further comprising a latch circuit. 17. The system of claim 16, wherein the latch transition detection unit detects when a change in content occurs in the output signal and generates the latch transition detection signal in a pulse form. chip. 17. The non-volatile latch circuit of claim 16, wherein the storage / recall control unit generates the storage control signals including a cell plate signal, a pull-up, and a pull-down enable signal according to the latch transition detection signal. System-on-chip.

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