KR102226821B1 - Semiconductor device - Google Patents

Abstract

The present invention relates to a semiconductor device, and is a technology for reducing current consumption during power-on. The present invention generates a first sense amplifier drive signal and a second sense amplifier drive signal in response to a sense amplifier enable signal, and an application terminal of the first sense amplifier drive signal and the second sense amplifier drive signal in response to the blocking signal. A sense amplifier driving control unit that blocks leakage current generated in the sensor, a sense amplifier driving unit that selectively connects the first sense amplifier driving node and the second sense amplifier driving node in response to the first sense amplifier driving signal and the second sense amplifier driving signal. And a sense amplifier configured to sense and amplify a voltage difference between a pair of bit lines by receiving a first driving voltage and a second driving voltage through the first sense amplifier driving node and the second sense amplifier driving node.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device, and is a technology for reducing current consumption during power-on.

In general, a semiconductor memory device is configured to store data and output the stored data. In this case, the semiconductor memory device includes a memory cell for storing data, a bit line for transferring a voltage stored in the memory cell to a sense amplifier, and a sense amplifier for sensing and amplifying a voltage applied from the bit line.

Recently, various technologies have been studied to reduce the current consumption of semiconductor memory devices installed in portable systems such as mobile phones and notebook computers. In particular, technologies for reducing current consumed in the precharge mode as well as technologies for reducing current consumed in the active mode are being actively researched.

An embodiment of the present invention is characterized in that it is possible to block unnecessary leakage current by maintaining the output of the level shifter at a specific level for a predetermined time during a power-on operation.

A semiconductor device according to an embodiment of the present invention generates a first sense amplifier drive signal and a second sense amplifier drive signal in response to a sense amplifier enable signal, and generates a first sense amplifier drive signal and a second sense amplifier drive signal in response to a blocking signal. A sense amplifier driving control unit for blocking a leakage current generated at an application terminal of the sense amplifier driving signal; A sense amplifier driving unit selectively connecting the first sense amplifier driving node and the second sense amplifier driving node in response to the first sense amplifier driving signal and the second sense amplifier driving signal; And a sense amplifier that senses and amplifies a voltage difference between a pair of bit lines by receiving a first driving voltage and a second driving voltage through the first sense amplifier driving node and the second sense amplifier driving node, wherein the blocking signal is powered on. During operation, the voltage level rises, maintains a specific voltage level for a certain period of time, and transitions to the ground voltage level when the power supply voltage level is maintained at the specific voltage level.

The embodiment of the present invention provides an effect of normally controlling an abnormal output of a level shifter during initial operation and blocking unnecessary leakage current.

1 is a configuration diagram of a semiconductor device.
2 is a configuration diagram of a semiconductor device according to an embodiment of the present invention.
3 is a detailed circuit diagram of the sense amplifier driving control unit of FIG. 2.
4 and 5 are other embodiments of the sense amplifier driving control unit of FIG. 2.
6 is a view for explaining each voltage level in the sense amplifier driving control unit of FIG. 2;

Hereinafter, in order to describe in detail so that those of ordinary skill in the art can easily implement the technical idea of the present invention, a most preferred embodiment of the present invention will be described with reference to the accompanying drawings.

In describing the present invention, known configurations irrelevant to the gist of the present invention may be omitted. In adding reference numerals to elements of each drawing, it should be noted that only the same elements have the same reference numerals as much as possible, even if they are indicated on different drawings.

As shown in FIG. 1, the semiconductor memory device includes a sense amplifier driver 10 and a sense amplifier 20.

Here, the sense amplifier driving unit 10 provides first and second senses to the first and second sense amplifier driving nodes RTO and SB, respectively, in response to the first to third sense amplifier driving signals SAP, SAN, and SAPCG. An amplifier driving voltage (VDD, VSS) or a precharge voltage (VBLP) is applied.

For example, when the third sense amplifier driving signal SAPCG is disabled and the first sense amplifier driving signal SAP is enabled in the active state, the sense amplifier driving unit 10 transmits to the first sense amplifier driving node RTO. The first sense amplifier driving voltage VDD is applied.

In addition, when the third sense amplifier driving signal SAPCG is disabled and the second sense amplifier driving signal SAN is enabled in the active state, the sense amplifier driving unit 10 sends a second sense amplifier driving node SB to the second sense amplifier driving node SB. Apply the sense amplifier driving voltage (VSS).

That is, in the active state, the first sense amplifier driving node RTO and the second sense amplifier driving node SB are separated from each other, and the first sense amplifier driving node RTO and the second sense amplifier driving node SB are The first sense amplifier driving voltage VDD and the second sense amplifier driving voltage VSS are applied.

On the other hand, the sense amplifier driver 10 connects the first and second sense amplifier driving nodes RTO and SB when the third sense amplifier driving signal SAPCG is enabled, and the bit line precharge voltage VBLP to the connected node. ) Is applied.

The sense amplifier driver 10 includes first to fifth transistors N1 to N5. The first transistor N1 receives a first sense amplifier driving signal SAP through a gate terminal, an external voltage VDD is applied through a drain terminal, and a source terminal is connected to the first sense amplifier driving node RTO. .

When the first transistor N1 is turned on by the first sense amplifier driving signal SAP, the external voltage VDD is output to the first sense amplifier driving node RTO at the level of the first sense amplifier driving voltage VDD. do.

In addition, the second transistor N2 receives the third sense amplifier driving signal SAPCG through the gate terminal, the drain terminal is connected to the first sense amplifier driving node RTO, and the source terminal is the second sense amplifier driving node ( SB).

The third transistor N3 receives the third sense amplifier driving signal SAPCG through the gate terminal, the bit line precharge voltage VBLP is applied through the drain terminal, and the source terminal is the first sense amplifier driving node RTO. Is connected to

The fourth transistor N4 receives the third sense amplifier driving signal SAPCG through the gate terminal, the bit line precharge voltage VBLP is applied through the drain terminal, and the source terminal is the second sense amplifier driving node SB. Is connected to

At this time, the drain terminals of the third transistor N3 and the fourth transistor N4 are connected in common, and the bit line precharge voltage VBLP is applied through a node connected in common. The fifth transistor N5 receives the second sense amplifier driving signal SAN through the gate terminal, the drain terminal is connected to the second sense amplifier driving node SB, and the ground voltage VSS is applied through the source terminal. Receive.

At this time, when the second sense amplifier driving signal SAN is enabled, the fifth transistor N5 outputs the ground voltage VSS to the second sense amplifier driving node SB at the level of the second sense amplifier driving voltage VSS. do.

In addition, when the first and second sense amplifier driving voltages VDD and VSS are applied to the first and second sense amplifier driving nodes RTO and SB, the sense amplifier 20 It detects and amplifies the voltage level difference of BLb).

When the external voltage VDD is first applied to the semiconductor memory device configured as described above, the voltage levels of the first to third sense amplifier driving signals SAP, SAN, and SAPCG may not be initialized.

When all of the first to third sense amplifier driving signals SAP, SAN, and SAPCG are not initialized, all of the first transistor N1, the second transistor N2, and the fifth transistor N5 may be turned on. In addition, a current path is formed through the turned-on first and second transistors N1 and N2 and the fifth transistor N5, so that unexpected current may be consumed.

2 is a block diagram of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2, a semiconductor device according to an exemplary embodiment of the present invention includes a sense amplifier driving control unit 100, a sense amplifier driving unit 200, and a sense amplifier 300.

The sense amplifier driving control unit 100 generates first to third sense amplifier driving signals SAP, SAN, and SAPCG in response to the sense amplifier enable signal SAE. In addition, the sense amplifier driving control unit 100 cuts off a leakage current that may occur in the sense amplifier driving unit 200 in response to a blocking signal LEAKOFF during a power-on operation.

For example, when the power-up signal is enabled, the sense amplifier driving control unit 100 disables the first and second sense amplifier driving signals SAP and SAN, and enables the third sense amplifier driving signal SAPCG. Let it. Then, after the power-up signal (not shown) is disabled, the first to third sense amplifier driving signals SAP, SAN, and SAPCG are generated in response to the sense amplifier enable signal SAE.

When the sense amplifier enable signal SAE is enabled after the power-up signal is disabled, the sense amplifier driving control unit 100 enables the first and second sense amplifier driving signals SAP, SAN, and enables the third sense amplifier. The amplifier drive signal SAPCG is disabled.

Meanwhile, when the sense amplifier enable signal SAE is disabled, the sense amplifier driving control unit 100 disables the first and second sense amplifier driving signals SAP, SAN, and the third sense amplifier driving signal SAPCG. Enable. In this case, the sense amplifier driving control unit 100 receives the external voltage VDD as the first driving voltage and the pumping voltage VPP as the second driving voltage.

The sense amplifier driving unit 200 selectively connects the first and second sense amplifier driving nodes RTO and SB in response to the first to third sense amplifier driving signals SAP, SAN, and SAPCG. Accordingly, the sense amplifier driver 200 forms the first and second sense amplifier driving nodes RTO and SB at the same voltage level, that is, the bit line precharge voltage VBLP level. Alternatively, the sense amplifier driving unit 200 applies the first sense amplifier driving voltage VDD to the first sense amplifier driving node RTO while the first and second sense amplifier driving nodes RTO and SB are separated. , The second sense amplifier driving voltage VSS is applied to the second sense amplifier driving node SB.

For example, when the first and second sense amplifier driving signals SAP and SAN are disabled, the sense amplifier driving unit 200 applies the first sense amplifier driving voltage VDD to the first sense amplifier driving node RTO. And preventing the second sense amplifier driving voltage VSS from being applied to the second sense amplifier driving node SB.

Meanwhile, the sense amplifier driving unit 200 separates the first and second sense amplifier driving nodes RTO and SB when the third sense amplifier driving signal SAPCG is disabled. Then, the sense amplifier driver 200 applies the first sense amplifier driving voltage VDD to the first sense amplifier driving node RTO when the first and second sense amplifier driving signals SAP and SAN are enabled, The second sense amplifier driving voltage VSS is applied to the second sense amplifier driving node SB.

In addition, when the sense amplifier 300 receives the first and second sense amplifier driving voltages VDD and VSS from the first and second sense amplifier driving nodes RTO and SB, the bit line BL and the bit line bar It detects and amplifies the voltage difference of (BLb). That is, the sense amplifier 300 performs a data sensing operation when the first and second sense amplifier driving voltages VDD and VSS are applied from the first and second sense amplifier driving nodes RTO and SB.

In addition, the sense amplifier driving control unit 100 blocks a leakage current that may occur in a node applying the first and second sense amplifier driving signals SAP and SAN while the third sense amplifier driving signal SAPCG is enabled. That is, when the blocking signal LEAKOFF is enabled during the power-on operation, the first sense amplifier driving node RTO and the second sense amplifier driving node SB are pulled down to the ground voltage level to block leakage current.

3 is a detailed circuit diagram of the sense amplifier driving control unit 100 of FIG. 2.

The sense amplifier driving control unit 100 includes inverters IV1 and IV5, level shifters 110 and 120, driving units 130 and 140, and a leakage current blocking unit 150.

The inverters IV1 and IV5 receive the sense amplifier enable signal SAE, drive invertedly, and output them to the level shifters 110 and 120. Here, the inverters IV1 and IV5 operate by receiving the external voltage VDD and the ground voltage VSS as driving voltages. Therefore, the output signals of the inverters IV1 and IV5 are signals that swing to the external voltage VDD and the ground voltage VSS.

Further, the level shifter 110 receives the output of the inverter IV1 and performs level shifting. That is, the level shifter 110 shifts a signal that swings to the external voltage (VDD) level and the ground voltage (VSS) level into a signal that swings to the pumping voltage (VPP) and ground voltage (VSS) levels.

In addition, the level shifter 120 receives the output of the inverter IV5 and performs level shifting. That is, the level shifter 120 shifts a signal that swings to the external voltage (VDD) level and the ground voltage (VSS) level into a signal that swings to the pumping voltage (VPP) and ground voltage (VSS) levels.

Here, it is assumed that the level shifters 110 and 120 are level shifters that output an input signal by non-inverting it. In addition, the pumping voltage VPP may be a voltage generated inside the semiconductor memory device or a voltage higher than the external voltage VDD applied from the outside of the semiconductor memory device.

In addition, the driving unit 130 inverts the output of the level shifter 110 to output the first sense amplifier driving signal SAP. The driving unit 130 includes a plurality of inverters IV2 to IV4 connected in series in an odd number. Here, the plurality of inverters IV2 to IV4 are operated by receiving the pumping voltage VPP and the ground voltage VSS as driving voltages.

Further, the driving unit 140 inverts the output of the level shifter 110 to output a second sense amplifier driving signal SAN. The driving unit 140 includes a plurality of inverters IV6 to IV8 connected in series in an odd number. Here, the plurality of inverters IV6 to IV8 operate by being applied with a pumping voltage VPP and a ground voltage VSS as driving voltages.

That is, the driving units 130 and 140 apply the pumping voltage VPP or the ground voltage VSS to the first and second sense amplifier driving signals SAP and SAN. These first and second sense amplifier driving signals SAP and SAN may be simultaneously enabled or disabled.

For example, when the outputs of the level shifters 110 and 120 are at a low level, the driving units 130 and 140 output the first and second sense amplifier driving signals SAP and SAN at the pumping voltage VPP level. On the other hand, when the outputs of the level shifters 110 and 120 are at a high level, the driving units 130 and 140 output the first and second sense amplifier driving signals SAP and SAN at the ground voltage VSS level.

In addition, when the blocking signal LEAKOFF is enabled to a high level during the power-on operation, the leakage current blocking unit 150 applies the first sense amplifier driving node RTO and the second sense amplifier driving node SB to the ground voltage VSS. ) Pull down to the level to cut off leakage current. The leakage current blocking unit 150 includes NMOS transistors N6 and N7 which are pull-down driving elements.

Here, the NMOS transistor N6 is connected between the output terminal of the first sense amplifier driving signal SAP and the ground voltage terminal, and the blocking signal LEAKOFF is applied through the gate terminal. Accordingly, when the blocking signal LEAKOFF transitions to a high level during the power-on operation, the NMOS transistor N6 is turned on and the first sense amplifier driving signal SAP is pulled down to the ground voltage VSS level.

In addition, the NMOS transistor N7 is connected between the output terminal of the second sense amplifier driving signal SAN and the ground voltage terminal, and the blocking signal LEAKOFF is applied through the gate terminal. Accordingly, when the blocking signal LEAKOFF transitions to a high level during the power-on operation, the NMOS transistor N7 is turned on and the second sense amplifier driving signal SAN is pull-down driven to the ground voltage VSS level.

4 and 5 are other embodiments of the sense amplifier driving control unit 100 of FIG. 2.

First, the embodiment of FIG. 4 further includes a leakage current blocking unit 160 in the embodiment of FIG. 3, and detailed configurations of the driving units 130_1 and 140_1 are different. The embodiment of FIG. 4 can be applied when the level shifters 110 and 120 are non-inverting level shifters.

When the blocking signal LEAKOFF is enabled during the power-on operation, the leakage current blocking unit 160 unconditionally outputs a low level signal when transitioning to a high level. That is, when the blocking signal LEAKOFF transitions to the high level, the low level signal is unconditionally output to the driving units 130_1 and 140_1 regardless of the outputs of the level shifters 110 and 120. Then, the input of the driving units 130_1 and 140_1 is at a low level, so that leakage current that may occur at the input terminals of the driving units 130_1 and 140_1 can be blocked. On the other hand, when the blocking signal LEAKOFF transitions to the low level, a signal corresponding to the output of the level shifters 110 and 120 is output to the driving units 130_1 and 140_1.

The leakage current blocking unit 160 includes NOR gates NOR1 and NOR2. Here, the NOA gate NOR1 calculates NOA on the output of the level shifter 110 and the blocking signal LEAKOFF. Further, the NOA gate NOR2 calculates the output of the level shifter 120 and the blocking signal LEAKOFF. The NOA gates NOR1 and NOR2 operate by receiving a pumping voltage VPP and a ground voltage VSS as driving voltages.

Further, the driving units 130_1 and 140_1 non-invertingly drive the output of the leakage current blocking unit 160 to output the first and second sense amplifier driving signals SAP and SAN. The driving unit 130_1 includes inverters IV9 and IV10 connected in series in an even number. In addition, the driving unit 140_1 includes inverters IV11 and IV12 connected in series in an even number. Here, the inverters IV9 to IV12 operate by receiving the pumping voltage VPP and the ground voltage VSS as driving voltages.

Meanwhile, the embodiment of FIG. 5 further includes a leakage current blocking unit 170 in the embodiment of FIG. 3, and detailed configurations of the level shifters 110_1 and 120_1 and the driving units 130_1 and 140_1 are different. The embodiment of FIG. 5 can be applied when the level shifters 110_1 and 120_1 are inverting level shifters.

When the blocking signal LEAKOFF is enabled during the power-on operation, the leakage current blocking unit 170 unconditionally outputs a low level signal when it transitions to a high level. That is, when the blocking signal LEAKOFF transitions to the high level, the high level signal is unconditionally output to the driving units 130_2 and 140_2 regardless of the outputs of the level shifters 110_1 and 120_1. Then, the input of the driving units 130_2 and 140_2 is at a low level, so that leakage current that may occur at the input terminals of the driving units 130_2 and 140_2 can be blocked. On the other hand, when the blocking signal LEAKOFF transitions to the low level, a signal corresponding to the output of the level shifters 110_1 and 120_1 is output to the driving units 130_2 and 140_2.

The leakage current blocking unit 170 includes NAND gates ND1 and ND2 and an inverter IV13. Here, the NAND gate ND1 performs a NAND operation on the output of the level shifter 110_1 and the blocking signal LEAKOFF inverted by the inverter IV13. In addition, the NAND gate ND2 performs a NAND operation on the output of the level shifter 120_1 and the blocking signal LEAKOFF inverted by the inverter IV13. The NAND gates ND1 and ND2 operate by receiving a pumping voltage VPP and a ground voltage VSS as driving voltages.

Further, the driving units 130_2 and 140_2 invert the output of the leakage current blocking unit 170 to output the first and second sense amplifier driving signals SAP and SAN. The driver 130_2 includes an odd number of inverters IV4. In addition, the driving unit 140_2 includes an odd number of inverters IV15. Here, the inverters IV14 and IV15 operate by receiving the pumping voltage VPP and the ground voltage VSS as driving voltages.

6 is a diagram for explaining each voltage level in the sense amplifier driving control unit of FIG. 2.

When the power-on operation of the semiconductor device starts, the potential of the blocking signal LEAKOFF starts to rise according to the level of the power-up signal. In addition, when the potential of the blocking signal LEAKOFF exceeds a predetermined voltage level, the blocking signal LEAKOFF maintains a specific voltage level during the period T1. Here, the specific voltage level of the blocking signal LEAKOFF may be set to the high voltage level VPPEXT. The high voltage level VPPEXT has a voltage level lower than the pumping voltage VPP and higher than the external power supply voltage VDD.

That is, after the power-on operation starts, the blocking signal LEAKOFF transitions to the high level during the period T1. Then, the output terminals of the level shifters 110 and 120 and the first and second sense amplifier driving signals SAP and SAN are pulled down to the ground voltage VSS level to block leakage current.

Thereafter, the level of the external power supply voltage VDD rises during the period T2 and maintains the voltage at a predetermined level. At this time, when the power voltage VDD maintains a specific level at the time point T2 passes, the blocking signal LEAKOFF transitions to the ground voltage VSS level.

When the blocking signal LEAKOFF transitions to the low level, the leakage current blocking unit 150 is turned off to stop the leakage current blocking operation. Further, the level shifters 110 and 120 level-shift the power supply voltage VDD to output a signal having a pumping voltage VPP level.

In the period (A) when the power-on operation starts and the power voltage VDD becomes the voltage level V1, the leakage current blocking unit 150 operates to block the leakage current. That is, in the period (A) where the power voltage VDD level is low, the leakage current is blocked through the leakage current blocking unit 150.

On the other hand, in the section (B) in which the power voltage VDD gradually rises and the power voltage VDD reaches the V2 level, the leakage current blocking unit 160 or the leakage current blocking unit 170 operates to block the leakage current. To be able to. That is, in the period (B) where the power voltage VDD level is high, the leakage current is blocked through the leakage current blocking units 160 and 170.

That is, when the power-on operation starts and enters the T2 section, the power voltage VDD level starts to rise, and the pumping voltage VPP level rises after a certain time. However, the time difference due to the timing at which the power is applied may affect the initial output values of the level shifters 110 and 120.

In the idle state after the power-on operation is finished, the output of the level shifters 110 and 120 is usually a low level, which is a default value. However, during initial power-on, the outputs of the level shifters 110 and 120 may be output at a high level for a predetermined timing due to a malfunction of the level shifters 110 and 120 regardless of the sense amplifier enable signal SAE. Accordingly, in the embodiment of the present invention, it is possible to prevent unnecessary current consumption due to a malfunction in the initial power-on state through the leakage current blocking units 150, 160, and 170.

Those skilled in the art to which the present invention pertains, since the present invention may be implemented in other specific forms without changing the technical spirit or essential features thereof, the embodiments described above are illustrative in all respects and should be understood as non-limiting. Only do it. The scope of the present invention is indicated by the claims to be described later rather than the detailed description, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. .

Claims (20)

Generates a first sense amplifier drive signal and a second sense amplifier drive signal in response to a sense amplifier enable signal, and generates at the application end of the first sense amplifier drive signal and the second sense amplifier drive signal in response to a blocking signal A sense amplifier driving control unit that cuts off the leakage current that is generated;
A sense amplifier driving unit selectively connecting a first sense amplifier driving node and a second sense amplifier driving node in response to the first sense amplifier driving signal and the second sense amplifier driving signal; And
A sense amplifier configured to sense and amplify a voltage difference between a pair of bit lines by receiving a first driving voltage and a second driving voltage through the first sense amplifier driving node and the second sense amplifier driving node,
The blocking signal is
A semiconductor device, comprising: a voltage level rising during a power-on operation, maintaining a specific voltage level for a certain period of time, and transitioning to a ground voltage level when the power supply voltage level is maintained at a specific voltage level. ◈ Claim 2 was abandoned upon payment of the set registration fee. The method of claim 1, wherein the sense amplifier driving control unit
A first level shifter level-shifting a first driving voltage according to the sense amplifier enable signal and outputting a second driving voltage level;
A second level shifter level-shifting a first driving voltage according to the sense amplifier enable signal and outputting a second driving voltage level;
A first driver for driving an output of the first level shifter to output the first sense amplifier driving signal;
A second driver configured to drive an output of the second level shifter to output the second sense amplifier driving signal; And
And a leakage current blocking unit configured to block a leakage current generated at an application terminal of the first sense amplifier driving signal and the second sense amplifier driving signal in response to the blocking signal. ◈ Claim 3 was abandoned upon payment of the set registration fee.◈ The semiconductor device according to claim 2, wherein the first driving voltage is a power supply voltage level. ◈ Claim 4 was abandoned upon payment of the set registration fee. The semiconductor device according to claim 2, wherein the second driving voltage is a pumping voltage level. ◈Claim 5 was abandoned upon payment of the set registration fee.◈ The method of claim 2, wherein the first driving part
A semiconductor device comprising a plurality of inverters connected in series. ◈Claim 6 was abandoned upon payment of the set registration fee.◈ The method of claim 5, wherein the plurality of inverters
A semiconductor device having an odd number. ◈ Claim 7 was abandoned upon payment of the set registration fee. The method of claim 6, wherein the first level shifter is
A semiconductor device comprising a non-inverting level shifter. ◈ Claim 8 was abandoned upon payment of the set registration fee. The method of claim 2, wherein the second driving part
A semiconductor device comprising a plurality of inverters connected in series. ◈ Claim 9 was abandoned upon payment of the set registration fee.◈ The method of claim 8, wherein the plurality of inverters
A semiconductor device having an odd number. ◈ Claim 10 was abandoned upon payment of the set registration fee. The method of claim 9, wherein the second level shifter
A semiconductor device comprising a non-inverting level shifter. ◈ Claim 11 was abandoned upon payment of the set registration fee. The method of claim 2, wherein the leakage current blocking unit
And when the blocking signal is enabled, pull-down driving of an application terminal of the first sense amplifier driving signal and the second sense amplifier driving signal is driven. ◈ Claim 12 was abandoned upon payment of the set registration fee. The method of claim 11, wherein the leakage current blocking unit
A first pull-down driving device connected between an application terminal of the first sense amplifier driving signal and a ground voltage terminal to which the blocking signal is applied through a gate terminal; And
And a second pull-down driving device connected between the application terminal of the second sense amplifier driving signal and the ground voltage terminal to which the blocking signal is applied through a gate terminal. ◈ Claim 13 was abandoned upon payment of the set registration fee. The method of claim 2, wherein the leakage current blocking unit
And maintaining the input terminals of the first driving unit and the second driving unit at a low level when the blocking signal is enabled. ◈ Claim 14 was abandoned upon payment of the set registration fee. The method of claim 13, wherein the leakage current blocking unit
A first NOA gate performing NOZ operation on the output of the first level shifter and the blocking signal; And
And a second NOA gate performing NOZ operation on the output of the second level shifter and the blocking signal. ◈ Claim 15 was abandoned upon payment of the set registration fee.◈ The method of claim 14, wherein the first driving part and the second driving part
A semiconductor device comprising a plurality of inverters connected in series in an even number. ◈ Claim 16 was abandoned upon payment of the set registration fee. The method of claim 15, wherein the first level shifter and the second level shifter are
A semiconductor device comprising a non-inverting level shifter. ◈ Claim 17 was abandoned upon payment of the set registration fee. The method of claim 2, wherein the leakage current blocking unit
And maintaining the input terminals of the first driving unit and the second driving unit at a high level when the blocking signal is enabled. ◈ Claim 18 was abandoned upon payment of the set registration fee.◈ The method of claim 17, wherein the leakage current blocking unit
An inverter inverting the blocking signal;
A first NAND gate for NAND-operating the output of the inverter and the output of the first level shifter; And
And a second NAND gate for NAND-operating the output of the inverter and the output of the second level shifter. delete ◈ Claim 20 was abandoned upon payment of the set registration fee. The semiconductor device of claim 1, wherein the blocking signal has a level lower than a pumping voltage and higher than a power supply voltage.

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