KR100938084B1 - Circuit of page buffer for multi level cell flash memory and method of operating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-level cell memory device. In particular, the present invention relates to a multi-level cell memory device. To read the data.

In addition, the data read from the sensing node can be directly output to the data line without latching using a circuit used in a program operation, thereby providing a faster read speed.

Page buffer, read

Description

Circuit of page buffer for multi level cell flash memory and method of operating the same}

1 is a circuit diagram of a page buffer of a conventional MLC flash memory.

2 is a timing diagram of a conventional read operation of a page buffer.

3 is a circuit diagram of a page buffer of an MLC flash memory according to an embodiment of the present invention.

4A and 4B are diagrams illustrating the connection of the page buffer operation read program signal of FIG. 3.

5 is an operation timing diagram of a page buffer according to an embodiment of the present invention.

* Brief description of the main parts of the drawings *

310: bit line selection section 320: MSB latch section

321: first latch 330: LSB latch portion

331: second latch 340: Y decoder

The present invention relates to data read of a multi-level cell flash memory, and in particular, a program signal (PGM signal) is used for separate reading during LSB (Least Significant Bit) and MSB (Most Significant Bit) programming. A page buffer circuit and a method of operating a multi-level cell flash memory for performing a faster read operation.

Flash memory is generally divided into NAND flash memory and NOR flash memory. NOR flash memory has a good random access time characteristic because memory cells are independently connected to bit lines and word lines, whereas NAND flash memory has a plurality of memory cells connected in series so that one contact per cell string is provided. Since only requires, it has excellent characteristics in terms of integration degree. Therefore, a NAND structure is mainly used for highly integrated flash memory.

Well known NAND flash memory devices include memory cell arrays, row decoders, and page buffers. The memory cell array includes a plurality of word lines and columns defined along rows and a plurality of bit lines extending along columns and a plurality of cell strings corresponding to the bit lines, respectively.

One side of the memory cell array includes a row decoder connected to string selection lines, word lines, and a common source line, and a page buffer connected to a plurality of bit lines is located on the other side.

Recently, in order to further improve the density of such flash memories, researches on multiple bit cells capable of storing a plurality of data in one memory cell have been actively conducted. This type of memory cell is referred to as a multi level cell (hereinafter referred to as MLC). In contrast, a single bit memory cell is referred to as a single level cell (hereinafter referred to as SLC).

MLC typically has two or more threshold voltage distributions and corresponding two or more data storage states. The MLC, which can program two bits of data, has four data storage states: [11], [10], [00], and [01]. Their distribution corresponds to the threshold voltage distributions of the MLC, respectively.

For example, assuming that the threshold voltage distributions of the memory cell are -2.7 V or less, 0.3 V to 0.7 V, 1.3 V to 1.7 V, and 2.3 V to 2.7 V, respectively, [11] is -2.7 V or less, [ 10 corresponds to 0.3V to 0.7V, [00] corresponds to 1.3V to 1.7V, and [01] corresponds to 2.3V to 2.7V. That is, when the threshold voltage of the MLC corresponds to one of the four threshold voltage distributions, two bits of data information corresponding to [11], [10], [00], and [01] are displayed. Stored in MLC.

A page buffer for programming and reading a flash memory device having an MLC is configured as follows.

1 is a circuit diagram of a page buffer of a conventional MLC flash memory.

Referring to FIG. 1, a page buffer 50 of an MLC memory device is connected to a memory cell array (not shown) including an MLC capable of storing two or more bits of data, and selects a bit line according to an input address. And a Y decoder 40 for connecting the first and second latch units 20 and 30 and the first and second latch units 20 and 30 to an external data line.

In particular, the first latch unit 20 is a latch circuit for programming and reading the MSB (Most Significant Bit), which is an upper bit of 2 bits of data, and the second latch unit 30 is a lower bit of 2 bits of data. A latch circuit for programming and reading LSB (Least Significant Bit).

The bit line selector 10 includes first to fourth NMOS transistors N1 to N4.

The first latch unit 20 includes fifth to fourteenth NMOS transistors N5 to N14, first to third inverters I1 to I3, and a second PMOS transistor P2. The second and third inverters I2 and I3 constitute a first latch 21.

The second latch unit 30 includes the fifteenth to twenty-first NMOS transistors N15 to N21, the fourth to sixth inverters I4 to I6, and the third PMOS transistor P3. The fifth and sixth inverters I5 and I6 constitute a second latch 31.

The first and second patch units 20 and 30 further include a first PMOS transistor P1 for providing a precharge voltage for a program or read operation.

In addition, the Y decoder 40 supplies data to the twenty-second to twenty-fourth NMOS transistors N22 to N24 for connecting the page buffers 20 and 30 to an external data line according to an address, and to the page buffers 20 and 30. A fourth PMOS transistor P4 and a twenty-fifth NMOS transistor N25 for input are included, and a seventh inverter I7 is included.

The operation of the page buffer 50 is as follows.

First, in a method of programming data in a memory cell, the LSB data latched in the second latch 31 of the second latch unit 30 is transferred to the memory cell connected to the bit line selected by the bit line selector 10. To program. Data verification is performed, and the LSB data is read and stored in the second latch 30 again.

After the LSB data has been programmed, the MSB data is latched in the first latch 21 of the first latch unit 20.

The data latched in the second latch 21 is compared with LSB data read in the second latch 31 to determine whether to program the MSB data.

In this case, the fifth, seventh, fifteenth, and sixteenth NMOS transistors N5, N7, N14, and N16 may compare the MSB data with the LSB data to determine a program.

On the other hand, when data is read into the memory cell, it operates as shown in the following timing chart.

2 is a timing diagram of a conventional read operation of a page buffer.

Referring to FIG. 2, the precharge control signal PRECHb is set to a low level in order to reset the second latch 31 of the second latch unit 30 before reading the lower LSB data among the two bits of data. The sensing node SO is set to a high level to turn on the twentieth NMOS transistor MN20, and the first LSB read control signal LSBREAD1 is applied to a high level to reset the node ND6 to a low level. Resetting the LSB takes 3us.

After the reset is completed, the precharge control signal PRECHb is input at a low level so that the precharge voltage is applied (S21), and the sensing node SO is precharged. The bit line control signal BSLE is applied at a high level in order to connect to the bit line connected to the memory cell for reading (S22), and the third NMOS transistor N3 is turned on to precharge the bit line. Let's do it. The precharge of the bit line is made for 6us of time.

After precharging the bit line, the bit line control signal BSLE is changed to a low level to turn off the third NMOS transistor N3 to float the bit line (S23). Therefore, when the connected cell is programmed, the precharge voltage applied to the bit line does not escape the precharge voltage of the bit line, and in the case of an erase cell, the precharge voltage of the bit line escapes to the common source line. The bit line is changed to 0V (S24).

A period in which the precharge voltage of the floated bit line changes in voltage depending on whether the memory cell is programmed or erased is called a data readout interval.

In the data readout period, the precharge control signal PRECHb is changed back to a high level to float the sensing node SO (S25). At this time, the sensing node SO maintains a high level.

The bit line control signal BSLE is applied at a high level to connect the bit line and the sensing node SO (S26). Thereafter, the first LSB read control signal LSBREAD1 is applied to turn on the twentieth NMOS transistor N20 (S28) to load the second latch 31 data of the sensing node SO (S29).

At this time, the sensing node SO is in a state where the precharge voltage is continuously applied, and the voltage level is changed according to the voltage state of the bit line at the time when the sensing node SO is connected to the bit line in step S26 (S27).

That is, in the case of a programmed cell, the sensing node SO is continuously maintained at a high level, and in the case of an erased cell, the sensing node SO is discharged. At this time, the sensing node SO is discharged or a period in which the voltage level is maintained is also included in the read period. The entire readout period is 6us for floating the bit line to change the voltage level, and 2us until the first LSB read control signal LSBREAD1 is applied to load data in the second latch 31. Include.

Thereafter, after discharging the bit line to the initial state for a time of 7us, the steps S21 to S29 are repeated to read the LSB data one more time by the second LSB read control signal LSBREAD2 and to read the MSB data. Do this. The reason why the LSB data is read twice is that the LSB data is read at two threshold voltage values and the MSB is loaded at one threshold voltage according to the characteristics of the MLC storing two bits of data.

The read operation as described above takes 45us for the LSB and 24us for the MSB. In this case, if the memory cell is a programmed cell, there is no problem since the sensing node SO is maintained at a high level. However, if the memory cell is an erased cell, a problem may occur.

More specifically, as shown in FIG. 2, in the case of the erase cell, the sensing node SO needs to be discharged while connected to the bit line during 2us during the step S26, so that the sensing node SO is discharged to 0V. There is a problem of not having enough time. Therefore, an error may occur in reading data.

To solve this problem, the sensing node SO can be read with a long time to be discharged, but this causes a problem that is inconsistent with the specification.

Accordingly, the present invention provides a multi-level cell flash that reads and outputs the upper and lower bits of data quickly and without error when reading data from a page buffer of a memory device including a multi-level cell. To provide a page buffer circuit and an operation method of the memory.

The page buffer circuit of the multi-level cell flash memory according to an aspect of the present invention for achieving the above technical problem,

An upper bit register configured to sense the voltage of the sensing node in response to the first read control signal to store upper sensing data and output inverted upper sensing data, or to store input data and to output inverted input data; In response to a second read control signal, the voltage of the sensing node is sensed to store first lower sensed data and output inverted first lower sensed data, or in response to a third read control signal, A lower bit register configured to sense a voltage to store second lower sensing data and output inverted second lower sensing data; An upper bit read and program control circuit connected between the sensing node and the upper bit register to transmit a voltage of the sensing node to a data input / output line by an upper bit read and a program control signal; And a lower bit read and a program control circuit connected between the sensing node and the lower bit register to transmit a voltage of the sensing node to a data input / output line by a lower bit read and a program control signal, wherein the sensing node comprises: It is characterized in that it is precharged for bit line procharge, and connected to the bit line to precharge the bit line, and then floated before disconnecting the bit line.

The upper bit read and program control signals may be output signals of a NOR gate using the upper bit program control signal and the first read signal as input signals.

The lower bit read and program control signals may be output signals of a NOR gate using the lower bit program control signals and the second and third read signals as input signals.

A bit line selection circuit for selecting one of a pair of bit lines in response to bit line selection signals and discharge signals, and connecting the selected bit line to the sensing node; And a precharge circuit configured to precharge or float the sensing node to an internal voltage in response to the precharge control signal.

The upper bit register may include: a sensing circuit configured to sense a voltage of the sensing node in response to the first read control signal and to generate the upper sensing data; A latch circuit for latching the upper sensing data and outputting inverted upper sensing data, or latching the input data and outputting the inverted input data; And a latch reset circuit for initializing the latch circuit in response to a reset control signal.

The lower bit register may include: a sensing circuit configured to sense a voltage of the sensing node in response to the second or third read control signal and to generate the first or second lower sensing data; And a latch circuit for latching the first lower sensing data, outputting the inverted first lower sensing data, or latching the second lower sensing data, and outputting the inverted second lower sensing data. .

In the multi-level cell flash memory device according to the present invention,

A memory cell array including a plurality of bit line pairs and a plurality of multi-level cells each connected to a plurality of word lines; One to each of the plurality of pairs of bit lines, each of which outputs data to be programmed to one of a multi-level cell or the like connected to a pair of corresponding bit lines in a program operation; Page buffer circuits for outputting data read from one of the multi-level cells connected to a pair of bit lines to a data line by a read and program control signal before a latch operation; And correspondingly connected to each of the plurality of page buffer circuits, and are further connected to a data input / output line to transmit data to be programmed to the page buffer circuit, or output read data transmitted from the page buffer circuit to the data input / output line. Y decoder circuits.

Each of the plurality of page buffers senses a voltage of a sensing node in response to a first read control signal to store upper sensing data and output inverted upper sensing data, or store input data, and invert input data. An upper bit register to output a; In response to a second read control signal, the voltage of the sensing node is sensed to store first lower sensed data and output inverted first lower sensed data, or in response to a third read control signal, A lower bit register configured to sense a voltage to store second lower sensing data and output inverted second lower sensing data; An upper bit read and program control circuit connected between the sensing node and the upper bit register to transmit a voltage of the sensing node to a data input / output line by an upper bit read and a program control signal; And a lower bit read and a program control circuit connected between the sensing node and the lower bit register to transmit a voltage of the sensing node to a data input / output line by a lower bit read and a program control signal, wherein the sensing node comprises: It is characterized in that it is precharged for bit line procharge, and connected to the bit line to precharge the bit line, and then floated before disconnecting the bit line.

Read operation method of a multi-level cell flash memory according to an aspect of the present invention,

A read operation method of a flash memory device, the method comprising: precharging a sensing node of a page buffer in response to a read command; Precharging a bit line by connecting the precharged sensing node and a bit line selected according to an input address; Plotting a sensing node of the page buffer; Cutting off the connection between the bit line and the sensing node to induce a change in the voltage level of the bit line according to whether the memory cell is programmed; Connecting the bit line and a sensing node; And outputting the upper or lower read data according to the voltage level of the sensing node connected to the bit line to the data output line according to the upper or lower bit read and program control signals.

The read and program control signals may be determined by a result of a NOA operation of a read control signal of the page buffer and an upper bit or lower bit program control signal.

Outputting the upper or lower read data to a data output line according to upper or lower bit read and program control signals, and then latching the upper or lower read data to an upper bit latch or a lower bit latch circuit according to a read control signal of the page buffer. Include.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 is a circuit diagram of a page buffer of an MLC flash memory according to an exemplary embodiment of the present invention, and FIGS. 4A and 4B are diagrams illustrating a connection diagram of a page buffer operation read program signal of FIG. 3.

Referring to FIG. 3, a page buffer 300 of a multi level cell (MLC) flash memory according to an embodiment of the present invention may include a bit line selector 310, a most significant bit latch (320), and an LSB. (Least Significant Bit) The latch unit 330 and the Y decoder 340. The first PMOS transistor MP1 is included to precharge the sensing node SO.

The bit line selector 310 selects a bit line to which a memory cell for program or read is connected and includes first to fourth NMOS transistors MN1 to MN4.

The MSB latch unit 320 operates to program and read the higher bits, and includes the fifth to fourteenth NMOS transistors MN5 to MN 14, the first to third inverters IN1 to IN3, and the second PMOS transistor MP2. ). In this case, the second and third inverters IN2 and IN3 are configured by the first latch 321.

The LSB latch unit 330 includes the fifteenth to twenty-first NMOS transistors MN15 to MN21, the fourth to sixth inverters IN4 to IN6, and the third PMOS transistor MP3. In this case, the fifth and sixth inverters IN5 and IN6 are constituted by a second latch 332.

The Y decoder unit 340 provides an input / output path for data input and output to the MSB and LSB latch units 320 and 330, and includes twenty-second to twenty-fourth NMOS transistors MN22 to MN24, and a seventh inverter IN7. . And a fourth PMOS transistor MP4 and a 25 th NMOS transistor MN25 for inputting data.

The first and second NMOS transistors MN1 and MN2 of the bit line selector 310 apply a power supply voltage or 0V to the unselected bit lines BLE or BLO, and control signals DISCHE or DISCHO to discharge them. It works by).

The third and fourth NMOS transistors MN3 and MN4 operate by the bit line select signal BSLE or BSLO, and connect the bit lines BLE or BLO to the sensing node SO according to an input address.

The MSB latch unit 320 is connected between the sensing node SO and the Y decoder 340 for data input and output, and the fifth NMOS transistor NM5 is connected between the sensing node SO and the first node ND1. In connection with the data transmission signal DATTRANS, the data latched in the first latch 321 is transmitted to the bit line through the sensing node SO.

The first inverter IN1 is connected between the first node ND1 and the second node ND2 to invert the MSB data of the second node ND2 and output the inverted MSB data to the first node ND1. The eighth and ninth NMOS transistors MN8 and MN9 are connected in series between the second node ND2 and the ground voltage, and the eighth NMOS transistor MN8 reads an MSB by an MSB read control signal MSBREAD signal. The ninth NMOS transistor MN9 operates with the sensing node SO as an input signal.

The first latch 321 including the second and third inverters IN2 and IN3 is connected between the second node ND2 and the third node ND3. The tenth NMOS transistor MN10 is connected between the third node ND3 and the ground voltage and operates according to the control signal MSBSET for resetting the MSB. The second PMOS transistor MN2 receives the power supply voltage using the third node ND3 as an input signal and outputs an inverted signal MSBVER_N of the verification signal.

A twelfth NMOS transistor MN12 is connected between the second node ND2 and the fourth node ND4 to operate by a data input control signal DATLOAD, and the thirteenth NMOS transistor MN13 is a third node. It is connected between the ND3 and the fourth node ND4 and operated by the inversion signal DATALOAD_N of the data control signal.

The eleventh NMOS transistor MN11 is connected between the sensing node SO and the fourth node ND4 and operated by a test control signal CELLIV for a test operation.

The sixth and seventh NMOS transistors MN6 and MN7 are connected in series between the sensing node SO and the first node ND1, and the sixth NMOS transistor MN6 is connected to the MSB read and program control signal MSBREADPROG. Is operated. The MSB read and program control signal MSBREADPROG is applied when programming the MSB data or reading data stored in the memory cell through the bit line.

As shown in FIG. 4B, the MSB read and program control signal MSBREADPROG applied to the sixth NMOS transistor MN6 uses a MSA program control signal MSBPROG and an MSB read control signal MSBREAD as input signals. NOR2) output signal. The NOR gate NOR2 outputs a high level only when the input signals are all low level. Therefore, in the read operation, the MSB program control signal MSBPROG is at a low level and the MSB read and program control signal MSBREADPROG is kept at a high level until the MSB read control signal MSBREAD is applied at a high level, thereby maintaining the sixth NMOS transistor. Turn on (MN6).

The fourteenth NMOS transistor MN14 is connected between the first node ND1 and the fourth node ND4 and is operated by a control signal MSBPASS for outputting read data.

In addition, the LSB latch unit 330 is also connected between the sensing node SO and the Y decoder 340 for data input and output. The seventeenth NMOS transistor MN17 is connected between the sensing node SO and the fifth node ND5 and is operated by the program signal SLCPROG for the single level cell SLC.

The fourth inverter IN4 is connected between the fifth node ND5 and the sixth node ND6 to invert and output the data of the sixth node ND6 corresponding to the LSB data to the fifth node ND5. .

The second latch 331 including the fifth and sixth inverters IN5 and 6 is connected between the sixth node ND6 and the seventh node ND7. The nineteenth NMOS transistor MN19 is connected between the sixth node ND6 and the eighth node ND8 and is operated by the first LSB read control signal LSBREAD1. The eighteenth NMOS transistor MN18 is connected between the seventh node ND7 and the eighth node ND8 and is operated by the second LSB read control signal LSBREAD2.

The twentieth NMOS transistor MN20 is connected between the eighth node ND8 and the ground voltage and is driven according to the state of the sensing node SO.

The third PMOS transistor MP3 receives the power supply voltage according to the signal of the seventh node ND7 and outputs the inverted signal LSBVER_N of the verification signal.

The fifteenth and sixteenth NMOS transistors MN15 and MN16 are connected in series between the sensing node SO and the fifth node ND5, and the fifteenth NMOS transistor MN15 is connected to the LSB read and program control signal LSBREADPROG. It works by The LSB read and program control signal LSBREADPROG is applied when programming LSB data or reading data stored in a memory cell through a bit line.

As shown in FIG. 4A, the LSB read and program control signal LSBREADPROG is a NOA using the LSB program control signal MSBPROG, the first LSB read control signal LSBREAD1, and the second LSB read control signal LSBREAD2 as input signals. This is an output signal of the gate NOR1. The NOR gate NOR1 outputs a high level only when the input signals are all low level. Therefore, in the read operation, the LSB program control signal LSBPROG is at a low level and the LSB read and program control signal (LSBREAD1) is continuously applied before the first LSB read control signal LSBREAD1 or the second LSB read control signal LSBREAD2 is applied at a high level. LSBREADPROG is maintained at a high level to turn on the fifteenth NMOS transistor MN15.

The 22nd to 24th NMOS transistors MN22 to MN24 and the 7th inverter IN7 of the Y decoder 340 are connected in series between the fourth node ND4 and the data input / output line, and the MSB latch unit 320 is disposed. And a path for transmitting data input / output from the LSB latch unit 330 to the data line by an address signal.

The fourth PMOS transistor MP4 is connected between a power supply voltage and an input node of the seventh inverter IN7, and the 25th NMOS transistor MN25 is connected between an input node of the seventh inverter IN7 and a ground power source. It operates in accordance with a control signal (not shown) for data input.

The read operation of the page buffer 300 according to an exemplary embodiment of the present invention will be described with reference to the following timing diagram.

5 is an operation timing diagram of a page buffer according to an embodiment of the present invention.

Referring to FIG. 5, an LSB reset (LSBRST) is performed to initialize the second latch 331 of the LSB latch unit 330 to initially read data.

The LSB reset applies the precharge control signal PRECHb to a low level to turn the sensing node SO to a high level to turn on the twentieth NMOS transistor MN20. The first LSB read control signal LSBREAD1 is applied at a high level to turn on the nineteenth NMOS transistor MN19 to reset the sixth node ND6 to a low level. That is, the 19th and 20th NMOS transistors MN19 and MN20 are turned on to connect the ground voltage and the sixth node ND6 to a low level. The LSB reset is allocated a time of 3 us.

After the reset is completed, a bit line precharge is performed. The precharge control signal PRECHb is applied to the low level to precharge the sensing node SO to the high level, and the bit line select signal BLSE is applied to the high level to turn on the third NMOS transistor MN3 to turn on the bit. Precharge the bit line by connecting the line and the sensing node (SO). Bitline precharge is performed for 6us.

After the bit line precharge, the sensing node SO is floated by applying a precharge control signal PRECHb to a high level (S51). In operation S52, the bit line is changed by changing the bit line selection signal BLSE to a low level in order to read data of a memory cell connected to the bit line.

When the bit line is floated, the voltage level of the bit line is changed during the read time (EVALUATION) according to the program state of the memory cell. In other words, if the memory cell is programmed, the current does not fall out, and thus the voltage precharged to the bit line does not fall to maintain the high level. However, if the memory cell is an erased cell, the current is removed and the bit line is changed to 0V.

In this case, since the sensing node SO is floated before the bit line is floated as in step S51, the sensing node SO maintains a high level when the memory cell is a programmed cell, and when the memory cell is an erase cell, SO) exits the current to some extent and lowers the voltage level.

Thereafter, the bit line selection signal BSLE is applied at a high level to turn on the third NMOS transistor MN3 to connect the bit line and the sensing node SO. In this case, if the memory cell is the erase cell, the sensing node SO is also connected to the connected bit line, and the current exits to 0V (S53 and S54). As shown in FIG. 5, in spite of a short read time (6us + 3us), the sensing node SO may confirm that the current is sufficiently exited in the case of the erased cell, and thus the voltage may escape to 0V.

The LSB read and program control signals LSBREADPROG are kept at a high level as shown in FIG. 4B until the first LSB read control signal LSBREAD1 is given a high level, thereby maintaining the 15th NMOS transistor MN15 turned on. .

Therefore, the data read from the sensing node SO may be transferred to the data line while the fifteenth NMOS transistor MN15 is turned on. In this case, before starting the LSB operation, the first latch 321 of the MSB latch unit 310 must be set so that the 16th NMOS transistor MN16 is turned on. Before the first LSB read control signal LSBREAD1 is applied, the control signal LSBPASS for reading data is applied, and the data of the sensing node SO is quickly output to the data line through the 21st NMOS transistor MN21.

That is, after the data of the sensing node SO is latched in the second latch unit 331, the read speed is higher than that of the data output to the data line.

Even if the read speed is increased as described above, when the memory cell is a program cell, the sensing node SO keeps its high level in a floating state even after the read time ends, and in the case of an erase cell, the sensing node ( Since SO) is sufficiently changed to 0V, data can be read more stably.

The first LSB read control signal LSBREAD1 is applied at a high level to read data of the memory cell into the second latch 331 (S55 to S57). That is, if the memory cell is a program cell, the sensing node SO maintains a high level to turn on the twentieth NMOS transistor MN20. The nineteenth NMOS transistor MN19 is turned on by the second LSB read control signal LSBREAD1, and the sixth node ND6 loads low-level data. If the sixth node ND6 is at a low level, the fifth node ND5 is at a high level.

As described above, the sensing node SO may be sufficiently changed to 0 V even with a short read time with respect to the erase cell by the LSB read and the program control signal LSBREADPROG, and the data line may be quickly read through the fifteenth NMOS transistor. It is also possible to transmit.

As described above, the LSB read operation is performed by the fifteenth NMOS transistor MN15 and the sixth NMOS transistor MN6 operated by the LSB read and program control signal LSBREADPROG and the MSB read and program control signal MSBREADPROG. By performing the MSB read operation, the sensing node S0 can sufficiently read data even in a short read time, and transmit the read data to the data line more quickly.

In the read operation of the page buffer 300 operating as described above, the LSB read takes 39us and the MSB read takes 21us, which can be confirmed to be shorter than before.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the page buffer circuit and the operation method of the multi-level cell flash memory according to the present invention can shorten the data read time by allowing the transistor of the page buffer which used the program to operate in the read operation, By changing the application period of the precharge voltage, it is possible to stably read data from the sensing node.

Claims (11)

An upper bit register configured to sense the voltage of the sensing node in response to the first read control signal to store upper sensing data and output inverted upper sensing data, or to store input data and to output inverted input data; In response to a second read control signal, the voltage of the sensing node is sensed to store first lower sensed data and output inverted first lower sensed data, or in response to a third read control signal, A lower bit register configured to sense a voltage to store second lower sensing data and output inverted second lower sensing data; An upper bit read and program control circuit connected between the sensing node and the upper bit register to transmit a voltage of the sensing node to a data input / output line by an upper bit read and a program control signal; And A lower bit read and a program control circuit connected between the sensing node and the lower bit register to transmit a voltage of the sensing node to a data input / output line by a lower bit read and a program control signal, The sensing node is precharged for bit line procharging, is connected to the bit line, precharges the bit line, and then floats before disconnecting from the bit line. . The method of claim 1, The upper bit read and program control signal, A page buffer circuit of a multi-level cell flash memory, characterized in that it is an output signal of a NOR gate using an upper bit program control signal and a first read signal as an input signal. The method of claim 1, The lower bit read and program control signals, A page buffer circuit of a multi-level cell flash memory, characterized in that it is an output signal of a NOR gate using a low-bit program control signal and second and third read signals as input signals. The method of claim 1, A bit line selection circuit for selecting one of the pair of bit lines in response to the bit line selection signals and the signals discharged, and connecting the selected bit line to the sensing node; And And a precharge circuit for precharging or floating the sensing node to an internal voltage in response to a precharge control signal. The method of claim 1, The upper bit register is A sensing circuit configured to sense a voltage of the sensing node in response to the first read control signal and to generate the upper sensing data; A latch circuit for latching the upper sensing data and outputting inverted upper sensing data, or latching the input data and outputting the inverted input data; And And a latch reset circuit for initializing the latch circuit in response to a reset control signal. The method of claim 1, The lower bit register, A sensing circuit configured to sense a voltage of the sensing node in response to the second or third read control signal and to generate the first or second lower sensing data; And And a latch circuit configured to latch the first lower sensing data, output the inverted first lower sensing data, or latch the second lower sensing data, and output the inverted second lower sensing data. Page buffer circuit of level cell flash memory. A memory cell array including a plurality of bit line pairs and a plurality of multi-level cells each connected to a plurality of word lines; One to each of the plurality of pairs of bit lines, each of which outputs data to be programmed to one of a multi-level cell or the like connected to a pair of corresponding bit lines in a program operation; Page buffer circuits for outputting data read from one of the multi-level cells connected to a pair of bit lines to a data line by a read and program control signal before a latch operation; And A plurality of page buffer circuits, one corresponding to each of the plurality of page buffer circuits, further connected to a data input / output line to transfer data to be programmed to the page buffer circuit, or to output read data transmitted from the page buffer circuit to a data input / output line. A multi level cell flash memory device comprising Y decoder circuits. The method of claim 7, wherein Each of the plurality of page buffers, An upper bit register configured to sense the voltage of the sensing node in response to the first read control signal to store upper sensing data and output inverted upper sensing data, or to store input data and to output inverted input data; In response to a second read control signal, the voltage of the sensing node is sensed to store first lower sensed data and output inverted first lower sensed data, or in response to a third read control signal, A lower bit register configured to sense a voltage to store second lower sensing data and output inverted second lower sensing data; An upper bit read and program control circuit connected between the sensing node and the upper bit register to transmit a voltage of the sensing node to a data input / output line by an upper bit read and a program control signal; And A lower bit read and a program control circuit connected between the sensing node and the lower bit register to transmit a voltage of the sensing node to a data input / output line by a lower bit read and a program control signal, And the sensing node is precharged for bit line procharge, and is floated after being connected to the bit line to precharge the bit line and before disconnecting from the bit line. In the read operation method of the flash memory device, Precharging the sensing node of the page buffer in response to the read command; Precharging a bit line by connecting the precharged sensing node and a bit line selected according to an input address; Plotting a sensing node of the page buffer; Cutting off the connection between the bit line and the sensing node to induce a change in the voltage level of the bit line according to whether the memory cell is programmed; Connecting the bit line and a sensing node; And Outputting upper or lower read data according to a voltage level of a sensing node connected to the bit line to a data output line according to upper or lower bit read and program control signals. Read operation method of a multi-level cell flash memory comprising a. The method of claim 9, The read and program control signals, And a read operation signal of the page buffer and a result of NOR operation of an upper bit or lower bit program control signal. The method of claim 9, After outputting the upper or lower read data to the data output line according to the upper or lower bit read and program control signal, And latching into an upper bit latch or a lower bit latch circuit according to the read control signal of the page buffer.

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