KR100937846B1 - Controller - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a controller of a display device having improved EMI (Electro Magnetic Interference) characteristics. The present invention relates to a timing signal applied to a gate driver and a source driver, and a color signal to an source mode and an odd mode. In the controller to be applied according to the mode, it characterized in that the pins for outputting the color signal of the even mode and the odd mode to the source driver are alternately formed.

Electro Magnetic Interference (EMI), Source Driver, Even Mode, Eod Mode, Color Signal Output Pin, Controller

Description

Controller

1 is a block diagram schematically illustrating an internal structure of a general liquid crystal display device.

2 is a view showing the pin arrangement of the conventional controller

3 is a schematic view showing a signal is applied to the color signal output pin of the conventional controller

Figure 4 is a schematic diagram showing a color signal output pin and a signal applied to the output signal of the controller of the present invention

5 is a diagram showing the pin arrangement of the controller of the present invention.

6 is a schematic diagram showing a state in which a signal is applied to the controller of the present invention

7 is a graph showing the EMI phenomenon according to the frequency when the color signal output pin is formed for each odd mode and even mode

8 is a graph illustrating EMI phenomenon according to frequency when the odd mode and even mode color signal output pins are alternately formed.

* Description of symbols on the main parts of the drawings *

30: Controller 31: R, G, B Data Output Pin

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a controller having improved EMI (Electro Magnetic Interference) characteristics.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention has been developed in various ways such as a television and a computer monitor for receiving and displaying broadcast signals.

In order to use such a liquid crystal display as a general screen display device in various parts, it is a matter of how high quality images such as high definition, high brightness and large area can be realized while maintaining the characteristics of light weight, thinness and low power consumption. Can be.

A general liquid crystal display device may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second glass substrates bonded to each other with a predetermined space; It consists of a liquid crystal layer injected between said first and second glass substrates.

Here, the first glass substrate (TFT array substrate) has a plurality of gate lines arranged in one direction at regular intervals, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing a gate line and a data line, and a plurality of thin film transistors switched by signals of the gate line to transfer the signal of the data line to each pixel electrode. Is formed.

In the second glass substrate (color filter array substrate), a light shielding layer for blocking light in portions other than the pixel region, an R, G, and B color filter layer for expressing color colors are common to implement an image. An electrode is formed.

The driving principle of the general liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal by optical anisotropy, thereby representing image information.

Currently, an active matrix LCD, in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, is attracting the most attention due to its excellent resolution and ability to implement video.                         

Hereinafter, a driving method of a conventional liquid crystal display device will be described with reference to the accompanying drawings.

1 is a block diagram schematically illustrating an internal structure of a general liquid crystal module.

As shown in FIG. 1, a general liquid crystal module includes a liquid crystal panel 1 having a thin film transistor array including a gate line and a data line, a gate driver 8 for driving the gate line, and a data line. A control unit that receives a signal from the source driver 9 and the system (or host) 10 and outputs a timing signal to the gate driver 8, the gamma reference voltage unit 5, and the source driver 8. (Controller) 3, a DC / DC converter 4 for receiving a signal from the system 10 and the controller (controller) 3 and outputting a required voltage, and the DC / DC converter 4 And a common voltage generator 6 that receives a signal from the controller (controller) 3 and applies a common voltage signal to the liquid crystal panel 1, and receives a gate voltage signal from the DC / DC converter 4. Inn in with driver (8) A gate driver interface (7), applying a voltage received from the DC / DC converting unit (4) that it is formed to a predetermined conversion to the gamma reference voltage unit (5) to be applied to the source driver (9).

The controller 3 processes the image data of the system 10 to fit the panel and generates various control signals.

The main role of the controller (controller) is to receive the RGB signal from the system 10, to distribute the data that can be processed by each source driver (9), to control the gate driver (8), the source driver (9) ) And the basic timing of the controller (controller) 3 is set in accordance with the timing of the gate driver 8.

Inside the control unit (controller) 3, basically several blocks are formed.

Typically, there is a polarity bit generation block, a gate / data clock divider block, a data processing block, and the like, and a timing simulation is performed to verify the entire function.

In addition, the control unit (controller) 3 performs a power on reset (Power_On_Reset) function, an abnormality detection function of the DC / DC converter 4, an abnormality detection function of an input signal, and an interface with the system 10 if necessary. It may be formed with a receiver circuit.

In the liquid crystal panel 1, thin film transistors are formed in each pixel, a gate electrode of the thin film transistor is connected to a gate line as a scan line, and a source electrode of the thin film transistor is connected to a data line as a signal line.

When the ON signal Vg_on is applied to the scan line, a channel is formed in the thin film transistor connected to the gate line, and the voltage of the signal line is applied to the pixel electrode via the source electrode and the drain electrode.

The resolution of the liquid crystal panel 1 is determined according to the number of gate lines and data lines.

The gate driver 8 which drives the gate line has a relatively simple structure because only the ON / OFF signal is sequentially applied to the gate line.

That is, the gate driver 8 adjusts the output logic level of the bi-direction shift register and the shift register, which sequentially move the data (start pulse) value having a logic input of "1" by one line time interval. A single or multiple gate driver IC is composed of a level shifter that converts the gate line to an ON / OFF voltage and a current buffer that amplifies the current in consideration of the load of the gate line.

The adjacent gate driver IC sequentially transfers logic values to the final stage in synchronization with a clock signal through the SIR-SIL and SOL-SOR connections according to the condition of the L / R terminal that determines the shift direction. The liquid crystal panel 1 is usually provided with three to six gate drivers.

The source driver 9 latches data of each RGB sequentially received in accordance with the dot clock by the controller (controller) 3 to set the timing scheme of the Dot at a Time Scanning (Line at a Time) method. Switch to Scanning. Every horizontal line period, data stored in the first latch is transferred to the second latch in accordance with a transfer enable signal. The data stored in the second latch is converted into an analog voltage by the A / D converter, and is then applied to the data line via a current buffer.

The image quality of the liquid crystal panel 1 depends particularly on the setting of the gamma reference voltage. The gamma reference voltage is determined in consideration of the electro-optical characteristics of the liquid crystal panel.

The DC / DC converter 4 and the gamma voltage unit 5 provide reference voltages for driving the gate driver 8 and the source driver 9.

The power supply unit of the LCM is composed of a DC / DC converter 4 and a backlight inverter (not shown). The DC / DC converter 4 often uses a single chip.

The main voltage sources are a 5V or 3.3V supply of logic circuits, an ON / OFF supply across the gate line, a gamma reference supply, and a common voltage (Vcom) signal supply. The liquid crystal panel module generates a necessary voltage by boosting or reducing the power supply voltage required for each circuit unit from a single power supply regardless of a notebook or a monitor. Voltage conversion circuits are an important issue in notebook TFT LCD modules where power consumption is more important than monitors.

Considerations in the design of the DC / DC converter 4 are ripple, efficiency, in-rush current, and start-up voltage of the output voltage.

If the reflow gamma reference voltage of the output voltage of the DC / DC converter 4 is changed, the image quality is deteriorated. Therefore, a choke coil is placed at the output terminal of the DC / DC converter 4 to filter the ripple.

Efficiency of the DC / DC converter 4 is a very important factor for lowering module power consumption. If the efficiency of the DC / DC converter 4 is 70%, the power consumption of the DC / DC converter 4 is about 0.27W (0.9x0.3). The power consumption of the TFT LCD module is about 1.43W, and about 20% is consumed by the DC / DC converter 4.

Hereinafter, a conventional controller will be described with reference to the accompanying drawings.

2 is a view showing a pin arrangement of a conventional controller, Figure 3 is a schematic diagram showing a state in which a signal is applied to the color signal output pin of the conventional controller.

As shown in FIG. 2, the color signal output pins of the conventional controller 20 are formed in blocks for each of the odd mode signals OR, OG, and OB and the even mode signals ER, EG, and EB. do. Therefore, the said color signal output pin is provided with the number of gradations with respect to the predetermined | prescribed mode predetermined color signal. In the figure, the number of gradations is six, and six output pins are formed for each color signal.

In this case, as shown in FIG. 3, the controller 20 outputs an odd mode signal and an even mode signal for the first frame and the second frame for each gray level. Accordingly, the conventional controller 20 alternately outputs signals of the odd signal output pin and the even signal output pin, and the same mode-specific pins are configured in the same block and are adjacent to each other.

Therefore, pins adjacent to each other in a predetermined mode are continuously output signals of the same polarity to each other electromagnetic signal interference, deteriorating the EMI (Electro Magnetic Interference) characteristics.

The conventional controller as described above has the following problems.

In the case of a conventional controller, the color signal data (R, G, B Data) output is divided into even and odd, and is output after the odd output pin array. It is in the form of an output pin array. As described above, since the color signal output pins of the controller are arranged separately for the odd block and the even block, when the signal is output for each odd mode, unnecessary electromagnetic fields are generated at adjacent pins of the odd block. When the signal is output by the even mode, an unnecessary electromagnetic field is formed at adjacent pins of the even block to interfere with the signal.

Therefore, in the conventional controller having a structure in which the pins for outputting the signal of the predetermined mode are adjacent to each other, the EMI characteristics are deteriorated because an unnecessary electromagnetic field is formed to interfere with the signal.

The present invention has been made to solve the above problems, to provide a controller that improves the EMI (Electro Magnetic Interference) characteristics, an object thereof.

In the controller of the present invention for achieving the above object, a timing signal is applied to each of the gate driver and the source driver, and the controller is configured to apply the color signal to the source driver in an even mode and an odd mode. The pins for outputting the color mode signals of the odd mode to the source driver are alternately formed.

The pin for outputting the color signal to the source driver is provided twice the number of the color signal multiplied by the number of gradations.

The color signal is R, G, B.

The gradation number is 6 or 8.

Hereinafter, the controller of the present invention will be described in detail with reference to the accompanying drawings.

Figure 4 is a schematic diagram showing a color signal output pin and a signal applied to the output signal of the controller of the present invention.

As shown in FIG. 4, the R, G, and B-data output pins 31 of the controller 30 of the present invention are in an odd mode in the number of gray levels (6, 8, or more) for each of the R, G, and B color signals. It is formed for (odd mode) and even mode (even mode). That is, when the number of gradations is 6, the R, G, and B-data output pins 31 of the controller 30 have 3 (R, G, B) x 6 (number of gradations) x 2 (odd, even) = 36 pieces. Pins are provided, and when the number of gradations is 8, 3x8x2 = 48 pins are provided.

In the case of the liquid crystal display currently manufactured, the number of grayscales of the R, G, and B data is manufactured to 6 to 8, which can be implemented by further increasing the number of grayscales thereafter.

Here, the odd mode output pins and even mode output pins of the R, G, and B-data output pins 31 are alternately formed. That is, as shown in FIG. 4, when the number of gray levels is 6, the output pins of the controller 30 are sequentially rotated from the bottom to RO0, RE0, RO1, RE1, ...., RO5, RE5, GO0, GE0, ... ., GO5, GE5, BO0, BE0, ....., BO5, BE5.

In this case, the R, G, and B-data output pins 31 maintain the above-described order (RO0, RE0, ....., BO0, BE5) and may be formed in order from the top.

5 is a view showing the pin arrangement of the controller of the present invention, Figure 6 is a schematic diagram showing a state that a signal is applied to the controller of the present invention.

As shown in FIG. 5, the R, G, and B-data output pins 31 of the controller 30 of the present invention may have an odd signal output pin and an even signal from the south direction of the controller 30 to the west direction. ) The signal output pins are alternately formed. In addition, the controller 30 of the present invention includes the ground voltage applying pins GND and VSS for applying a ground voltage in addition to the R, G, and B-data output pins 31, and the power supply voltage applying pin part VDD for applying a power supply voltage. ), Input pins (RAMP, RBMP, RCMP) receiving R, G, and B color signals from the test pin system (TEST) that performs the test, timing signal input pins (RACLK, RBCML RCCLK, Timing signal output pins (I_SSCR, SOE, POL, I) that apply timing signals to the DFI, DFI, ESEL, FLK_S, GOE_E1, SOE_E1, GOE_S1, DEONLY, POL_OT, IDI, SOE_E0, SOE_S, SSC_S, gate drivers or source drivers. -REVO, I_REVE, I_SSPR, I_SSCL, I_SSPL, etc. are further provided.

As such, the color signal output pins 31 of the controller 30 may include the odd signal output pins RO0 to RO5, GO0 to GO5, BO0 to BO5, and even signal output pins RE0 to RE5, GE0 to GE5, and BE0 to. BE5) are alternately formed, and as shown in FIG. 6, in the first frame (1 frame), the odd mode signal is sent to the source driver side to the odd signal output pins RO0 to RO5, GO0 to GO5, and BO0 to BO5. The even mode signal is applied to the even signal output pins RE0 to RE5, GE0 to GE5, and BE0 to BE5 to the source driver in the second frame.

That is, an odd mode signal output pin and an even mode signal output pin which are output pins of different modes are formed adjacent to each other so that a signal is not applied to the adjacent pins for each frame, and one pin is interposed between each signal output pin. Since the signal is being applied, the electromagnetic interference (EMI) is minimized when the signal is applied.                     

The main role of the controller having the above pin assignment is to receive the R, G, and B-data signals through the system (host) interface, distribute the data to each source driver IC, and control the gate driver IC. Therefore, the basic timing of the controller is set in accordance with the timing of the source driver IC and the gate driver IC.

Controllers vary greatly depending on panel characteristics such as gate line delay and charge rate of TFTs. Unlike gate and source drivers, controllers use their own products. 3K ~ 4K gates can be used as a controller for basic functions.

The interior of such a controller can be divided into several blocks.

Typical examples include a polarity bit generation block, a gate start pulse generation block, a gate / data clock divider block, a data processing block, and the like. This is done by timing simulation to verify the full functionality.

The controller is equipped with a power on reset (Power_On_Reset) function, an abnormality detection function of a DC / DC converter, an abnormality detection function of an input signal, a receiver circuit that interfaces with a system, and a gamma level ( gamma level) Voltage generator circuits may be added.

7 is a graph illustrating EMI phenomenon according to frequency when the color signal output pins are formed for each of the odd mode and the even mode. FIG. 8 is a graph illustrating the EMI phenomenon according to the frequency when the odd mode and even mode color signal output pins are alternately formed. The graph shows EMI phenomenon.

As shown in FIG. 7, when R, G, and B-data output pins are formed by blocking for each mode for each odd mode and even mode, signals are applied to pins adjacent to each other between the output pins blocked for each mode. As a result, electromagnetic interference is intensified between adjacent pins.

On the other hand, as shown in FIG. 8, when the odd mode output pin and the even mode output pin are alternately formed, when the signals are applied to one pin in the case of adjacent pins, the signal is not applied to the immediately adjacent pin. Therefore, electromagnetic interference between the adjacent pins is minimized.

In particular, as shown in FIGS. 7 and 8, when the odd mode / even mode signal output pins are alternately formed, the odd mode output pins and the even mode output pins are 150 MHz or more compared with the respective blocks. EMI reduction effect in the high frequency region is remarkable.

On the other hand, as described above, the controller configured by alternating the odd mode output pin and the even mode output pin to improve the EMI characteristic can be commonly applied to a general display device as well as a liquid crystal display.

The present invention is not limited to the above embodiments, but is within the scope that can be modified by those skilled in the art within the scope of the technical idea of the present invention.

 The controller of the present invention as described above has the following effects.

When the color signal is output from the controller to the source driver by the odd mode and the even mode, the array of the color signal output pins of the controller is alternately formed with the odd mode and the even mode so that signals of the same mode are not applied to adjacent output pins. This improves EMI between the output pins and adjacent sections of the controller.

Claims (5)

A controller for applying a timing signal to a gate driver and a source driver, and applying color signals to the source driver separately in an even mode and an odd mode, The controller includes an output pin for dividing the R, G, and B color signals into an even mode and an odd mode for each gray level, and the output pins output the color signals of the even mode and the odd mode for each gray level of the color signals. Output pins are alternately located And the output pins are connected to the source driver so that color signals of an even mode and an ord mode are output to the source driver in accordance with the number of gradations of the color signals. delete delete The method of claim 1, And the number of gradations is six. The method of claim 1, And the number of gradations is eight.

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