KR100936770B1 - Voltage Controlled Oscillator Using Sub-feedback Loop and Analog-Digital Converter Having The Same - Google Patents

Abstract

The analog to digital converter includes a voltage controlled oscillator and a phase detector. The voltage controlled oscillator includes a plurality of delay stages connected by a ring-shaped main loop and sub-feedback stages connected to the plurality of delay stages to form at least one sub-feedback loop, and the plurality of delay stages in response to an input signal. Each of the output terminals outputs a plurality of oscillation signals having a phase difference from each other. The phase detector detects a phase change amount of the plurality of oscillation signals and determines a digital value corresponding to the input signal based on the detected phase change amount.

Description

Voltage Controlled Oscillator Using Sub-feedback Loop and Analog-Digital Converter Having The Same}

The present invention relates to a voltage controlled oscillator and an analog to digital converter, and more particularly, to a voltage controlled oscillator using a sub-feedback loop and an analog to digital converter including the same.

Recent advances in CMOS technology to the nanometer level have made it difficult to design high-performance analog-to-digital converters due to reduced supply voltages and changes in process, voltage, and temperature (PVT). Due to these environmental factors, research on time-based analog-to-digital converters using voltage controlled oscillators is being conducted. Unlike conventional analog-to-digital converters that process voltage information using op amps or comparators, analog-to-digital converters using voltage controlled oscillators (VCOs) provide flip-flops for low supply voltages on fine CMOS process scales. Logic gates are used to process phase information. Analog-to-digital converters using voltage-controlled oscillators have the advantage of reducing power consumption by operating at low voltages using digital circuits.

Important building blocks in analog-to-digital converters using voltage-controlled oscillators are the voltage-controlled oscillators, which include the linearity and tuning range of the voltage-controlled oscillator (the difference between the maximum and minimum values of the output frequency of the voltage-controlled oscillator) and the number of phases (detectable). The number of phases) determines the resolution and sampling rate of the analog to digital converter. However, despite the importance of voltage controlled oscillators, studies on the design of voltage controlled oscillators for analog-to-digital converters have not received much attention. Conventionally, an inverter is used as a delay cell of a voltage controlled oscillator in the form of a ring oscillator. As a result, an input swing range is limited to a specific level in order to use an oscillation signal in a period where linearity is maintained. This limitation of input swing range and insufficient number of phases degrades the performance of analog-to-digital converters.

Therefore, the need for an analog-to-digital converter and a voltage controlled oscillator for improving the resolution and linearity by securing a wide tuning range is increasing.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a voltage controlled oscillator having an improved resolution and linearity using a sub-feedback loop and a body bias voltage, and an analog-to-digital converter including the same.

Another object of the present invention is to provide a voltage controlled oscillation method of improving linearity by subfeeding an oscillation signal and applying a body bias voltage.

According to an embodiment of the present invention, an analog-to-digital converter includes a voltage controlled oscillator and a phase detector. The voltage controlled oscillator includes a plurality of delay stages connected to a ring-shaped main loop and sub-feedback stages connected to the plurality of delay stages to form at least one sub-feedback loop, and the plurality of delay stages in response to an input signal. Each of the delay stages outputs a plurality of oscillation signals having a phase difference from each other. The phase detector detects a phase change amount of a plurality of oscillation signals and determines a digital value corresponding to the input signal based on the detected phase change amount.

Each of the plurality of delay stages and the sub-feedback stage may include a differential amplifier and a frequency controller. The differential amplifier may invert and amplify the output signal of the previous delay stage. The frequency controller adjusts a frequency of the plurality of oscillation signals by adjusting a delay time during which the differential amplifier inverts and amplifies an output signal of the previous delay stage in response to the input signal, and adjusts the frequencies of the plurality of oscillation signals. The frequency gain, which is the ratio of the frequency change of the plurality of oscillation signals to the change of the signal, may be adjusted.

The bias voltage may include a first body bias voltage and a second body bias voltage, and the frequency controller may include a pull-up controller that assists a pull-up operation of the differential amplifier in response to the input signal and the first body bias voltage; And a pull-down controller configured to assist a pull-down operation of the differential amplifier in response to the input signal and the second body bias voltage.

The differential amplifier may include a first NMOS transistor pair and a first PMOS transistor pair. The first NMOS transistor pair may have a source terminal connected to a first power supply voltage and may receive an output signal of the previous delay stage through a gate terminal and output an output signal of the current delay stage to a drain terminal. The first PMOS transistor pair may have a source terminal connected to a second power supply voltage, one gate terminal connected to the other drain terminal, and a drain terminal connected to the drain terminal of the first NMOS transistor pair. Can be.

The pull-up control unit may include a source terminal connected to the second power supply voltage, a drain terminal connected to a drain terminal of the first NMOS transistor pair, and receiving the input signal through a gate terminal, and receiving the first body bias voltage through a body. The pull-down controller may include an applied second PMOS transistor pair, wherein the pull-down controller includes a source terminal connected to the first power voltage and a drain terminal connected to a drain terminal of the first NMOS transistor pair. And a second NMOS transistor pair receiving an input signal, the second body bias voltage applied to the body, and having an absolute threshold voltage greater than an absolute value of the threshold voltage of the second PMOS transistor pair. have.

The sum of the absolute value of the threshold voltage of the second PMOS transistor and the threshold voltage of the second NMOS transistor may be equal to the difference between the first power voltage and the second power voltage.

Increasing the common mode voltage of the first body bias voltage and the second body bias voltage reduces the absolute value of the frequency gain in the first region of the input voltage and the absolute value of the frequency gain in the second region. Increasing the differential mode voltage between the first body bias voltage and the second body bias voltage decreases the absolute value of the frequency gain in the first region and the absolute value of the frequency gain in the second region. can do.

The analog-to-digital converter may further comprise a sample / hold circuit for sampling and temporarily holding the analog signal to supply the input signal to the voltage controlled oscillator.

The phase detector may include a phase quantizer for detecting and quantizing a phase change amount of each of the plurality of oscillation signals in response to a sampling clock, and a decimation filter for decimating an output signal of the phase quantizer.

According to an embodiment of the present invention, a voltage controlled oscillator is connected to a plurality of delay stages connected to a plurality of delay stages and a plurality of delay stages to form a main loop in a ring shape. A plurality of oscillation signals having a phase difference from each output terminal of the plurality of delay stages in response to an input signal, wherein the plurality of delay stages and the sub-feedback stages each include a differential amplifier , A pull-up control unit and a pull-down control unit. The differential amplifier inverts and amplifies the output signal of the previous delay stage. The pull-up controller controls a pull-up operation of the differential amplifier in response to the input signal to adjust a delay time for the differential amplifier to invert and amplify the output signal of the previous delay stage, and in response to a bias voltage Adjust the frequency gain, which is the ratio of the frequency change of the plurality of oscillation signals to the change. The pull-down controller controls the pull-down operation of the differential amplifier in response to the input signal to adjust the delay time for the differential amplifier to invert and amplify the output signal of the previous delay stage, and adjust the frequency gain in response to a bias voltage. Adjust.

According to an embodiment of the present invention, a voltage controlled oscillation method according to an embodiment of the present invention inverts and amplifies an output signal of each of a plurality of delay stays connected to a ring-shaped main loop in response to an analog input signal. Providing to a delay stage, inverting at least one output signal of the plurality of delay stages and feeding back an input signal of at least one or more previous delay stages to generate a plurality of oscillation signals at each output stage of the plurality of delay stages And adjusting a first bias voltage and a second bias voltage applied to the plurality of delay stages so that the frequencies of the plurality of oscillation signals for the change of the analog input signal in the first region and the second region of the input signal. Adjusting a frequency gain that is a rate of change.

The voltage controlled oscillator and the analog-to-digital converter including the same according to an embodiment of the present invention can improve resolution and linearity by using a sub-feedback loop and a body bias voltage.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, a voltage controlled oscillator and an analog to digital converter according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

1 is a block diagram illustrating an analog-to-digital converter according to an embodiment of the present invention.

Referring to FIG. 1, the analog-to-digital converter 100 includes a sample / hold circuit 110, a voltage controlled oscillator 120, and a phase detector 130.

The sample / hold circuit 110 receives the analog signal SA, samples the sample, and temporarily holds the analog signal SA to provide the input signal SI of the voltage controlled oscillator 120.

The voltage controlled oscillator 120 outputs a plurality of oscillation signals SO in response to the input signal SI. The voltage controlled oscillator 120 changes and outputs frequencies of the plurality of oscillation signals SO in proportion to or inversely proportional to the magnitude of the input signal SI.

Since the phase change amount of the oscillation signal for a predetermined time is proportional to the integral value of the frequency, the process of adjusting or detecting the phase change amount of the power generation signal may be understood as the same as the process of adjusting or detecting the frequency of the oscillation signal. Hereinafter, in the present specification, the phase may be interpreted in the meaning of frequency, and the frequency may also be interpreted in the meaning of phase. In addition, in describing an embodiment of the present invention, the tuning range means a difference between the maximum value and the minimum value that can be effectively used in the analog-to-digital converter among the frequencies of the output signal of the voltage controlled oscillator, and the number of phases during the sampling period. It means the number of unit phases that can be detected.

The voltage controlled oscillator 120 may be implemented as a ring oscillator in which a plurality of delay stages are connected in a ring form, and use phase information of a plurality of oscillation signals having a phase difference while reducing a tuning range by using a sub-feedback loop. Can improve the resolution.

The phase detector 130 detects a frequency or phase change amount of the output signal SO of the voltage controlled oscillator 120, converts the detected phase change amount into a digital signal SD, and outputs the converted signal.

The phase detector 130 includes a phase quantizer 131 and a decimation filter 132. The phase quantizer 131 detects and quantizes a phase change amount of each of the plurality of oscillation signals in response to the sampling clock SS. The decimation filter 132 decimates the output signal SQ of the phase quantizer.

FIG. 2 is a waveform diagram illustrating each signal flow of the analog-digital converter of FIG. 1.

Referring to FIG. 2, in each period of the sampling clock SS, the sample / hold circuit 110 samples and uniformly holds an analog signal and provides it to the voltage controlled oscillator 120 as an input signal SI. The voltage controlled oscillator 120 outputs an oscillation signal SO having a frequency proportional to the input signal SI. At this time, if a plurality of oscillation signals are output, rather than outputting a single oscillation signal, the interval of detectable phase change can be further subdivided and the resolution can be increased. For example, in the waveform diagram of FIG. 2, eight oscillation signals may be output to detect up to a phase change amount of 1/8 interval of a detectable phase change amount when using a single oscillation signal.

The phase detector 130 detects a phase change amount of the oscillation signal. For example, the phase quantizer 131 of the phase detector 130 may detect the phase change amount PS by counting the number SQ of the unit phase change amount during each period of the sampling clock SS.

3 is a conceptual diagram illustrating a voltage controlled oscillator according to an embodiment of the present invention included in the analog to digital converter of FIG. 1.

Referring to FIG. 3, the voltage controlled oscillator is implemented as a ring oscillator in which a plurality of delay stages are connected in a ring shape. The voltage controlled oscillator includes delay stages MDS1 to MDS8 forming a main loop and subfeedback stages SDS1 to SDS8 forming a subfeedback loop.

An output terminal of each of the plurality of delay stages outputs an oscillation signal having a phase difference from each other. The voltage controlled oscillator according to an embodiment of the present invention includes subfeedback stages SDS1 to SDS8 for forming a shorter subfeedback loop in addition to the main loop. The sub-feedback loop may be a loop having a smaller length than the main loop. In FIG. 3, eight delay stages MDS1 to MDS8 are connected in series to form a main loop, and subfeedback stages SDS1 to SDS8 for shortening an oscillation path of the main loop are connected to each other. In the embodiment shown in FIG. 3, the sub-feedback stages SDS1 to SDS8 feed back the output signal of each delay stage MDS1 to MSD8 to the input signal of the delay stage one step earlier. For example, the output signal of the third delay stage MDS3 is provided to the input signal of the second delay stage MDS2 via the sub-feedback stage SDS2. The output signal of the fourth delay stage MDS4 is provided as an input signal of the third delay stage MDS3 via the sub-feedback stage SDS3. Similarly, each delay stage is provided as an input signal of the delay stage one step before the sub-feedback stage. In the embodiment illustrated in FIG. 3, eight delay stages and sub-feedback stages are used, but the number of delay stages and the number of sub-feedback stages may be freely modified, and the connection relationship between the sub-feedback stages may also be freely modified.

4 is a block diagram illustrating another exemplary embodiment of the voltage controlled oscillator of FIG. 3.

Referring to FIG. 4, the voltage controlled oscillator includes a plurality of delay stages MSD1 to MSD31 for receiving a differential input signal and inverting the differential input signal, and outputs the oscillation signals output from the respective output stages of the plurality of delay stages MSD1 to MSD31. It includes sub-feedback stages SDS1 to SDS8 that feed back one or more steps. In order for oscillation to occur, the output signal of one delay stage can be connected directly to the next delay stage or can be connected alternately.

Analog-to-digital converter according to an embodiment of the present invention can increase the number of phases by using the phase information of the plurality of oscillation signals output from the voltage controlled oscillator. In addition, when a conventional analog-to-digital converter increases the number of phases, it is difficult to improve the resolution by reducing the tuning range, whereas the analog-to-digital converter according to an embodiment of the present invention uses a plurality of oscillation signals to adjust the number of phases. While increasing, the subfeedback loop can reduce the reduction in tuning range, thereby improving resolution.

FIG. 5 is a circuit diagram illustrating delay stages MDS1 to MDS31 or sub-feedback stages SDS1 to SDS31 of the voltage controlled oscillator of FIG. 4.

Referring to FIG. 5, each of the delay stages MDS1 to MDS31 or the sub-feedback stages SDS1 to SDS31 includes a differential amplifier 510 and a frequency controller 520.

The differential amplifier 510 receives the output signal of the previous stage, inverts it, amplifies it, and provides the output signal to the next delay stage. The differential amplifier 510 includes first NMOS transistor pairs NM1 and NM2 and first PMOS transistor pairs PM1 and PM2. The first NMOS transistor pairs NM1 and NM2 have a source terminal connected to the first power supply voltage VSS, receive an output signal of a previous delay stage through a gate terminal, and output an output signal of a current delay stage to a drain terminal. . The first power supply voltage VSS may be a ground voltage. In the first PMOS transistor pair PM1 and PM2, a source terminal is connected to the second power supply voltage VDD, one gate terminal is connected to the other drain terminal, and a drain terminal is connected to the first NMOS. It is connected to a pair of transistors. In FIG. 5, the differential amplifier including the first NMOS transistor pair and the first PMOS transistor pair is illustrated as an embodiment, but the number and the conduction types of the transistors may be freely modified according to the embodiment.

The frequency controller 520 adjusts the frequency of the oscillation signal output from the voltage controlled oscillator 120 by adjusting the delay time of the signal in the differential amplifier 510 in response to the input signal SI. The frequency controller 520 outputs an oscillation signal having a frequency corresponding to the magnitude of the input signal SI, and performs analog-to-digital conversion by detecting phase information of the oscillation signal and converting the signal into a digital signal. In addition, the frequency controller 520 improves linearity by adjusting frequency gain which is a ratio of frequency change of the plurality of oscillation signals to change of the input signal using the bias voltages VB1 and VB2.

The frequency controller includes a pull-up controller 520 and a pull-down controller 530. The pull-up control unit 510 and the pull-down control unit 520 assist the pull-up operation and the pull-down operation of the differential amplifier 510 in response to the input signal SI, respectively.

The pull-up control unit 521 includes second PMOS transistor pairs PM3 and PM4. The second PMOS transistor pair PM3 and PM4 has a source terminal connected to the second power supply voltage VDD and a drain terminal connected to the drain terminal of the first NMOS transistor pair NM1 and NM2. The input signal SI is received. In addition, the first body bias voltage VB1 is applied to the body of the second PMOS transistor to adjust the frequency gain of the oscillation signals output from the voltage controlled oscillator.

Pull-down control unit 522 includes second NMOS transistor pairs NM3 and NM4. In the second NMOS transistor pairs NM3 and NM4, a source terminal is connected to the first power supply voltage VSS, and a drain terminal is connected to the drain terminal of the first NMOS transistor pair NM1 and NM2. (SI) is input. In addition, the second body bias voltage VB2 is applied to the body to adjust the frequency gain of the oscillation signals output from the voltage controlled oscillator.

6A and 6B are diagrams showing the relationship between the frequency of the oscillation signal output from the voltage controlled oscillator and the input signal of the voltage controlled oscillator.

Hereinafter, a method of improving linearity of the voltage controlled oscillator will be described with reference to FIGS. 5, 6A, and 6B.

As the input signal SI of the voltage controlled oscillator increases, the frequency of the oscillation signal decreases due to the influence of the second PMOS transistor pairs PM3 and PM4. However, if the input signal SI continues to increase and the second PMOS transistor pairs PM3 and PM4 are turned off, the frequency may be further reduced due to the influence of the second NMOS transistors NM3 and NM4, thereby limiting the tuning range. Decreases.

6A and 6B, the slope of the graph represents the ratio of the frequency change of the oscillation signal to the change of the input signal, that is, the frequency gain. That is, the sharp slope of the graph means that the absolute value of the frequency gain increases, and the slow slope of the graph means the absolute value of the frequency gain decreases. If both of the second PMOS transistor pairs PM3 and PM4 and the second NMOS transistors NM3 and NM4 are turned on by the input signal SI, the slope of the graph is sharper than when the pair of transistors are turned on. In the analog-to-digital converter according to the exemplary embodiment of the present invention, the second PMOS transistor pair PM3 and PM4 and the second yen may be inclined. Linearity can be improved by adjusting the threshold voltage of the transistor so that only one pair of MOS transistor pairs NM3 and NM4 is turned on. For example, the sum of the absolute value of the threshold voltages of the second PMOS transistor pairs PM3 and PM4 and the threshold voltages of the second NMOS transistor pairs NM3 and NM4 is equal to the first power supply voltage VSS and the second power supply. Design the lengths of the second NMOS transistor pairs NM3 and NM4 to be equal to the difference in voltage VDD, and the second PMOS transistor pairs PM3 and PM4 and the second NMOS so that the slope of the graph remains constant. The linearity can be improved by designing the width of transistor pairs NM3 and NM4. In this case, the threshold voltages of the second NMOS transistor pairs NM3 and NM4 may be higher than the threshold voltages of the second PMOS transistor pairs PM3 and PM4.

However, even if the characteristics of the transistors are designed and determined, there may be a change in the manufacturing process. The analog-to-digital converter according to an embodiment of the present invention may further improve linearity by using a body bias voltage. Increasing the first body bias voltage VB1 increases the effective resistance and threshold voltage of the second PMOS transistor pairs PM3 and PM4, and decreasing the second body bias voltage increases the second NMOS transistor pairs NM3 and NM4. Increases the effective resistance and threshold voltage. Therefore, if the common mode voltage (VB1 + VB2) / 2 of the first body bias voltage VB1 and the second body bias voltage VB2 is increased, the absolute value of the frequency gain in the first region AR1 of the input signal is increased. (The magnitude of the slope of LINE 1) becomes flatter and the absolute value of the frequency gain (the magnitude of the slope of LINE 2) in the second region AR2 of the input signal becomes more sharp. In addition, when the differential mode voltage (VB1-VB2) / 2 of the first body bias voltage VB1 and the second body bias voltage VB2 is increased, the absolute value of the frequency gain in the first region AR1 of the input signal is increased. (The magnitude of the slope of LINE 1) and the absolute value (the magnitude of the slope of LINE 2) of the frequency gain in the second area AR2 of the input signal decreases. Therefore, the linearity of the voltage controlled oscillator can be maintained by adjusting the first body bias voltage VB1 and the second body bias voltage VB2 so that LINE 1 and LINE 2 of FIGS. 6A and 6B are aligned.

7 is a diagram illustrating a result of simulating the voltage controlled oscillator of FIG. 4.

The diagram in FIG. 7 is simulated using a CMOS technology of 0.13 micrometers and a supply voltage of 1.2V. Referring to FIG. 7, it can be seen that the voltage controlled oscillator according to the embodiment of the present invention can obtain a tuning range of 0.88 GHz, and the graph is close to a straight line so that the linearity is high.

TABLE 1

Conventional VCO VCO of the present invention Number of phases 6 62 Power Consumption 1.2 mW 15.5mW Time resolution 183 ps 18.3 ps Tuning range 1.41-2.32 GHz 1.02-1.90 GHz Phase noise -92.84 to -92.91 dB -104.3 to -106.5 dB ENOB 8.10bit 11.28bit

Table 1 compares the performance of a conventional voltage controlled oscillator without a sub-feedback loop and body bias technique with a voltage controlled oscillator according to an embodiment of the present invention.

Referring to Table 1, the voltage controlled oscillator of the present invention has a time resolution improved by about 10 times and an effective number of bits (ENOB) improved by about 3.18 bits compared to a conventional voltage controlled oscillator. The number of phases is about 10.3 times better, but the tuning range is not significantly reduced.

As described above, the voltage controlled oscillator and the analog-to-digital converter including the same may improve resolution and linearity by using a sub-feedback loop and a body bias voltage.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1 is a block diagram illustrating an analog-to-digital converter according to an embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating each signal flow of the analog-digital converter of FIG. 1.

3 is a conceptual diagram illustrating a voltage controlled oscillator according to an embodiment of the present invention included in the analog to digital converter of FIG. 1.

4 is a block diagram illustrating another exemplary embodiment of the voltage controlled oscillator of FIG. 3.

FIG. 5 is a circuit diagram illustrating a delay stage or a sub-feedback stage of the voltage controlled oscillator of FIG. 4.

6A and 6B are diagrams showing the relationship between the frequency of the oscillation signal output from the voltage controlled oscillator and the input signal of the voltage controlled oscillator.

FIG. 7 is a diagram illustrating a result of simulating the voltage controlled oscillator of FIG. 4.

Claims (15)

A plurality of delay stages connected in a ring-shaped main loop and sub-feedback stages connected to the plurality of delay stages to form at least one sub-feedback loop, each of the plurality of delay stages in response to an input signal. A voltage controlled oscillator for outputting a plurality of oscillation signals having a phase difference from each other at an output terminal, and adjusting a frequency gain which is a ratio of a frequency change of the plurality of oscillation signals to a change of the input signal in response to a bias voltage; And A phase detector configured to detect a phase change amount of the plurality of oscillation signals and determine a digital value corresponding to the input signal based on the detected phase change amount; Each of the plurality of delay stages and the sub-feedback stages A differential amplifier for inverting and amplifying the output signal of the previous delay stage; And In response to the input signal, the differential amplifier adjusts a delay time of inverting and amplifying the output signal of the previous delay stage to adjust frequencies of the plurality of oscillation signals, and to change the input signal in response to the bias voltage. A frequency controller for adjusting the frequency gain for the The bias voltage includes a first body bias voltage and a second body bias voltage, The frequency control unit A pull-up controller configured to assist a pull-up operation of the differential amplifier in response to the input signal and the first body bias voltage; And A pull-down controller configured to assist a pull-down operation of the differential amplifier in response to the input signal and the second body bias voltage; The differential amplifier is A first NMOS transistor pair having a source terminal connected to a first power voltage and receiving an output signal of the previous delay stage through a gate terminal and outputting an output signal of a current delay stage to a drain terminal; And A source terminal is connected to the second power supply voltage, one gate terminal is connected to cross the other drain terminal, and the drain terminal includes a first PMOS transistor pair connected to the drain terminal of the first NMOS transistor pair. Analog to digital converter characterized in that. delete delete delete The method of claim 1, The pull-up control unit may include a source terminal connected to the second power supply voltage, a drain terminal connected to a drain terminal of the first NMOS transistor pair, and receiving the input signal through a gate terminal, and receiving the first body bias voltage through a body. A second PMOS transistor pair applied; The pull-down control unit has a source terminal connected to the first power supply voltage, a drain terminal connected to a drain terminal of the first NMOS transistor pair, the input signal received through a gate terminal, and the second body bias voltage applied to a body. And a second NMOS transistor pair having a threshold voltage of an absolute value greater than an absolute value of the threshold voltage of the second PMOS transistor pair. The method of claim 5, wherein the sum of the absolute value of the threshold voltage of the second PMOS transistor and the absolute value of the threshold voltage of the second NMOS transistor is equal to the difference between the first power voltage and the second power voltage. An analog-to-digital converter characterized by. The method of claim 6, Increasing the common mode voltage of the first body bias voltage and the second body bias voltage decreases the absolute value of the frequency gain in the first region of the input signal and increases the frequency gain in the second region of the input signal. Increases the absolute value of, Increasing the differential mode voltage between the first body bias voltage and the second body bias voltage decreases the absolute value of the frequency gain in the first region and the absolute value of the frequency gain in the second region. Analog-to-digital converter. The method of claim 1, And a sample / hold circuit for sampling and temporarily holding an analog signal to supply the input signal to the voltage controlled oscillator. The method of claim 1, wherein the phase detection unit A phase quantizer for detecting and quantizing phase shift amounts of the plurality of oscillation signals in response to a sampling clock; And And a decimation filter for decimating the output signal of the phase quantizer. A plurality of delay stages connected by a ring-shaped main loop and sub-feedback stages connected to the plurality of delay stages to form at least one sub-feedback loop, and each output stage of the plurality of delay stages in response to an input signal. Outputs a plurality of oscillation signals having a phase difference from each other, Each of the plurality of delay stages and sub-feedback stages A differential amplifier for inverting and amplifying the output signal of the previous delay stage; And Controlling a pull-up operation of the differential amplifier in response to the input signal to adjust a delay time for the differential amplifier to invert and amplify the output signal of the previous delay stage; A pull-up control unit which adjusts a frequency gain which is a ratio of frequency change of the plurality of oscillation signals; And A pull-down controlling the pull-down operation of the differential amplifier in response to the input signal to adjust the delay time of inverting and amplifying the output signal of the previous delay stage, and adjusting the frequency gain in response to the bias voltage Including a control unit, The differential amplifier is A first MOS transistor pair having a source terminal connected to a first power supply voltage and receiving an output signal of the previous delay stage through a gate terminal and outputting an output signal of a current delay stage to a drain terminal; And A source terminal is connected to the second power supply voltage, one gate terminal is connected to cross the other drain terminal, and the drain terminal includes a second MOS transistor pair connected to the drain terminal of the first MOS transistor pair. Voltage controlled oscillator. delete The method of claim 10, The pull-up control unit includes a third MOS transistor pair having a source terminal connected to the second power supply voltage, a drain terminal connected to a drain terminal of the first MOS transistor pair, and receiving the input signal through a gate terminal. The pull-down control unit has a source terminal connected to the first power supply voltage, a drain terminal connected to a drain terminal of the first MOS transistor pair, and receiving the input signal through a gate terminal, and the threshold voltage of the third MOS transistor pair And a fourth MOS transistor pair having a threshold voltage of an absolute value greater than the absolute value. The method of claim 12, wherein the sum of the absolute value of the threshold voltage of the third MOS transistor and the absolute value of the threshold voltage of the fourth MOS transistor is equal to a difference between the first power voltage and the second power voltage. Voltage controlled oscillator. The method of claim 12, The bias voltage includes a first bias voltage and a second bias voltage, When the common mode voltage of the first body bias voltage applied to the body of the third MOS transistor pair and the second body bias voltage applied to the body of the fourth MOS transistor pair is increased, the first region of the input voltage is increased. The absolute value of the frequency gain of the decreases and the absolute value of the frequency gain in the second region increases, Increasing the differential mode voltage between the first body bias voltage and the second body bias voltage reduces the absolute value of the frequency gain in the first region and the frequency gain in the second region. oscillator. In response to the analog input signal, inverting and amplifying the output signal of each of the plurality of delay stays connected to the ring-shaped main loop and providing it to the next delay stage; Inverting at least one output signal of the plurality of delay stages and feeding back an input signal of at least one or more previous delay stages to generate a plurality of oscillation signals at each output terminal of the plurality of delay stages; And The first bias voltage and the second bias voltage applied to the plurality of delay stages are adjusted to change the frequency change of the plurality of oscillation signals with respect to the change of the analog input signal in the first region and the second region of the input signal. And adjusting a frequency gain that is a ratio.

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