KR100935250B1 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, by forming a ground metal layer between the bit line and the lower terminal, it is possible to reduce the parasitic capacitance between the bit line and the lower terminal, thereby increasing the operating margin of the device The present invention relates to a semiconductor device capable of improving the reliability of a device by removing noise caused by a voltage change, and a method of manufacturing the same. The semiconductor device of the present invention includes a predetermined gate electrode and a capacitor formed on the semiconductor substrate; A first insulating layer deposited on the semiconductor substrate to embed the gate electrode and the capacitor; A ground metal layer formed in a cell region of an upper portion of the first insulating layer while exposing a portion where a bit line contact is to be formed; A second insulating film deposited over the upper portion of the first insulating film so that the ground metal layer is buried; A metal plug formed by buried in a bit line contact formed over the first insulating film and the second insulating film to expose the semiconductor substrate between the gates; And a bit line formed on an upper portion of the metal plug.

Bitline, parasitic capacitance, ground metal layer, tungsten

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}             

1-6 is a process flowchart which shows an example of the manufacturing method of the semiconductor element by this invention.

****** Description of the main parts ******

100 semiconductor substrate 101 cell region

102: ferry / logic region 103: gate electrode

104: flat plate capacitor 105: first insulating film

106: grounding metal layer 107: second insulating film

108: bit line contact (metal plug) 109: bit line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the parasitic capacitance between the bit line and the lower terminal can be reduced, so that the bit line capacitance Cb can be significantly reduced, thereby increasing the operating margin of the device. In addition, the present invention relates to a semiconductor device and a method of manufacturing the same, which can improve the reliability of the device by removing noise caused by voltage changes.

In semiconductor memory devices, such as DRAM devices, it is important to improve the sensitivity of a sense amplifier that functions to reliably sense and amplify data stored in memory cells. The sensitivity of the sense amplifier is the potential difference ΔV (ΔV = (Vcc / 2) / [1+ (Cb / Cs)] inputted at both ends, wherein Vcc is a supply voltage, Cb is a bit line capacitance, and Cs is a storage capacitance. The larger the value is, the higher the potential difference ΔV should be.

As one of the methods of improving the sensitivity of the sense amplifier, a method of increasing the storage capacitance Cs may be considered. However, the method of increasing the storage capacitance Cs is larger due to the higher integration of DRAM devices. It is true that there was a limit to this reduction.

For this reason, by improving the sensitivity of the sense amplifier, it is required to reduce the bit line capacitance Cb in order to increase the operating margin of the device, but the bit line capacitance is the capacitance between the bit lines, the capacitance between the bit lines and the upper terminals and the bits. Since various capacitances such as capacitance between the line and the lower terminal act in combination, it is also true that the bit line capacitance Cb was not easy due to the complex capacitance.                         

In particular, in a memory device using a gate electrode and a capacitor, such as an MPDL, the capacitor area under the bit line becomes wider, so that the capacitance between the bit line and the lower terminal acts greatly, and thus, between the bit line and the lower terminal. The size of the bit line capacitance Cb depends on the size of the parasitic capacitance. That is, in such a memory device, in order to improve the sensitivity of the sensor amplifier and increase the operating margin of the device by reducing the bit line capacitance (Cb), a technique for reducing the parasitic capacitance between the bit line and the lower terminal is urgently required. However, it is true that a method for reducing such parasitic capacitance has not been proposed in the related art, and accordingly, the ratio of the bit line capacitance Cb and Cb / Cs increases, resulting in the sensitivity of the sensor amplifier and the operating margin of the device. There was a problem of this degrading.

Due to this problem of the prior art, the parasitic capacitance of the bit line and the lower terminal is significantly reduced, thereby reducing the ratio of the bit line capacitance Cb and Cb / Cs, thereby reducing the sensitivity of the sensor amplifier and the operating margin of the device. There is an urgent need for a semiconductor device capable of increasing and a method of manufacturing the same.

The present invention can significantly reduce the parasitic capacitance of the bit line and the lower terminal, to reduce the ratio of the bit line capacitance (Cb) and Cb / Cs, in order to solve the problems of the prior art as described above, It is to provide a semiconductor device and a method of manufacturing the same that can increase the sensitivity of the amplifier and the operating margin of the device.

In order to solve the above object, the present invention is a predetermined gate electrode and a capacitor formed on a semiconductor substrate; A first insulating layer deposited on the semiconductor substrate to embed the gate electrode and the capacitor; A ground metal layer formed in a cell region of an upper portion of the first insulating layer while exposing a portion where a bit line contact is to be formed; A second insulating film deposited over the upper portion of the first insulating film so that the ground metal layer is buried; A metal plug formed by being embedded in a bit line contact formed over the first insulating film and the second insulating film so as to expose the semiconductor substrate between the gate electrodes; And a bit line formed on an upper portion of the metal plug.

In addition, the present invention comprises the steps of depositing a first insulating film on the semiconductor substrate formed with a predetermined capacitor and the gate so that the gate electrode and the capacitor is embedded; Depositing a ground metal layer on the first insulating layer, and patterning the ground metal layer to remain in only a cell region while exposing a bit line contact forming portion; Forming a second insulating layer on the resultant of the patterned ground metal layer so as to embed the ground metal layer; And forming a metal plug and a bit line in the resultant product on which the second insulating film is formed.

In the semiconductor device and a method of manufacturing the same according to the present invention, a ground metal layer is formed on an upper portion of a first insulating layer formed to fill a capacitor and a gate, and thus, a bit line and a lower terminal formed on the second insulating layer. That is, since the ground metal layer is formed between the capacitors, even if the area of the capacitor becomes large, parasitic capacitance between the bit line and the lower terminal can be minimized, thereby increasing the sensitivity of the sensor amplifier and the operating margin of the device. In addition, the reliability of the device can be improved by removing noise caused by voltage changes.

In the semiconductor device and the method of manufacturing the semiconductor device according to the present invention, the ground metal layer may be formed using all metals used for grounding in the manufacturing process of a general semiconductor device, in particular, formed using tungsten It is preferable to. By using such tungsten, it is possible to more effectively reduce the capacitance between the bit line and the lower terminal.

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of a semiconductor device according to the present invention will be described in detail. 6 is a cross-sectional view showing the structure of a semiconductor device finally formed according to the present invention.

Referring to FIG. 6, a semiconductor device according to the present invention includes a predetermined gate electrode 103 and a plate capacitor 104 formed on the semiconductor substrate 100, and the gate electrode 103 and the capacitor 104 are embedded. The ground metal layer formed in the cell region 101 of the upper portion of the first insulating layer 105 while exposing the first insulating layer 105 to be deposited on the semiconductor substrate and the portion where the bit line contact 108 is to be formed. And a second insulating film 107 deposited over the upper portion of the first insulating film 105 so that the ground metal layer 106 is embedded, and the semiconductor substrate between the gate electrode 103 is exposed. And a bit plug 109 formed over the metal plug and a metal plug formed by being embedded in the bit line contact 108 formed over the first insulating film 105 and the second insulating film 107.

In one example of the semiconductor element according to the present invention, first, the gate electrode 103 and the flat plate capacitor 104 are formed on the semiconductor substrate. The gate electrode 103 and the flat plate capacitor 104 are formed by sequentially stacking and patterning a gate insulating film, a gate poly, and the like, similarly to a semiconductor device according to the related art, but the specific structure thereof varies depending on the type of device. Can be. However, the specific configurations of the gate electrode 103 and the flat plate capacitor 104 according to the type of device are extremely obvious to those skilled in the art, and those skilled in the art can easily change the configuration thereof.

In addition, in one example of the semiconductor device according to the present invention, the first insulating film 105 is formed so that the gate electrode 103 and the flat plate capacitor 104 are buried. Such an insulating film also includes an oxide film and a nitride film, which are conventionally used as an insulating film. It can be formed using all, etc., the thickness of the formation can also be determined by those skilled in the art extremely easily depending on the degree of integration of the device and the size of the pattern accordingly.

Meanwhile, a patterned ground metal layer 106 is formed in the cell region 101 to expose a portion where the bit line contact 108 is to be formed in the cell region 101. The cell region 101 is formed on the first insulating layer 105. By forming such a ground metal layer 106 at the bottom, even if the area of the lower capacitor 104 is large, the parasitic capacitance between the lower terminal and the bit line 109 to be formed on the ground metal layer 106 is significantly reduced. As a result, the operating margin of the device can be increased.                     

As described above, the ground metal layer 106 may be formed using all the metals used for grounding in the conventional semiconductor device manufacturing, but in order to effectively remove the parasitic capacitance between the bit line and the lower terminal, It is particularly preferable to form the same using a metal, and in order to minimize the step between the ferry / logic region 102 in which the ground metal layer 106 is not formed and the cell region 101 in which the ground metal layer is formed, The deposition thickness is preferably as thin as possible.

In addition, in an example of the semiconductor device according to the present invention, a second insulating film 107 is deposited on the ground metal layer 106, and the second insulating film 107 is also similar to the first insulating film 105. It is possible to deposit using all the insulating materials known to those skilled in the art in the prior art, the deposition thickness can also be easily determined by those skilled in the art according to the type of device and the size of the pattern.

The bit line contact 108 exposing the semiconductor substrate between the gate electrode 103 is formed over the first insulating film 105 and the second insulating film 107. As described above, the bit line contact portion is formed. In this case, since the ground metal layer 103 is not formed, the bit line contact may be formed in the same manner as in the prior art, and the metal plug 108 may be formed to fill the bit line contact according to a conventional process. Can be.

Finally, in one example of the semiconductor device according to the present invention, a bit line 109 is formed on the metal plug, and the bit line may also be formed using a conventional material used in a general semiconductor device. Can be.                     

That is, as described above, the semiconductor device of the present invention is characterized in that the ground metal layer 106 is formed on the first insulating film 105, the area of the lower capacitor 104 by the ground metal layer. Even if this becomes wider, the capacitance between the lower terminal and the bit line 109 can be minimized, thereby reducing the bit line capacitance Cb, thereby increasing the operating margin of the device and the sensitivity of the sense amplifier. .

Hereinafter, with reference to the accompanying drawings, a preferred example of the method for manufacturing a semiconductor device according to the present invention will be described in detail. 1-6 is a process flowchart which shows an example of the manufacturing method of the semiconductor element by this invention.

In the method for manufacturing a semiconductor device according to the present invention, first, as shown in FIG. 1, the gate is formed on a semiconductor substrate 100 on which a predetermined substructure such as the gate electrode 103 and the flat plate capacitor 104 are formed. The first insulating layer 105 is deposited to bury the electrode and the capacitor, and planarization is performed through a chemical mechanical polishing (CMP) process.

Then, as can be seen in FIG. 2, a ground metal layer 106 is deposited on the first insulating film 105 using tungsten. At this time, the thickness of the tungsten (W) used as the ground metal layer 106 is formed as thin as possible, so that the ferry / logic region 102 from which the tungsten (W) will be removed later, and the cell region 101 where the tungsten will remain Minimize the step with).

On the other hand, after the ground metal layer 106 is deposited, as shown in FIGS. 3A and 3B, the ground metal layer 106 is removed from the ferry / logic region 102, and only the cell region 101 is grounded. The metal layer 106 remains, and in the portion of the cell region 101 where the bit line contact 108 is to be formed in a later process, the ground metal layer is exposed so that the first insulating layer 105 under the ground metal layer 106 is exposed. Pattern.

The patterning process may be performed by performing a photo-etching process using a photoresist film (not shown) according to a general pattern formation method used in a semiconductor device, and by patterning in this manner, as shown in FIG. 3B, a cell The metal ground layer 106 may be obtained in which only the metal of the portion of the region where the bit line contact 108 is to be formed is removed.

Meanwhile, after the patterning process is performed, as shown in FIG. 4, the second insulating film 107 is deposited on the first insulating film 105 so that the ground metal layer 106 is buried, and planarized. do. Like the first insulating film, the second insulating film 107 may be deposited using all conventional insulating materials. In particular, the second insulating film 107 may be deposited using the same material as the first insulating film to simplify and manufacture the manufacturing process. It is advantageous in terms of reduction in unit cost.

Subsequently, as shown in FIG. 5, a region in which the bit line contact 108 is to be formed is defined through a photolithography process using a photoresist film (not shown), and according to the photoresist pattern, a lower second insulating film By etching away the 107 and the first insulating film 105, a bit line contact 108 exposing the semiconductor substrate 100 between the gate electrode 103 is formed, and a metal is deposited so that the bit line contact is buried. Thus, the metal plug 108 is formed.

Then, finally forming the bit line 109 on the top of the resultant metal plug 108, as can be seen in Figure 6, the final semiconductor device of the present invention can be manufactured.

According to the method of manufacturing a semiconductor device according to the present invention, a semiconductor device having a ground metal layer 106 formed between the capacitor 104 and the bit line 109 can be manufactured, and by forming such a semiconductor device, The parasitic capacitance between the bit line and the lower terminal and thus the bit line capacitance Cb may be minimized, thereby manufacturing a semiconductor device having improved operating margin and reliability.

According to the semiconductor device of the present invention and a method of manufacturing the same, the parasitic capacitance of the bit line and the lower terminal can be significantly reduced, thereby reducing the ratio of the bit line capacitance Cb and Cb / Cs. The sensitivity and the operating margin of the device can be increased, and noise due to voltage change can also be removed, thereby significantly improving the reliability of the device.

Claims (4)

A predetermined gate electrode and a capacitor formed on the semiconductor substrate; A first insulating layer deposited on the semiconductor substrate to embed the gate electrode and the capacitor; A ground metal layer formed in a cell region of an upper portion of the first insulating layer while exposing a portion where a bit line contact is to be formed; A second insulating film deposited over the upper portion of the first insulating film so that the ground metal layer is buried; A metal plug formed by being embedded in a bit line contact formed over a first insulating film and a second insulating film to expose the semiconductor substrate between the gates; And And a bit line formed on the metal plug. The semiconductor device of claim 1, wherein the ground metal layer is formed of tungsten. Depositing a first insulating film on the semiconductor substrate on which a predetermined capacitor and a gate are formed so that the gate and the capacitor are embedded; Depositing a ground metal layer on the first insulating layer, and patterning the ground metal layer to remain in only a cell region while exposing a bit line contact forming portion; Forming a second insulating layer on the resultant of the patterned ground metal layer so as to embed the ground metal layer; And And forming a metal plug and a bit line in the resultant product on which the second insulating film is formed. The method of claim 3, wherein the ground metal layer is formed of tungsten.

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