KR100930413B1 - Light driver control circuit, semiconductor integrated circuit comprising same and method for generating light driver control signal - Google Patents

Abstract

The write driver control circuit of the present invention includes a pulse width combination unit for combining a write driver control signal and a clock signal to output a reference signal having the same pulse width as the clock signal; And a pulse width adjusting unit for generating a reset signal by varying a pulse width of the reference signal.

Description

Write driver control circuit, semiconductor integrated circuit and light driver control signal generation method including the same {Write Driver Control Circuit, Semiconductor Integrated Circuit Including The Same And Generating Method of WDC Signal}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a light driver control circuit, a semiconductor integrated circuit including the same, and a method of generating a light driver control signal.

1 is a circuit diagram of a general write driver.

The write driver illustrated in FIG. 1 includes first to tenth inverters IV1 to IV10 and first to thirteenth transistors M1 to M13.

The write driver latches the data DATA and DATA_B according to the write driver strobe signal WDS and the reset signal RST to transmit the data output signals DATA_OUT and DATA_OUTB or to free the data output signals DATA_OUT and DATA_OUTB. Charge.

When the reset signal RST is at a low level and the write driver strobe signal WDS is at a low level, the data output signals DATA_OUT and DATA_OUTB are precharged. When the reset signal RST is at a high level and the write driver strobe signal WDS is at a high level, the data DATA and DATA_B are transmitted as the data output signals DATA_OUT and DATA_OUTB.

2 is a circuit diagram of a light driver control circuit according to the prior art.

The write driver control circuit shown in FIG. 2 includes a plurality of inverters IV1 to IV7, first to fifth delay units 1 to 5, and first and second NAND gates ND1 and ND2.

The write driver enable signal WDE is generated by a combination of a low address strobe (RAS), a column address strobe (CAS), and a write enable (WE). The write driver strobe signal WDS is generated to have a pulse width of a narrow high level section compared to the write driver enable signal WDE through the circuit of FIG. 2. The reset signal RST is generated to have a pulse width of a wider high level section than the write driver enable signal WDE through the circuit of FIG. 2.

3 is a timing diagram of input / output signals of the write driver control circuit of FIG. 2.

The write driver enable signal WDE is synchronized with the clock signal CLK but is generated by a combination of the RAS, the CAS, and the WE, and thus the pulse width thereof may be different from the clock signal CLK. The write driver strobe signal WDS is generated to have a higher pulse width narrower than that of the write driver enable signal WDE. In addition, the reset pulse RST is generated to have a higher level pulse width than the write driver enable signal WDE.

4 is a timing diagram of input and output signals of the write driver control circuit shown in FIG. 2 when a high frequency clock signal is input.

Since the pulse width of the write driver enable signal WDE is independent of the clock signal CLK, even if the frequency of the clock signal CLK is increased, the pulse width of the high section of the write driver enable signal WDE may be increased. It is constant. However, the write driver enable signal WDE is a signal having a high level section once during one period of the clock signal CLK. Therefore, when the clock frequency is increased, the high period of the write driver enable signal WDE is constant while the width of the low period is reduced. In addition, like the write driver enable signal WDE, the write driver strobe signal WDS and the reset signal RST have a pulse width of a high interval at a constant interval even when the clock frequency is increased, The pulse width is reduced.

That is, when the clock frequency is increased, the pulse width of the low period of the write driver strobe signal WDS and the reset signal RST is decreased, and the pulse width of the write driver strobe signal WDS should be wider than that of the write driver strobe signal WDS. The pulse width of the low section of the reset signal RST becomes too narrow, which causes a problem of no margin. In this case, the write driver has a problem in that the time for precharging the data output signals DATA_OUT and DATA_OUTB is insufficient, resulting in poor data transmission characteristics.

Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a light driver control circuit for securing a margin of a write driver control signal and reducing data defects, a semiconductor integrated circuit including the same, and a method for generating a write driver control signal. have.

According to another aspect of the present invention, a write driver control circuit includes a pulse width combination unit configured to combine a write driver control signal and a clock signal to output a reference signal having the same pulse width as the clock signal; And a pulse width adjusting unit configured to generate a reset signal by varying a pulse width of the reference signal.

In addition, the semiconductor integrated circuit including the write driver control circuit according to the present invention includes a pulse width combination unit for outputting a reference signal having the same pulse width as the clock signal by combining the write driver control signal and the clock signal; A pulse width adjusting unit generating a reset signal by varying a pulse width; And a write driver for driving data according to the write driver strobe signal to output a data output signal, and precharging the data output signal according to the reset signal.

The method of generating a write driver control signal of the present invention includes: combining a write driver control signal and a clock signal to generate a reference signal having the same pulse width as the clock signal; Generating a reset signal by varying a pulse width of the reference signal.

The write driver control circuit, the semiconductor integrated circuit including the same, and the method of generating the write driver control signal according to the present invention reduce the failure of data transmission to the data line by securing the margin of the write driver control signal regardless of the frequency of the clock signal. You can.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

5 is a block diagram of a semiconductor integrated circuit including a write driver control circuit 40 according to the present invention.

The semiconductor integrated circuit shown in FIG. 5 includes a write driver control circuit 40 and a write driver 50.

The write driver control circuit 40 includes a pulse width combination unit 10, a pulse width adjustment unit 30, and a margin adjustment unit 20.

The pulse width combiner 10 generates a reference signal syncs having the same pulse width as the clock signal CLK by combining the write driver enable signal WDE and the clock signal CLK.

The pulse width adjusting unit 30 generates a reset signal RST by increasing the pulse width of the logic high of the reference signal syncs.

When the write lead bar signal WRB is activated, the margin adjusting unit 20 delays the reference signal syncs more than the reset signal RST and outputs the write driver strobe signal WDS. The write lead bar signal WRB is a high level signal during a write operation and a low level signal during a read operation.

The write driver 50 drives data DATA and DATA_B according to the write driver strobe signal WDS to output data output signals DATA_OUT and DATA_OUTB, and outputs the data output signal according to the reset signal RST. Precharge (DATA_OUT, DATA_OUTB). The write driver 50 may be implemented as shown in FIG. 1.

FIG. 6 is a circuit diagram of the light driver control circuit 40 shown in FIG.

The pulse width combiner 10 includes a first inverter IV1, a first delay unit 11, a ninth inverter IV9, a second delay unit 12, and a first logic operation unit 13.

The first inverter IV1 receives the write driver enable signal WDE.

The first delay unit 11 delays the output of the first inverter IV1 by a predetermined time.

The ninth inverter IV9 receives the output of the first delay unit 11.

The second delay unit 12 delays the clock signal CLK for a predetermined time.

The first delay unit 11 and the second delay unit 12 may be implemented as a general delay circuit. The delay time of the first delay unit 11 and the second delay unit 12 is set for timing adjustment when the write driver enable signal WDE and the clock signal CLK are combined.

The first logic calculator 13 performs an AND operation on the output of the ninth inverter IV9 and the output of the second delay unit 12. The first logic calculator 13 includes a first NAND gate ND1 and a second inverter IV2. The first NAND gate ND1 receives an output of the ninth inverter IV9 and an output of the second delay unit 12. The second inverter IV2 receives the output of the first NAND gate ND1.

The margin adjusting unit 20 includes a third delay unit 21 and a second logic operation unit 22.

The third delay unit 21 delays the reference signal syncs for a predetermined time. The delay time of the data strobe signal WDS is determined relative to the reset signal RST according to the delay value of the third delay unit 21.

The second logic calculator 22 receives the output of the write lead bar signal WRB and the third delay unit 21 and performs an AND operation to output the write driver strobe signal WDS. The second logic calculator 22 includes a second NAND gate ND2 and a third inverter IV3. The second NAND gate ND2 receives the output of the write lead bar signal WRB and the third delay unit 21. The third inverter IV3 receives the output of the second NAND gate ND2 and outputs the write driver strobe signal WDS.

The pulse width adjusting unit 30 includes a fourth inverter IV4, a fourth delay unit 31, and a third logic operation unit 32.

The fourth inverter IV4 receives the reference signals syncs.

The fourth delay unit 31 delays the reference signal syncs for a predetermined time. The fourth delay unit 31 may be implemented by a plurality of inverters. For example, the fourth delay unit 31 may be implemented as two inverters connected in series.

The third logic calculator 32 NAND-operates and delays the output of the fourth inverter IV4 and the output of the fourth delay unit 31 to generate the reset signal RST. The third logic operation unit 32 includes a fourth NAND gate ND4, a seventh inverter IV7, and an eighth inverter IV8. The fourth NAND gate ND4 receives an output of the fourth inverter IV4 and an output of the fourth delay unit 31. The seventh inverter IV7 receives the output of the fourth NAND gate ND4. The eighth inverter IV8 receives the output of the seventh inverter IV7 and outputs the reset signal RST.

The pulse width adjusting unit 30 may adjust the pulse width of the reset signal RST according to the delay time of the fourth delay unit 31.

7 is a timing diagram of signals for controlling a write driver when a high frequency clock signal is input according to the present invention.

Since the clock frequency is a high frequency, the pulse width of the high section of the clock signal CLK is small, and the pulse width of the write driver enable signal WDE is constant, so that the write driver has a higher frequency than the clock signal CLK. The pulse width of the low section of the enable signal WDE is relatively reduced. The reference signal syncs has the same pulse width as the clock signal CLK. In addition, since the write driver strobe signal WDS becomes a signal obtained by delaying the reference signal syncs for a predetermined time, a margin of a low period is secured regardless of the clock frequency. The reset signal RST has a wider pulse width than the reference signal syncs. However, since the reference signal syncs is basically the same as the pulse width of the clock signal CLK, the reset signal RST width is wider than the pulse width of the clock signal CLK, but a margin of pulse width in the low section is provided. Can be secured.

An operation of the light driver control circuit according to the present invention will be described with reference to FIGS. 5 to 7 as follows.

The first logic calculator 13 of the pulse width combiner 10 of FIG. 6 outputs a signal in which the clock signal CLK and the write driver enable signal WDE are combined. The pulse width of the high level of the write driver enable signal WDE is greater than that of the clock signal CLK, and the write driver enable signal WDE is a signal input in synchronization with the clock signal CLK. The reference signal syncs has the same pulse width as the clock signal CLK. The third delay unit 21 delays the reference signal syncs and delays the reference signal syncs in the period where the write lead bar signal WRB is at a high level so that the write driver strobe signal WDS is delayed. Will output

In addition, the pulse width adjusting unit 30 generates a reset signal RST in which a high level section is extended by a delay time of the fourth delay unit 31 compared to a high level pulse width of the reference signal syncs. do. Therefore, when the frequency of the clock signal CLK increases, the reset signal RST increases the pulse width of the high level relative to the clock signal CLK by the delay time of the fourth delay unit 31. A certain margin can be secured. Accordingly, it can be seen that the reset signal RST shown in FIG. 7 has a margin of a pulse width in a low section compared to FIG. 4. Therefore, the write driver 50 operates normally by precharging the data output signals DATA_OUT and DATA_OUTB according to the write driver strobe signal WDS and the reset signal RST having a sufficiently low pulse width margin. Can be performed and the badness of the data transmission characteristics can be reduced.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof.

Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a circuit diagram of a general light driver,

2 is a circuit diagram of a light driver control circuit according to the prior art;

3 is a timing diagram of input and output signals of the write driver control circuit shown in FIG. 2;

4 is a timing diagram of input and output signals of the write driver control circuit shown in FIG. 2 when a high frequency clock signal is input;

5 is a block diagram of a semiconductor integrated circuit including a write driver control circuit according to the present invention;

FIG. 6 is a circuit diagram of the light driver control circuit shown in FIG. 5; and

7 is a timing diagram of signals for controlling a write driver when a high frequency clock signal is input according to the present invention.

<Description of the symbols for the main parts of the drawings>

1 to 6: first to sixth delay units

10: pulse width combination unit 20: margin adjustment unit

30: pulse width adjusting unit 40: light driver control circuit

50: light driver 11: first delay unit

12: second delay unit 13: first logic operation unit

21: third delay unit 22: second logic operation unit

31: fourth delay unit 32: third logic operation unit

Claims (19)

A pulse width combination unit for combining a write driver enable signal and a clock signal to output a reference signal having the same pulse width as the clock signal; And And a pulse width adjusting unit configured to generate a reset signal by varying a pulse width of the reference signal. The method of claim 1, And a margin adjusting unit configured to output a write driver strobe signal by delaying the reference signal by a predetermined time compared to the reset signal. The method of claim 1, The pulse width combination unit, And a write driver control circuit configured to logically multiply the write driver enable signal by the clock signal to generate the reference signal. The method of claim 3, wherein The pulse width combination unit, And a first delay signal for delaying the write driver enable signal by a first delay time and a second delay signal for delaying the clock signal by a second delay time to generate the reference signal. The method of claim 2, The margin adjustment unit, And outputting the write driver strobe signal by delaying the reference signal by a set time compared to the reset signal according to the write lead bar signal. The method of claim 5, wherein The margin adjustment unit, A delay unit for delaying the reference signal by a predetermined time; And And a logic operation unit configured to receive the output of the write lead bar signal and the output of the delay unit and perform an AND operation to output the write driver strobe signal. The method of claim 1, The pulse width adjustment unit, And increasing the pulse width of the high period of the reference signal to generate the reset signal. The method of claim 7, wherein The pulse width adjustment unit, An inverting element receiving the reference signal; A delay unit for delaying an output of the inverting element by a predetermined time; And And a logic calculator configured to NAND-operate and delay the output of the inverting element and the output of the delay unit to output the reset signal. A pulse width combination unit for combining a write driver enable signal and a clock signal to output a reference signal having the same pulse width as the clock signal; A pulse width adjusting unit configured to generate a reset signal by varying a pulse width of the reference signal; And And a write driver for driving data according to the write driver strobe signal to output a data output signal and precharging the data output signal according to the reset signal. The method of claim 9, The pulse width combination unit, And logically multiply the write driver enable signal by the clock signal to generate the reference signal. The method of claim 9, The pulse width combination unit, And generate the reference signal by performing an AND operation on the first delay signal delaying the write driver enable signal by a first delay time and the second delay signal delaying the clock signal by a second delay time. The method of claim 9, And a margin adjuster configured to output a write driver strobe signal by delaying the reference signal by a predetermined time compared to the reset signal. The method of claim 12, The margin adjustment unit, And output the write driver strobe signal by delaying the reference signal by a set time relative to the reset signal according to a write lead bar signal. The method of claim 13, The margin adjustment unit, A delay unit for delaying the reference signal by a predetermined time; And And a logic operation unit configured to receive the output of the write lead bar signal and the delay unit and perform an AND operation to output the write driver strobe signal. The method of claim 9, The pulse width adjustment unit, And generate the reset signal by increasing a pulse width of a high section of the reference signal. The method of claim 15, The pulse width adjustment unit, An inverting element receiving the reference signal; A delay unit for delaying an output of the inverting element by a predetermined time; And And a logic calculator configured to NAND-operate and delay the output of the inverting element and the output of the delay unit to output the reset signal. Combining a write driver enable signal and a clock signal to generate a reference signal having the same pulse width as the clock signal; And And generating a reset signal by varying a pulse width of the reference signal. The method of claim 17, And generating a write driver strobe signal by delaying the reference signal by a predetermined time. The method of claim 17, Generating the reference signal, And a logical sum operation of the write driver enable signal and the clock signal.

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