KR100928515B1 - Data receiver - Google Patents

Abstract

A data receiving apparatus is disclosed. The device receives a transmission signal in which a strobe signal is inserted in a different size from the data signal between the data signals, and a clock signal having the same magnitude as the data signal is inserted subsequent to the strobe signal and cancels the differential component of the received transmission signal. A strobe signal extractor for extracting a strobe signal corresponding to a result compared with the first and second offset levels, a clock recoverer for recovering a clock signal from a received transmission signal using the extracted strobe signal, and a restored clock signal In response to, having a sampler for sampling a data signal included in the received transmission signal, the sampler being compared at a third level comparator and a third level comparator to compare the differential components of the transmission signal and output the compared result. And a first D flip-flop for outputting the result in response to the recovered clock signal. Therefore, it is possible to minimize the possibility of error in time intervals, to accurately recover the clock signal even if the level of the common component fluctuates, and to reduce the area of the circuit for recovering the clock signal, Not only is it suitable for transmitting / receiving data, it is not only resistant to noise generated during the transmission process or path of data signal and clock signal, but also it can carry data of arbitrary data signal on strobe signal and transmit it, thereby improving data transmission efficiency. Has the effect.

Data receiving, clock signal, data signal, strobe signal, display

Description

Data receiving apparatus

The present invention relates to a timing controller for a chip on glass (COG), a chip on film (COF) or a tape carrier package (TCP) and a source driver. The present invention relates to a new data interface method applicable to the present invention, and more particularly, to a data receiving apparatus.

As the resolution of displays such as televisions and monitors has gradually increased, more data has to be transmitted. Therefore, when transmitting data at a high transmission rate, electromagnetic interference (EMI) or high frequency interference (RFI) is most likely to be transmitted in the wiring for transmitting the data signal between the timing control unit and the column driver integrated circuit source driver. It happens a lot. In order to reduce the emission of such interference, small signal differential transmission schemes such as reduced swing differential signaling (RSDS) or low voltage differential signaling (mini-LVDS) are widely used.

As the data transfer rate increases, the RSDS method and the mini-LVDS method described above may signal by impedance mismatch or the like at the point where the line branches to the source drive because multiple source drivers share data and clock lines. Problems such as deterioration of quality are caused. Therefore, in recent years, a point-to-point differential signaling (PPDS) method for connecting a timing controller and a source driver in a 1: 1 manner has been proposed, and a corresponding method has been developed in Korea.

In the PPDS scheme, the data is connected 1: 1 by the timing controller and the source driver, but the clock signal has a structure shared by several source drivers as before. Accordingly, in the PPDS scheme, when the data is transmitted at high speed, a timing skew error increases between the clock signal and the data signal. This makes it difficult to speed up the transmission.

On the other hand, the above-described method developed in Korea transmits the clock signal and the data or control signal in series through one transmission path. Therefore, the clock signal and the data signal are transmitted with the same delay time. Therefore, there is an advantage that can further reduce the skew error between the clock signal and the data signal generated during the transmission process. However, this approach still has its limitations. That is, in order to detect a clock signal from the signal received at the source driver, the received signal is compared with each level of the reference signal. When the level of the common component of the clock signal and the data signal received at the source driver varies, There is a problem that the clock signal cannot be detected properly.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a data receiving apparatus capable of efficiently extracting a strobe signal, restoring a clock signal, and sampling data from a transmission signal in which a strobe signal is inserted between a clock signal and a data signal. .

In the data receiving apparatus according to the present invention for achieving the above object, a strobe signal is inserted between the data signal in a different size from the data signal, and a clock signal having the same size as the data signal is inserted subsequent to the strobe signal A strobe signal extractor configured to receive the signal and extract the strobe signal corresponding to a result of comparing the differential component of the received transmission signal with first and second offset levels, and using the extracted strobe signal And a sampler configured to sample the data signal included in the received transmission signal in response to the recovered clock signal, in response to the restored clock signal, and a sampler configured to recover the clock signal from the received transmission signal. A third level comparator and a third level comparator for comparing the differential components and outputting the compared result In response to the result compared by the level comparator in the recovered clock signal having a second 1 D flip-flop outputs are preferred.

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The data receiving apparatus according to the present invention transmits the clock signal and the data signal through the same path in the same size, so that the clock signal and the data signal can be processed in the same way during the transmission and recovery process. It is possible to minimize the possibility of timing skew error, to accurately recover the clock signal even if the level of the common component fluctuates, and to reduce the area of the circuit for recovering the clock signal. It is not only suitable for transmitting / receiving data at high transmission speed, but also robust to noise generated in the process or path of data signal and clock signal, and can transmit data of arbitrary data signal on strobe signal to transmit data. It has an effect to increase.

Hereinafter, the configuration and operation of each embodiment of a data transmission device and a data reception device according to the present invention will be described as follows with reference to the accompanying drawings.

1 is a block diagram of a data transmitting apparatus and a data receiving apparatus according to an embodiment of the present invention.

The data transmitter 100 shown in FIG. 1 includes a clock signal generator 110 and a transmitter 120, and the data receiver 200 includes a strobe signal extractor 210, a clock recoverer 220, It consists of a sampler 230.

The clock signal generator 110 shown in FIG. 1 generates a clock signal and outputs the generated clock signal to the transmitter 120. The transmitter 120 generates a transmission signal using the clock signal input from the clock signal generator 110 and the data input through the input terminal IN1, and transmits the generated transmission signal through the channel 260 to a data receiving apparatus ( 200). According to the present invention, the transmitter 120 inserts a strobe signal (hereinafter referred to as 'STB') with a different size (or level) than the data signal between the data signals, and a clock signal having the same size as the data signal is inserted. Generate a transmit signal to be inserted subsequent to the strobe signal. In this case, a plurality of clock signals may be inserted between the strobe signals.

Hereinafter, the strobe signal STB defined in the present invention is used to indicate the start and end of sequentially inputted information. The strobe signal STB is a signal having information indicating that one data set ends and a new data set starts. . Therefore, the strobe signal STB does not include information to be transmitted and is distinguished from the clock signal and the data signal in that the strobe signal STB is not information having a time to read data, such as a clock signal. In general, the strobe signal STB is an element included in a transmission protocol that operates a physical transmission means consisting of a transmitter, a receiver, and a channel in a data transmission system.

For better understanding of the present invention, assuming that the transmitter 120 transmits a transmission signal by converting it into a differential signal, embodiments of the present invention will be described below with reference to the accompanying drawings. However, the present invention can be applied to a case where the transmission signal is a non-differential signal and not a differential signal, without being limited thereto.

2 to 4 show exemplary waveform diagrams of a transmission signal generated at the transmitter 120 according to embodiments of the present invention. Here, the data D _{n -1} is the last data of the M th data set (hereinafter, referred to as a packet), and the data D ₀ corresponds to the first data of the M + 1 th packet. do.

As shown in Figure 2 to 4, the transmission section 120 is inserted into the strobe signal (STB) as a data signal (D _X) with different sizes in front of the data signals (D _o) which the M + 1 th packet starts and , a data signal (D _X) and the same size as the clock signal (CLK) of the inserts subsequent to the strobe signal (STB), and outputs the result as a transmission signal. Here, x means a positive integer including 0. Various embodiments are possible depending on the position at which the clock signal CLK is inserted after the strobe signal STB.

According to an embodiment of the present invention, as shown in FIG. 2, the transmitter 120 inserts the clock signal CLK immediately after the strobe signal STB, and follows the clock signal CLK in a subsequent manner. D ₀ to D ₂ ) are inserted to generate a transmission signal.

According to another exemplary embodiment of the present disclosure, the transmitter 120 may generate a transmission signal by inserting the clock signal CLK at a predetermined spaced distance based on the strobe signal STB. For example, as shown in FIG. 3, two data signals D ₀ from the strobe signal STB. And the clock signal CLK may be inserted by being spaced apart by D ₁ ).

According to another embodiment of the present disclosure, the transmitter 120 may insert a plurality of dummy signals between the strobe signals STBs. For example, the transmitter 120 may insert a dummy signal into at least one of a front end and a rear end of the strobe signal STB. That is, as shown in FIG. 4, the transmitter 120 inserts the dummy signal DC1 at the front end of the strobe signal STB and inserts the dummy signal DC2 at the rear end of the strobe signal STB to transmit the signal. Can be generated. The reason for inserting the dummy signal is as follows.

When transmitting data at high speed, the strobe signal STB may affect the immediately adjacent signal. Therefore, when the dummy signals DC1 and DC2 are inserted before and after the strobe signal STB as shown in FIG. 4, the clock and data signals immediately adjacent to the strobe signal STB as shown in FIG. 2 are shown. It can reduce the impact on your computer. It also helps to generate the strobe signal STB. In addition, when a plurality of dummy signals are inserted, the clock signal may be conveniently and accurately restored by the data receiving apparatus 200.

2 to 4, the transmitter 120 may set a larger size of the strobe signal STB than the clock signal CLK or the data signal D _x . It is also possible to set the size of the strobe signal STB smaller than the CLK or the data signal D _x . For example, the size of the strobe signal (STB) (SPH and SPL) data signals (D _x) and the clock signal (CLK) the size of three times the size if larger set to (HR and LR), the data receiving device (200 ) Makes it easier to detect the strobe signal STB.

Meanwhile, differential components of the strobe signal STB, which are differential signals, are transmitted from the data transmitting apparatus 100 to the data receiving apparatus 200 through two lines of the channel 260, and the differential components have various values as follows. Can have In general, a differential signal has differential components, where the higher component of the differential components is defined as a 'positive level' and the lower component is defined as a 'negative level'. In differential signal transmission, one of the two lines used as the channel sends a positive level and the other sends a negative level. In general, when the data to be sent is at a high level, a line that sends a positive level is called a P-channel, and another line that sends a negative level is called an N-channel. However, when the data to be sent is at the low level, the line sending the positive level is called N-channel, and the other line sending the negative level is named P-channel.

According to an embodiment of the present invention, as shown in FIG. 2 or 3, the strobe signal STB may be a symmetric differential signal. Here, the symmetrical differential signal means a differential signal having differential components that are symmetric to each other. That is, when the positive level SPH of the strobe signal STB is transmitted on the P-channel, the negative level SPL is transmitted on the N-channel. Alternatively, when the negative level SPL of the strobe signal STB is transmitted on the P-channel, the positive level SPH of the STB is transmitted on the N-channel. As shown in FIG. 2 or FIG. 3, transmitting the positive level SPH and the negative level SPL together may obtain the effect of reducing the generation of electromagnetic waves.

According to another embodiment of the present invention, as shown in FIG. 4, the strobe signal STB may be an asymmetric differential signal. Here, the asymmetric differential signal refers to a differential signal having differential components that are asymmetric with each other based on a common component. That is, when the positive level of the strobe signal STB is transmitted at the high level SPH, the negative level of the strobe signal STB is lower than or equal to the low value CDL of the data level of the data signal D _x . (CDL) may be sent. Alternatively, when the negative level of the strobe signal STB is transmitted at a low level SPL, the positive level of the strobe signal STB is at a level CDH that is higher than or equal to the high value CDH of the data level of the data signal. Can be sent. As described above, since the ratio of the strobe signal STB in the time domain is very low, the differential components of the strobe signal STB may have non-symmetrical values.

According to the present invention, the pulse widths of the data signal D _x and the clock signal CLK may be the same, and the strobe signal STB may be inserted with a pulse width that is an integer multiple of the pulse width of the data signal D _x . It may be. 2 or 3, the pulse width of the strobe signal STB and the pulse width of the data signal D _x (or clock signal CLK) are the same. However, in the case of FIG. 4, the pulse width of the strobe signal STB is approximately twice the pulse width of the data signal D _x . In the case of the present invention, the pulse width occupied by the strobe signal STB has no information. Therefore, it is desirable to reduce as much as possible the width occupied by the strobe signal STB in a range in which the strobe signal STB serves only as a reference for recovering the clock signal CLK and the data signal as part of the transmission protocol. That is, the rising time, falling time, rising slope, and falling slope of the strobe signal STB are not factors influencing the operation.

As described above, the positive level of the strobe signal STB is transmitted to the P-channel and the negative level is transmitted to the N-channel, or the negative level of the strobe signal STB is transmitted to the P-channel and the positive level is N-. Can be transmitted in a channel. In general, when the positive level is transmitted on the P-channel and the negative level is transmitted on the N-channel, the polarity of the signal is defined as positive (+), on the contrary, the negative level is transmitted on the P-channel, and the positive level is transmitted on the N-channel. Define the polarity of the signal as negative when transmitted. In addition, the two polarities are recognized as information corresponding to the binary numbers '0' and '1', respectively. According to the present invention, the polarity of the strobe signal STB can be used as information. For example, the polarity of the strobe signal STB may be used as data information of a specific promised data signal Dx predetermined by the transmission protocol. If the promised data signal Dx is the last data signal Dn-1 of a packet, if the value of the signal Dn-1 is '1', the positive level of the strobe signal STB is P. If the value of (Dn-1) is '0', the positive level of the strobe signal is transmitted through the N-channel. Therefore, since the last data Dn-1 does not need to be transmitted separately, the transmission efficiency is further improved. As described above, when data information of an arbitrary data signal is transmitted on the strobe signal STB, data can be transmitted on all bits of the transmission packet except for a clock signal, thereby increasing transmission efficiency. The transmission efficiency is a value obtained by dividing the number of bits having valid information excluding bits necessary for information transfer, for example, a clock signal or a parity, etc. by the total number of transmission bits.

On the other hand, the configuration and operation of the data receiving apparatus 200 are as follows.

The strobe signal extracting unit 210 receives the transmission signal transmitted from the data transmission apparatus 100, extracts the strobe signal STB from the received transmission signal, and extracts the extracted strobe signal STB from the clock recovery unit 220. )

As described above, because the strobe signal (STB) is greater than the size of the data signals (D _x) and the clock signal (CLK), it is possible to extract a strobe signal (STB) to the transmission signal check the size. In particular, the difference between the differential components of the transmission signal may be examined to extract the strobe signal STB. This will be described later in detail with reference to FIGS. 8 to 10 when the display, which is an application example of the data transmitting apparatus and the data receiving apparatus, will be described.

The clock recovery unit 220 restores the clock signal CLK using the strobe signal STB extracted by the strobe signal extraction unit 210, and receives the restored clock signal RCLK from the sampler 230 and the data. Output to the outside of the device 200. For example, using the extracted strobe signal STB, the clock recovery unit 220 extracts a clock signal CLK positioned subsequent to the strobe signal STB. Referring to FIG. 2, the first crossing point a is determined as the rising edge of the recovery clock signal CLK from the trailing end of the strobe signal STB, and the next crossing point b is determined as the falling edge of the recovery clock signal CLK. do. Referring to FIG. 3, the intersection c located at the third starting point of the clock signal or the data signal from the trailing end of the strobe signal STB is determined as the rising edge of the recovery clock signal, and then the intersection point d is the recovery clock signal. Determine as the falling edge of. Referring to FIG. 4, the first crossing point e is determined as the rising edge of the recovery clock signal from the rear of the dummy signal DC2 subsequent to the strobe signal STB, and the next crossing point f is the falling edge of the recovery clock signal. Decide as

As such, after generating a recovery clock signal at a high logic level between the determined rising edge (a, c or e) and the falling edge (b, d or f), the clock recovery unit 220 generates the next strobe signal STB. This occurs by keeping the recovery clock signal at a low logic level until is detected. Subsequently, when the next strobe signal STB is detected, the above-described operation is repeated to detect the rising edge and falling edge of the recovery clock signal again.

In order to obtain two crossing points for recovering the clock signal, the transmitter 120 may insert the clock signal CLK to have a polarity opposite to the data signal D _x subsequent to the clock signal CLK. That is, the clock signal CLK shown in FIG. 2 or 4 has a low level CDL, but the data signal D ₀ subsequent to the clock signal CLK has a high level CLH. Have That is, when the clock signal CLK and the data signal D _O have opposite polarities, other edges may be generated in addition to the first edge obtained from the intersection point between the strobe signal STB and the clock signal CLK. . In addition, the clock signal CLK shown in FIG. 3 has a low level CDL, but the data signal D ₂ subsequent to the clock signal CLK has a high level CLH. That is, the clock signal CLK and the data signal D ₂ have opposite polarities. However, the present invention is not limited thereto. That is, a delay locked loop (DLL) or a phase locked loop (PLL) may be formed using only one intersection point a, b, c, d, e or f as described below with reference to FIG. 8. In the case of restoring the clock signal by using the polarity, the polarity of the clock signal CLK and the subsequent data signal need not be considered.

The sampler 230 samples the data signal included in the transmission signal in response to the restored clock signal RCLK and outputs the same through the output terminal OUT. That is, the sampler 230 compares the two differential components of the transmission signal shown in FIG. 2 and sets the data information D ₀ , D ₁ , D ₂ of the data signal to '1', '0' and '1', respectively. And the determined data is output in response to the recovered clock signal RCLK. In the data receiving apparatus 200 shown in FIG. 1, the result of comparing the differential components of the transmission signal in the sampler 230 is output to the clock recovery unit 220, and the clock recovery unit 220 is provided from the sampler 230. The clock signal is restored in response to the input comparison result. However, the present invention is not limited thereto, and unlike FIG. 1, the transmission signal may be directly applied to the clock recovery unit 220 without passing through the sampler 230. In this case, the clock recovery unit 220 performs a comparison operation of the sampler 230.

Since the process of reading data from the data receiving apparatus 200 using the recovered clock signal RCLK is common, a description thereof will be omitted.

As described above, the strobe signal STB may have a positive level and a negative level of different magnitudes based on a common component, but the clock signal is restored using the differential component that is the difference between the two values, and the data signal D _x . Since is read, the data receiving apparatus 200 may react very insensitively to noise commonly occurring in the transmission pair during the transmission through the channel 260. Also, even though the edge of the strobe signal STB has a change, the strobe signal STB does not have information about time, unlike the clock signal CLK, and the clock signal CLK is relative to the strobe signal STB. Since only serves to inform the location, the data receiving apparatus 200 according to the present invention can accurately detect the clock signal.

On the other hand, when the polarity of the strobe signal STB is transmitted as data information of the promised data signal Dx predetermined by the transmission protocol, the data receiving apparatus 200 transmits the polarity of the strobe signal STB to the promised data. It can be recognized as the level of the data signal. If the promised data signal is the last data signal Dn-1 of a packet, the data receiving apparatus 200 transmits the data signal Dn when the positive level of the strobe signal STB is transmitted to the P-channel. The value of -1) is determined to be '1', and when the positive level of the strobe signal STB is transmitted to the N-channel, the value of Dn-1 is determined to be '0'.

The above-described data transmitting apparatus 100 and data receiving apparatus 200 shown in FIG. 1 may be applied to various examples. Hereinafter, when the data transmission and reception apparatuses 100 and 200 are applied to a display, the configuration and operation of the display according to an embodiment of the present invention will be described with reference to the accompanying drawings.

5 is a structural diagram of a display according to an embodiment of the present invention. FIG. 6 is a diagram illustrating only a transmission structure of a transmission signal between the timing controller 300 and the column driving circuit 500 to help understand the display illustrated in FIG. 5.

5 and 6, the display includes a timing controller 300, a display panel 400, column driving circuits 500, and row driving circuits 600. Here, the column driving circuit 500 and the row driving circuit 600 may be integrated circuit (IC). The timing controller 300 controls the column driving circuits 500 and the row driving circuits 600, and the column driving circuits 500 and the row driving circuits 600 drive the display panel 400. . The display panel 400 displays an image according to the scan signals R1 to Rn and the data signals C1 to Cm. The display panel 400 is a TFT liquid crystal display (TFT-LCD), a STN-LCD, or a FLCD (ferroelectric liquid crystal screen). LCD panel, PDP (Plasma Display Panel) panel or OLED (Organic Luminescence Electro Display) panel, FED, etc., may be various display panels usable between the timing controller 300 and the display driving integrated circuit (DDI). have.

The row driving circuits 600 apply scan signals R1 to Rn to the display panel 400, and the column driving circuits 500 apply data signals C1 to Cm to the display panel 400. The timing controller 300 receives data through the input terminal IN2, transfers a transmission signal consisting of the data signal DATA, the strobe signal STB, and the clock signal CLK to the column driving circuit 500, and drives the row. The clock signal CLK_R and the start pulse SP_R are applied to the circuit 600. At this time, although not shown, the timing controller 300 transmits a control signal for controlling the column driving circuit 500 such as a start pulse SP, which is a signal indicating that data transfer for a new horizontal scan line is started in the prior art. In accordance with the protocol, the unit packet may be delivered to the column driving circuit 500. The data signal DATA transferred from the timing controller 300 to the column driving circuit 500 may include only image data to be displayed on the display panel 400 or may further include a control signal.

The timing controller 300 corresponds to the data transmission apparatus 100 shown in FIG. 1. That is, the timing controller 300 inserts the strobe signal STB in a different size from the data signal DATA between the data signals including the data input through the input terminal IN2, and has the same size as the data signal DATA. The clock signal CLK is subsequently inserted into the strobe signal STB to generate a transmission signal, and the generated transmission signal is transmitted to the column driving circuit 500. As described above, the transmission signal may be a differential signal. In this case, only one differential pair is used to send the strobe signal STB, the clock signal CLK, and the data signal DATA from the timing controller 300 to one column driving circuit 500. Specifically, the timing controller 300 may insert the clock signal CLK immediately after the strobe signal STB as shown in FIG. 2 and transmit the strobe signal STB as shown in FIG. 3. The clock signal CLK may be inserted and transmitted at a predetermined spaced distance as a reference, and as shown in FIG. 4, the dummy signals DC1 and DC2 may be inserted into at least one of a front end and a rear end of the strobe signal STB. You can also send. 2 to 4, the timing controller 300 may set the size of the strobe signal STB to be larger than the clock signal CLK. Alternatively, the timing controller 300 may be set smaller than the clock signal CLK. In addition, the timing controller 300 may transmit at least one dummy signal DC1 and DC2, may insert and transmit a plurality of clock signals between the strobe signals STB, and may follow the clock signal CLK. The clock signal CLK may be inserted to have a polarity opposite to that of the data signal DATA, and the strobe signal STB may be inserted with a pulse width that is an integer multiple of the minimum pulse width of the data signal DATA. In addition, the timing controller 300 may transmit a control signal, for example, a start pulse SP or the like, in a unit packet according to a transmission protocol, following the strobe signal STB.

The column driving circuit 500 corresponds to the data receiving apparatus 200 shown in FIG. 1. That is, the column driving circuit 500 receives the transmission signal sent from the timing controller 300, extracts the strobe signal STB from the received transmission signal, and extracts the clock signal CLK from the extracted strobe signal STB. The data signal DATA included in the transmission signal is sampled using the recovered clock signal RCLK.

Hereinafter, the configuration and operation of embodiments of the present invention of each of the timing controller 300 and the column driving circuit 500 illustrated in FIGS. 5 and 6 will be described with reference to the accompanying drawings.

FIG. 7 is a schematic block diagram of an embodiment 300A of the present invention of the timing controller 300 shown in FIGS. 5 and 6.

The timing controller 300A illustrated in FIG. 7 includes a receiver 310, a buffer 320, a transmitter 330, a clock signal generator 340, a controller 350, and a data generator 360. The transmitter 330 and the clock signal generator 340 illustrated in FIG. 7 correspond to the transmitter 120 and the clock signal generator 110 illustrated in FIG. 1, each having the same configuration, and perform the same function. In addition, the data transmission apparatus 100 shown in FIG. 1 may further include a receiver 310 and a buffer 320 shown in FIG. 7, and the data transmission apparatus 100 may include a timing controller 300A of a display. When applied to, the timing controller 300A further includes a controller 350 and a data generator 360 in addition to the data transmitter 100.

The receiver 310 of the timing controller 300A receives the image data LVDS DATA and the external clock signal LVDS CLK 'through the input terminal IN2, and converts the received image data into a TTL (Trasistor-Transistor Logic) signal. To the data generator 360. In addition, the receiver 310 converts the external clock signal LVDS CLK 'into a TTL signal and outputs the TTL signal to the clock signal generator 340. The signal input to the receiver 310 may be a differential signal in the form of an LVDS, but the present invention is not limited thereto and may be a differential signal in the form of a transition minimized differential signal (TMDS) or a signal other than a differential signal. The TTL signal generally means a digitally converted signal, and unlike LVDS, which has a small voltage width of 0.35V, it has a large voltage width at the power supply voltage level.

The control unit 350 receives an information signal from the outside, and generates a control signal corresponding to the information signal received from the outside. At this time, the control unit 350 generates a control signal for controlling the column drive circuit 500 in accordance with a predetermined transmission protocol while using the information signal. Herein, the information signal has a form of a TTL signal, and has information for controlling a display such as a resolution of an image to be displayed on the display panel 400. In addition, the controller 350 serves to control each unit shown in FIG. 7.

The data generator 360 processes the image data DATA received from the receiver 310 according to the control signal received from the controller 350, and outputs the processed image data to the buffer 320. If the control signal is generated in the control unit 350 from an information signal having information on the resolution, the data generator 360 processes the image data so that the display panel 400 can display an image at a desired resolution. do. In addition, the data generator 360 may output a control signal to the buffer 320 together with the image data.

The buffer 320 receives image data output from the data generator 360, buffers the input image data, and outputs the image data to the transmitter 330 as a data signal DATA. In addition, the buffer 320 may output a control signal received from the data generator 360 to the transmitter 330.

The clock signal generator 340 receives the clock signal CLK 'converted into a TTL signal from the receiver 310 and generates a start pulse SP_R and a clock signal CLK_R which are transmitted to the row driving circuit 600. The clock signal CLK is transmitted to the column driving circuit 500. As such, the reason why the clock signal generator 340 generates the clock signal CLK from the external clock signal CLK 'is that the frequency and the external clock signal of the clock signal CLK to be used in the display shown in FIG. This is because the frequencies of (LVDS CLK ') may be different from each other.

The transmitter 330 inserts the strobe signal STB into the data signal received from the buffer 320 and the clock signal CLK received from the clock signal generator 340 to generate a transmission signal, and generates the transmission signal ( CD1, CD2, ..., or CDm) are output to the corresponding column drive circuit 500. That is, the transmitter 330 transmits the strobe signal STB, the clock signal CLK, and the data signal DATA to one of the column driving circuits 500 through one differential pair. The STB is inserted and transmitted in a different size than the clock signal CLK. In this case, the clock signal CLK and the data signal DATA have the same magnitude.

According to the present invention, the transmitter 330 may further include the control signal received from the controller 350 via the buffer 320 and the data generator 360 as well as the image data in the data signal DATA. In this case, the transmitter 330 may include the clock signal CLK and the control signal after the strobe signal STB.

Hereinafter, the configuration and operation of the transmitter 330 according to an embodiment of the present invention will be described.

The transmitter 330 may be implemented by a demultiplexer 332, a plurality of serial converters 334, and a plurality of drivers 336. The demultiplexer 332 separates and outputs a data signal output from the buffer 320 for each serial converter 334 in response to the clock signal CLK.

The serial converter 334 sequentially converts the strobe signal STB, the clock signal CLK, and the data signal DATA in series, and outputs the converted result to the driver 336. For example, when generating a transmission signal as shown in FIG. 2, the serial converter 334 sequentially outputs data D _{n -2} and D _{n -1} of the M th packet, and then strobe signal STB. ), And then outputs a clock signal CLK, and sequentially outputs the data D ₀ , D _1, and D ₂ of the M + 1 th packet.

The driver 336 is located between (or at a predetermined position) the clock signal CLK for the last data of the M-th packet among the signals sequentially output from the serial converter 334 and the M + 1 th packet. The strobe signal STB is converted into a different magnitude from the data signal DATA and output as a transmission signal. At this time, the driver 336 generates the transmission signal by equalizing the magnitudes of the data signal DATA and the clock signal CLK. In addition, the driver 336 also converts signals sequentially output from the serial converter 334 into differential signals.

According to an exemplary embodiment of the present invention, the driver 336 may convert the signals sequentially output from the serial converter 334 into symmetric differential signals, as shown in FIGS. 2 and 3.

According to another exemplary embodiment of the present invention, the driver 336 converts the data signal DATA and the clock signal CLK among the signals sequentially output from the serial converter 334 into symmetrical differential signals, and strobe signal STB. ) May be converted into an asymmetric differential signal and output.

On the other hand, the polarity information of the strobe signal STB can be used as data information of the promised data signal Dx predetermined by the transmission protocol. If the promised data signal Dx is the last data signal Dn-1 of a packet, the driver 336 selects a channel to transmit the positive level and the negative level of the strobe signal STB to the last data signal Dn−. Decide according to the level of 1). That is, when the level of the data signal Dn-1 is '1', the positive level of the strobe signal is transmitted through the P-channel and the negative level is transmitted through the N-channel. Alternatively, if the level of the Dn-1 is '0', the positive level of the strobe signal is transmitted through the N-channel, and the negative level is transmitted through the P-channel.

Hereinafter, the configuration and operation of the column driving circuit 500 shown in FIG. 5 according to an embodiment of the present invention will be described with reference to the accompanying drawings.

8 is a block diagram of an embodiment 500A of the present invention of the column drive circuit 500 shown in FIGS. 5 and 6. The column driving circuit 500A includes an input buffer 510, a strobe signal extraction unit 520, a clock signal recovery unit 530, a sampler 540, and a driving data processing unit 580.

The strobe signal extractor 520, the clock signal recoverer 530, and the sampler 540 illustrated in FIG. 8 may include the strobe signal extractor 210, the clock recoverer 220, and the sampler 230 illustrated in FIG. 1. Corresponding to each other, each has the same configuration and plays the same role. Therefore, the configuration and operation of each unit 520, 530, and 540 described below may be applied to each unit 210, 220, and 230 shown in FIG. 1.

First, the channel 260 connected to the timing controller 300 corresponding to the data transmitter 100 and the column driving circuit 500A corresponding to the data receiver 200 may cause various interface problems such as impedance mismatch. Can be. To address this, the input buffer 510 serves to interface the channel 260 and the column drive circuit 500A. That is, the input buffer 510 buffers the transmission signal received through the input terminal IN3 and outputs the buffered result to the strobe signal extractor 520 and the sampler 540, respectively.

The strobe signal extractor 520 extracts the strobe signal from the transmission signal received from the input buffer 510. Configuration and operation of embodiments of the strobe signal extractor 520 are as follows.

FIG. 9 is a waveform diagram illustrating the operation of the hysteresis comparator 522 shown in FIG. 8, where the horizontal axis represents the differential component Vd of the transmission signal input to the hysteresis comparator 522, and the vertical axis represents the hysteresis. The output voltage Vo of the comparator 522 is shown, respectively.

According to an embodiment of the present invention, the strobe signal extractor 520 may be implemented as a hysteresis comparator 522. The hysteresis comparator 522 outputs the strobe signal STB according to a result of comparing the differential component Vd of the transmission signal with the threshold voltage Vth. That is, the hysteresis comparator 522 changes the input differential component Vd when the differential component Vd of the input transmission signal is changed to a value higher than the positive threshold voltage Vth or lower than the negative threshold voltage -Vth. In response to the output voltage Vo, the output voltage Vo is changed to either the ground voltage or the constant voltage VDD to be used as the strobe signal STB. If not, keep the same output voltage (Vo). To this end, the driver 336 must alternately transmit the positive level and the negative level of the strobe signal STB through the P-channel and the N-channel. 9, when the differential component Vd of the transmission signal is higher than the threshold voltage Vth, the strobe signal STB of the Mth packet is generated from the hysteresis comparator 522 to the constant voltage VDD. This is because the strobe signal STB of the M + 1th packet can be changed to the ground voltage only when the differential component Vd of the transmission signal is lower than the threshold voltage -Vth. The threshold voltage Vth may be | HR-LR | with reference to FIGS. 2 to 4. As described above, since the strobe signal STB is extracted by comparing the differential component Vd of the transmission signal with the threshold voltage Vth, the clock signal CLK and the data signal DATA received by the column driving circuit 500A. Even if the level of the common component, which is the intermediate level of the differential components, varies, the strobe signal STB can be properly detected by the column driving circuit 500.

10 (a) and 10 (b) show a block diagram and an operation waveform diagram of another embodiment according to the present invention of the strobe signal extraction unit 520 shown in FIG. 8, respectively.

The strobe signal extractor illustrated in FIG. 10A includes first and second level comparators 524 and 525, first and second synthesizers 526 and 527, and a first logical sum 528. Here, VDD represents the operating voltage of each comparator 524 and 525.

According to another embodiment of the present invention, the first synthesizer 526 synthesizes the N-channel component and the first offset level | Voffset1 | among the differential inputs of the transmission signal, and compares the synthesized result with the first level comparator ( 524) is output to the negative input terminal. The second synthesizer 527 synthesizes the P-channel component and the second offset level (-| Voffset2 |) among the differential inputs of the transmission signal and converts the synthesized result into the negative input terminal of the second level comparator 525. Output The first level comparator 524 compares the P-channel component of the received transmission signal with the level of the result synthesized by the first synthesizer 526 and outputs the compared result to the first logical sum unit 528. In addition, the second level comparator 525 compares the N-channel component of the received transmission signal with the level of the result synthesized by the second synthesizer 527, and outputs the compared result to the first logical sum unit 528. . The first logic sum unit 528 may OR the outputs of the first and second level comparators 524 and 525, and output the result of the logic sum as the strobe signal STB.

The first offset level should have a value greater than the differential component of the data signal when the differential component of the data signal (subtracting the N-channel component from the P-channel component) is positive. For example, in the case of FIGS. 2 to 4, the first offset level may be the level HR-LR. In addition, the second offset level should have a lower value than the differential component of the data signal when the differential component of the data signal is negative. For example, in the case of FIGS. 2 to 4, the second offset level may be the level LR-HR. The first offset level and the second offset level may have the same absolute value or different values.

Referring to FIG. 10B, the strobe signal extractor illustrated in FIG. 10A shows the high level VDD when the differential component of the transmission signal is larger than the first offset level, for example, the level HR-LR. Output the strobe signal STB and output the strobe signal STB having the high level VDD when the differential component of the transmission signal is lower than the negative second offset level, for example, the level LR-HR. .

Meanwhile, the sampler 540 illustrated in FIG. 8 serves to sample the data signal in response to the clock signal RCLK from the transmission signal received from the input buffer 510. According to an embodiment of the present invention, the sampler 540 may be implemented as a third level comparator 542 and a first D flip-flop 544.

The third level comparator 542 compares the differential components of the transmission signal input from the input buffer 510 with each other, and outputs the compared result to the data input terminal D of the first D flip-flop 544. For example, referring to FIG. 2, the third level comparator 542 compares two differential components of the data signal D ₀ , outputs a "high" logic level of '1', and outputs the data signal D ₁ . The two differential components are compared to output a "low" logic level of '0', and the two differential components of the data signal D2 are compared to output a "high" logic level of '1'.

The first D flip-flop 544 receives the result compared by the third level comparator 542 through the data input terminal D, and corrects the result in response to the clock signal CLK input to the clock terminal. Output through output terminal (Q).

In addition, the sampler 540 may additionally perform a function of converting the sampled data into parallel data.

Hereinafter, the configuration and operation of the embodiment of the clock recovery unit 530 shown in FIG. 8 will be described as follows.

According to an embodiment of the present invention, the clock recovery unit 530 may be implemented as a clock signal detector 532 and a PLL (or DLL) 534. In response to the signal CLK + DATA output from the third level comparator 542, the clock signal detector 532 may select at least one of a leading edge and a trailing edge of the clock signal CLK input subsequent to the strobe signal STB. Detect.

FIG. 11 is a block diagram of a preferred embodiment of the clock signal detector 532 of FIG. 8 according to the present invention, wherein the second and third D flip-flops 550 and 552, the inverter 551, and the second logic sum It consists of 554.

FIG. 12 illustrates waveform diagrams input and output to each unit shown in FIG. 11, and an arrow on the edge indicates clock information.

The second D flip-flop 550 shown in FIG. 11 inputs a constant voltage VDD to the data input terminal D, and outputs a signal CLK + DATA output from the third level comparator 542 to a clock terminal ( CK) and the strobe signal STB to the clear (CL) terminal. Accordingly, the second D flip-flop 550 outputs the constant voltage VDD in response to the result of comparison by the third level comparator 542 of the sampler 540 and is cleared in response to the strobe signal STB.

The inverter 551 inverts the result compared by the third level comparator 542 of the sampler 540 and outputs the inverted result to the clock terminal CK of the third D flip-flop 552.

The third D flip-flop 552 inputs the constant voltage VDD to the data input terminal D and outputs the result of inverting the signal CLK + DATA output from the third level comparator 542. ) And the strobe signal (STB) to the clear (CL) terminal. Accordingly, the third D flip-flop 552 outputs the constant voltage VDD in response to the inverted signal from the inverter 551 and is cleared in response to the strobe signal STB.

The second logic sum unit 554 may OR the signals output from the positive output terminals Q of the second and third D flip-flops 550 and 552, and detect the result of the OR by the clock signal detector 532. And output as the completed clock signal CLK ".

In FIG. 11, the second flip-flop 550 is a means for detecting the first rising edge that is input after the strobe signal STB in the signal CLK + DATA output from the third comparator 542. The flop 552 and the inverter 551 are means for detecting the first falling edge which is input following the strobe signal STB in the output signal CLK + DATA of the third comparator 542.

11, since only the first edge of the signal following the strobe STB is detected and used as clock information, the polarity of the data signal Dx subsequent to the clock signal need not be considered.

The clock signal differs from the data signal in that it has time information on the rising edge or the falling edge. In the case of the phase modulation scheme, information of the data may be included in the phase, but in general, the data signal has information at a low logic level or a high logic level. Therefore, if only one of the rising edge or the falling edge of the clock signal is detected in every packet, the PLL (or DLL) 534 is used to obtain the entire clock signal that can sample all the data signals Dx in each packet. Can be restored Here, the PLL 534 (or DLL) generates a plurality of edges whose phases are delayed at regular intervals between the clock signals detected in each packet, synthesizes them, and sends them to the recovered clock signal RCLK.

8, the PLL (or DLL) 534 generates the clock signal RCLK by using the edge of the clock signal CLK "detected by the clock signal detector 532. In the case of FIGS. The starting point of the clock signal is made using only one of the rising (a, c or e) or the falling edge (b, d or f) of the clock signal CLK "detected by the clock signal detecting unit 532, and based on this, any By generating a clock signal having a width of, it is possible to recover the clock signal as shown in FIG. 8. In this case, the trailing edge of the randomly generated clock signal CLK "is not used for restoring the clock signal. The clock signal detector 532 described above detects any one of the leading edge and the trailing edge of the clock signal. However, the PLL (or DLL) 534 may not be used, in which case the detected clock signal (CLK) is delayed at regular time intervals and used as a point in time for sampling every data. The period of the inserted clock signal CLK is equal to the length of one packet, and if the length becomes 10 times or more than the width of each data, the column driving circuit 500A removes the PLL (or DLL) 534. It is preferable to generate a clock signal RCLK having a period equal to the width of the data.

Meanwhile, the driving data processor 580 receives data sampled by the sampler 540, converts the received data into a display panel driving signal suitable for driving the display panel 400, and converts the converted signals Y1, Y2, ... and Yk) are output to the display panel 400. Here, the signals Y1, Y2, ..., and Yk in analog form are one of C1 to Cm shown in FIG. For example, when the sampled data is not aligned in time, the driving data processor 580 matches the time points at which the values of the data change, and arranges them. In addition, in response to a result of sequentially shifting the start pulse SP, the driving data control unit 580 sequentially stores data included in the alignment data signal and outputs the data in parallel. At this time, the signals output in parallel are converted into analog signals Y1, Y2, ... and Yk. Here, the start pulse SP may be generated by the driving data processor 580 in response to a clock signal from a packet received according to a transmission protocol.

13 is a structural diagram of a display according to another embodiment of the present invention. FIG. 14 is a diagram illustrating only a transmission structure of a transmission signal between the timing controller 302 and the column driving circuit 502 to help understand the display shown in FIG. 13.

The display shown in FIGS. 5 and 6 uses a point to point scheme, while the display shown in FIGS. 13 and 14 uses a point to couple scheme. Except for this, since the display shown in FIGS. 13 and 14 has the same configuration and operation as the display shown in FIGS. 5 and 6, the description of the same parts will be omitted. That is, the timing controller 302, the display panel 402, the column driving circuit 502, and the row driving circuit 602 include the timing controller 300, the display panel 400, and the column driving circuit 500 illustrated in FIG. 5. ) And the row driving circuit 600, respectively, and perform the same function.

In the case of the display shown in Figs. 5 and 6, one differential pair is connected to one column driving circuit 500, while the display shown in Figs. 13 and 14 is connected to two column driving circuits 502. Differential pairs are connected. Thus, the amount of data transferred through the differential pair doubles compared to the display shown in FIGS. 5 and 6. That is, when the display is implemented as illustrated in FIGS. 5 and 6, the demultiplexer 332 illustrated in FIG. 7 may convert a data signal corresponding to one column driving circuit 500 into one serial converter ( 334). However, when the display is implemented as shown in FIGS. 13 and 14, the demultiplexer 332 outputs data signals corresponding to the plurality of column driving circuits 502 to one serial converter 334. .

If a time error occurs, the clock signal may not be correctly restored. Therefore, the exact position of the data signal is not known, and the position different from the error is known. However, according to the present invention, in transmitting the data signal and the clock signal between the timing controller 300 or 302 and the column driving circuit 500 or 502 in the display, the time error of the clock signal generated when the clock signal is restored. (Timing skew error) For example, the change in the time interval between the clock signals and / or the time interval between the clock signal and the data signal is very small so that the clock signal can be more stably restored. Therefore, performance of 1.5 Gbps / ch or more can be realized.

On the other hand, prior to transmitting data at the side 100, 300 or 302 transmitting the data, a period for restoring the clock signal for a predetermined time may be provided at the side 200, 500 or 502 receiving the data. . During this period, the sending side 100, 300 or 302 does not transmit valid data.

Although the description has been made on the assumption that the data transmitting apparatus 100 and the data receiving apparatus 200 illustrated in FIG. 1 are applied to a display, the data receiving apparatus 100 and the data transmitting apparatus 200 may also be applied to the processing of a voice signal. Can be. In this case, the receiver 310 of the data transmitter 100 receives voice data, and the buffer 320 buffers the voice data and outputs the voice data to the transmitter 330 as a data signal. Otherwise, the operation of the data receiving apparatus 200 is the same as in the above-described processing of image data.

In the case of FIG. 5 described above, only one pair of signals are transmitted from the timing controller 300 to each column driving circuit 500, but the present invention is not limited thereto. Here, one pair of signals means a pair of P-channel and N-channel as described above. That is, in order to transfer more data between the timing controller 300 and each column driver circuit 500, a plurality of pairs of signals may be transmitted from the timing controller 300 to each column driver circuit 500.

Likewise, in FIG. 13, only one pair of signals is transmitted from the timing controller 302 to the two column drive circuits 502, but the present invention is not limited thereto. That is, in order to transfer more data between the timing control unit 302 and the two column drive circuits 502, a plurality of pairs of signals may be transmitted from the timing control unit 302 to the two column drive circuits 502. .

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a block diagram of a data transmitting apparatus and a data receiving apparatus according to an embodiment of the present invention.

2 to 4 show exemplary waveform diagrams of a transmission signal generated in a transmission unit according to embodiments of the present invention.

5 is a structural diagram of a display according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating only a transmission structure of a transmission signal between a timing controller and a column driving circuit to help understand the display illustrated in FIG. 5.

FIG. 7 is a schematic block diagram of an embodiment of the present invention of the timing controller illustrated in FIGS. 5 and 6.

8 is a block diagram of an embodiment of the present invention of the column drive circuit shown in FIGS. 5 and 6.

FIG. 9 is a waveform diagram illustrating the operation of the hysteresis comparator illustrated in FIG. 8.

10 (a) and (b) show a block diagram and an operation waveform diagram of another embodiment according to the present invention of the strobe signal extraction unit shown in FIG. 8, respectively.

FIG. 11 is a block diagram of a preferred embodiment of the present invention of the clock signal detector shown in FIG. 8.

FIG. 12 shows waveform diagrams input and output to each unit shown in FIG. 11.

13 is a structural diagram of a display according to another embodiment of the present invention.

FIG. 14 is a diagram illustrating only a transmission structure of a transmission signal between the timing controller and the column driving circuit to help understand the display illustrated in FIG. 13.

* Explanation of symbols for main parts of the drawings

100: data transmission device 200: data receiving device

110, 340: clock signal generator 120, 330: transmitter

210, 520: strobe signal extraction unit 220, 530: clock recovery unit

230, 540: sampler 300, 302: timing controller

310: receiver 320: buffer

332: demultiplexer 334: serial converter

336 drive unit 350 control unit

360: data generator 400, 402: display panel

500, 502: column drive circuit 510: input buffer

522: hysteresis comparator 524, 525, 542: level comparator

526, 527: synthesizer 528, 554: logical sum

532 a clock signal detector 534 DLL or PLL

544, 550, 552: D flip-flop 551: inverter

580: driving data processing unit 600, 602: row driving circuit

Claims (11)

A strobe signal is inserted between the data signals in a different size than the data signal, and a clock signal having the same magnitude as the data signal receives a transmission signal inserted subsequent to the strobe signal, and receives the differential component of the received transmission signal. A strobe signal extractor configured to extract the strobe signal corresponding to a result compared with first and second offset levels; A clock recovery unit which restores the clock signal from the received transmission signal using the extracted strobe signal; And A sampler for sampling the data signal included in the received transmission signal in response to the restored clock signal, The sampler A third level comparator for comparing the differential components of the transmission signal and outputting a compared result; And And a first D flip-flop configured to output a result compared by the third level comparator in response to the restored clock signal. The method of claim 1, wherein the strobe signal extractor A first synthesizer for synthesizing an N-channel component and the first offset level among the differential components of the transmission signal and outputting a synthesized result; A second synthesizer for synthesizing the P-channel component and the second offset level among the differential components of the transmission signal and outputting the synthesized result; A first level comparator for comparing the P-channel component of the transmission signal with a level of a signal output from the first synthesizer and outputting a result of the comparison; A second level comparator for comparing the N-channel component of the transmission signal with the level of the signal output from the second synthesizer and outputting a result of the comparison; And And a first logic summation unit configured to OR the outputs of the first and second level comparators and output the result of the OR as the extracted strobe signal. The data receiving apparatus of claim 2, wherein the first offset level is greater than the differential component of the data signal when the differential component of the data signal is positive. The data receiving apparatus of claim 2, wherein the second offset level is lower than the differential component of the data signal when the differential component of the data signal is negative. The data receiving apparatus of claim 2, wherein an absolute value of the first offset level and the second offset level is the same. delete delete The method of claim 1, wherein the clock recovery unit And a clock signal detection unit configured to extract at least one of a leading edge and a trailing edge of the clock signal input subsequent to the extracted strobe signal. The method of claim 8, wherein the clock recovery unit And a delay lock loop for restoring the clock signal by using the edge extracted by the clock signal detector. The method of claim 8, wherein the clock recovery unit And a phase locked loop for restoring the clock signal by using the edge extracted by the clock signal detector. The method of claim 8, wherein the clock signal detector A second D flip-flop that outputs a constant voltage in response to a result compared by the first comparator and is cleared in response to the strobe signal; An inverter for inverting the result compared in the first comparator; A third D flip-flop that outputs the constant voltage in response to the inverted signal at the inverter and is cleared in response to the strobe signal; And And a second logic summation unit configured to OR the signals output from the second and third D flip-flops, and output a result of the OR as a clock signal detected by the clock signal detector.

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