KR100922882B1 - Control circuit for termination - Google Patents

Abstract

PURPOSE: A termination control circuit is provided to stably control a dynamic termination operation although a peripheral situation is changed. CONSTITUTION: A termination control circuit includes a storing part(810), a first comparing part(820), an adding part(830), and a second comparing part(840). The storing part stores an external code in response to a write command. The first comparing part compares a value of the external code with an internal code, and generates an activation signal of a dynamic termination operation. The adding part adds a fixed value to the value of the external code according to a burst length. The second comparing part compares the value of the external code added by the adding part with the internal code, and generates a deactivation signal of the dynamic termination operation.

Description

Termination Control Circuit {CONTROL CIRCUIT FOR TERMINATION}

The present invention relates to a termination control circuit that determines the start and end of the termination operation, and particularly to prevent the malfunction of the termination control circuit.

With the increase in capacity / speed of semiconductor memory devices (DRAM) and the advent of DDR SDRAM, several new concepts have been added to control the data transfer speed of memory devices faster. Among them, the termination resistance is necessary to facilitate signal transmission between the devices.

In this case, if the resistance is not properly matched, the transmitted signal is reflected and a signal transmission error is likely to occur. However, when a fixed resistance is applied to the outside, it cannot be properly matched due to aging of the integrated circuit, temperature change, or difference in manufacturing process. Accordingly, in recent years, a technique for adjusting the resistance of the termination stage has been proposed and used by adjusting the number of turned-on transistors among the plurality of transistors connected in parallel so that the resistance value is the same as compared with the external reference resistor.

The termination control circuit refers to a circuit that controls on / off of a termination operation for terminating an input / output pad in response to a termination command input from an outside of the memory device. The termination command input from the outside is input in synchronization with the external clock, but the memory device operates in synchronization with the internal clock. Therefore, the termination command input from the outside should be domain-crossed by the internal command, and the termination control circuit is a circuit that performs this role.

In addition, Dynamic Termination (Dynamic ODT) operation must be supported from DDR3 SDRAM according to the specifications set by JEDEC. Dynamic termination operation refers to an operation that sets the resistance value of the termination resistor inside the chip to have the resistance value required for data input even when the write command is input, even if the mode register set (MRS) is not set again.

The interface of the semiconductor memory device differs in the termination method and the resistance value at the time of data input and output. When outputting data, the DQ pad is pulled up or pulled down to output 'high' or 'low' data.When data is input, a constant resistance value (different from the resistance value at data output) With the input / output pads pulled up and pulled down, you can receive data. Starting with DDR3 memory devices that support dynamic termination operation, the on-die termination circuit inside the chip performs the proper operation for data input only by inputting a write command.

That is, the termination control circuit controls the start and end of the termination operation according to the termination command input from the outside, and controls the start and end of the dynamic termination operation according to the write command input from the outside.

1 is a block diagram of a conventional termination control circuit.

The termination control circuit includes a clock divider 101, a replica delay unit 102, an internal counter 110, an external counter 120, a normal controller 130, and a dynamic controller 140.

The clock divider 101 receives an internal clock DLLCLK1 supplied through a delay lock loop (DLL), and toggles the clock DLLCLK2 until the reset signal RST is released. To prevent. When the reset signal RST is released, the internal clock DLLCLK2 that is toggled is output. In other words, the DLLCLK1 and the DLLCLK2 are the same internal clocks, but the DLLCLK2 does not toggle until the reset signal RST is released and maintains a constant level. The reset signal RST is a signal that is enabled when the termination control circuit does not operate and then disabled when the termination control circuit operates. For example, in the asynchronous mode, the termination control circuit does not need to operate. In this case, the reset signal RST is enabled so that the domain crossing circuit stops operating and the internal code values (DLLCNT <2: 0>, EXTCNT) <2: 0>) and so on.

The replica delay unit 102 is a block modeling a time difference existing between the internal clock DLLCLK2 and the external clock EXTCLK, and the time with the external clock EXTCLK is input to the internal clock DLLCLK2. The external clock (EXTCLK) is output to reflect the difference.

The internal counter 110 is initialized by the reset signal RST, and counts the internal clock DLLCKL2 from the time when the reset signal RST is released to output the internal code DLLCNT <2: 0>. The initial value of the internal code DLLCNT <2: 0> has an initial value determined according to Cas Write Latency (CWL). This is because the start time of the internal termination operation is changed from the time of applying the external command according to the cas light latency CWL. Since the caslight latency CWL is defined in the specification so that the value itself is limited to the operating frequency, the initial value is determined according to the caslight latency CWL, which is equivalent to the initial value determined according to the operating frequency. Has meaning.

The external counter 120 is initialized by the reset signal RST, and the external clock EXTCLK is counted from the time when the reset signal RST is released to output the external code EXTCNT <2: 0>. The initial value of the external code EXTCNT <2: 0> is set to zero.

The normal controller 130 generates a normal termination command ODTEN in response to a command (ODT_startp, ODT_endp, signals generated by an external command) from an external memory controller. The memory device determines the start point and the end point of the termination operation in response to the normal termination command ODTEN, which is an internal command.

The dynamic controller 140 generates a dynamic termination command DYNAMIC ODTEN, which is an internal command, in response to the write command WT_startp (a signal generated by the write command, which will be described in detail later). The memory device starts a dynamic termination operation in response to the internal termination of the dynamic termination command DYNAMIC ODTEN, and stops the dynamic termination operation in response to the dynamic termination command DYNAMIC ODTEN being disabled.

2 is a diagram for describing an operation of the dynamic controller 140 of FIG. 1.

The internal counter 110 does not operate before the reset signal RST is released, and the internal code DLLCNT <0: 2> has an initial value of 5 (determined according to CWL, as described above). Likewise, the external counter 120 does not operate before the reset signal RST is released, and the external code EXTCNT <2: 0> has an initial value of zero. When the reset signal RST is released, the internal counter 110 and the external counter 120 are enabled, and the internal clock DLLCLK2 also starts to toggle. Since the external clock EXTCLK is generated by delaying the internal clock DLLCLK2, the external clock EXTCLK is toggled later than the internal clock DLLCLK2. Therefore, the inner code DLLCNT <2: 0> starts counting first, and after the time equal to the delay value of the replica delay unit 102, the outer code EXTCNT <2: 0> starts counting.

When the write command is input while the internal code DLLCNT <2: 0> and the external code EXTCNT <2: 0> are counted, the WT_STARTP pulse signal is enabled in response. The external code EXTCNT <2: 0> at the time of enabling the WT_STARTP pulse signal is stored (1 is stored in the drawing). When the internal code (DLLCNT <2: 0>) is equal to the value of the stored external code (EXTCNT <2: 0>, 1), the DYNAMIC_ON signal is enabled as 'low', which is the internal command dynamic termination. Enable the command (DYNAMIC ODTEN). When the dynamic termination command DYNAMIC ODTEN is enabled, the dynamic termination operation of the memory device starts.

Now we'll discuss disabling the dynamic termination command. The external code stored in response to the write command (EXTCNT <2: 0>, value of 1) is added with a predetermined value according to the burst length (BL). When the burst length BL is 8, 8 data are inputted to the rising / falling of the clock, so 4 clocks are required to input data and 6 clocks are required in consideration of timing margins. In addition, when the burst length BL is 4, a total of 4 clocks is required by adding 2 clocks for data input and 2 clocks at the front and rear.

Therefore, when the burst length BL is 8, 6 is added to the stored external code (EXTCNT <2: 0>, 1 value) (the figure illustrates BL = 8, thus 1 + 6 = 7 value). If the burst length is 4, 4 is added to the stored external code (EXTCNT <2: 0>) (i.e., (BL / 2) +2 is added) and a certain value is added. The value of the external code (EXTCNT <2: 0>) (7) and the value of the internal code (DLLCNT <2: 0>) are compared and the value of the internal code (DLLCNT <2: 0>) is added to a certain value When the value (7) of (EXTCNT <2: 0>) is equal to (7), the DYNAMIC_OFF signal is enabled low, which disables the DYNAMIC ODTEN instruction. As a result, the dynamic termination operation is terminated.

In this manner, the dynamic control unit 140 enables the dynamic termination operation after a predetermined time when the write command is input, and disables the dynamic termination operation after securing a required time and a constant margin for data input.

FIG. 3 is a diagram to help understand the WT_STARTP pulse signal of FIG. 2.

The WT_STARTP pulse signal is basically enabled in response to a write command. As shown in the figure, an external casing command (CAS) corresponding to a write command is input and enabled after some time in which an additive latency (AL) is reflected.

In detail, when the external cas command CAS corresponding to the write command is input, the WC_STARTP pulse signal is enabled after a predetermined delay is received by the internal input circuit in synchronization with the clock CLK. That is, the WT_STARTP pulse signal can be regarded as a signal generated by a write command inputted from the outside and delayed slightly. For reference, the pulse width of the WT_STARTP pulse signal may be appropriately set depending on the margin.

4 is a view for explaining the operation of the normal control unit 130 of FIG.

The internal counter 110 does not operate before the reset signal RST is released, and the internal code DLLCNT <0: 2> has an initial value of 5 (determined according to CWL, as described above). Likewise, the external counter 120 does not operate before the reset signal RST is released, and the external code EXTCNT <2: 0> has an initial value of zero. When the reset signal RST is released, the internal counter 110 and the external counter 120 are enabled, and the internal clock DLLCLK2 also starts to toggle. Since the external clock EXTCLK is generated by delaying the internal clock DLLCLK2, the external clock EXTCLK is toggled later than the internal clock DLLCLK2. Therefore, the inner code DLLCNT <2: 0> starts counting first, and the outer code EXTCNT <2: 0> starts counting after a time equivalent to the delay value of the replica delay unit 102.

Meanwhile, the ODT_STARTP signal generated by the command of the external memory controller is enabled. The external code (EXTCNT <2: 0>) at the time of enabling the ODT_STARTP pulse signal is stored (1 in the drawing) and the external code (EXTCNT <2) in which the internal code (DLLCNT <2: 0>) is stored. When it is equal to the value of: 0>, 1), the ODT_DLL_STARTBP signal is enabled as 'low', and this signal is the normal termination command which controls the normal termination operation (meaning the existing operation rather than the dynamic termination operation). Enable (ODTEN) to start the normal termination operation.

The disable of the normal termination command ODTEN is the same as the enable. By using the ODT_ENDP signal generated by the command of the external controller, the external code (EXTCNT <2: 0>) at the time of enabling is stored (6 in the drawing), and the internal code (DLLCNT <2: 0>). If the value of is equal to the value of the stored external code (EXTCNT <2: 0>, 6), the ODT_DLL_ENDBP signal is enabled as 'low', and this signal disables the normal termination command (ODTEN) to enable normal termination. Let it end.

In other words, both the start and end of the normal termination operation are essentially controlled by an external memory controller.

FIG. 5 is a diagram for better understanding of the ODT_STARTP signal and the ODT_ENDP signal of FIG. 4.

The ODT_STARTP and ODT_ENDP signals are basically generated by input from an external memory controller (also called an external chipset). An external ODT instruction is a signal input from an external memory controller to satisfy a setup hold condition. The ODT command generates an ODT_COM signal which is delayed for a predetermined time by adding an additive latency after synchronizing with a clock. At the time of enabling and disabling the ODT_COM signal, the ODT_STARTP signal and the ODT_ENDP signal, which are pulse signals, are enabled.

6 is a configuration diagram of the dynamic controller 140 of FIG. 1.

The dynamic controller 140 includes a storage unit 610, a first comparator 620, an adder 630, a second comparator 640, and a controller 650, and a first comparator 620. And a first comparison control unit 621, a second comparison control unit 641, and a delay unit 642 for controlling the on / off of the second comparison unit 640.

The storage unit 610 stores the external code EXTCNT <2: 0> in response to the write command WT_STARTP. That is, in FIG. 2, when the write command WT_STARTP is enabled, the storage unit is responsible for storing a value of '1' of the external code EXTCNT <2: 0>. The storage unit 610 may be configured as D flip-flops that store the external code EXTCNT <2: 0> in response to the write command WT_STARTP. The drawing illustrates an example in which the external code EXTCNT <2: 0> is composed of three bits, and in this case, three D flip-flops may be used.

The first comparison unit 620 compares the value of the external code EXTLAT <2: 0> stored in the storage unit 610 with the internal code DLLCNT <2: 0>, and activates the activation signal DYNAMIC_ON of the dynamic termination operation. Create The activation signal DYNAMIC_ON is activated when the value of the stored external code EXTLAT <2: 0> and the internal code DLLCNT <2: 0> are the same. That is, the first comparator 620 controls the start of the dynamic termination operation. Since this operation has been described in detail with reference to FIG. 2, a detailed description thereof will be omitted.

The first comparison controller 621 controls the on / off of the first comparison unit 620. The first comparison control unit 621 activates the first comparison unit 620 in response to the write command WT_STARTP and responds to the activation signal DYNAMIC_ON. Deactivate the first comparator 620. That is, COMPEN1, which is an enable signal of the first comparator 620, is activated by the write command WT_STARTP and is inactivated by the activation signal DYNAMIC_ON. The first comparison control unit 621 may be configured with an SR latch.

The summation unit 630 adds a predetermined value to the value of the stored external code EXTLAT <2: 0> according to the burst length BL. As described above, the adder 630 adds a value of (BL / 2) +2 to the stored external code EXTLAT <2: 0>.

The second comparator 640 compares the value of the external code EXTADD <2: 0> output from the adder 630 with the internal code DLLCNT <2: 0> to deactivate the signal DYNAMIC_OFF of the dynamic termination operation. ) The deactivation signal DYNAMIC_OFF is activated when the value of the added external code EXTADD <2: 0> is equal to the internal code DLLCNT <2: 0>. That is, the second comparator 640 controls the end of the dynamic termination operation. Since this operation has been described in detail with reference to FIG. 2, a detailed description thereof will be omitted.

The second comparison controller 641 controls the on / off of the second comparison unit 640, and activates the second comparison unit 640 in response to the write command WT_STARTPD delayed by the delay unit 642. The second comparison unit 640 is deactivated in response to the deactivation signal DYNAMIC_OFF. That is, the enable signal COMPEN2 of the second comparator 640 is activated by the delayed write command WT_STARTPD and is inactivated by the deactivation signal DYNAMIC_OFF. The second comparison control unit 641 may be simply configured with an SR latch.

The controller 650 activates the DYNAMIC ODTEN signal in response to the activation signal DYNAMIC_ON, and deactivates the DYNAMIC ODTEN signal in response to the deactivation signal DYNAMIC_OFF. The DYNAMIC ODTEN signal allows the memory device to perform dynamic termination while active.

The second comparison controller 641 is activated by the write command delayed by the delay unit 642 to start an operation. In other words, the second comparator 640 and the first comparator 620 are different from each other in starting the operation by the delay value of the delay unit 642. The delay value of the delay unit 642 depends on the change in the power supply voltage VDD. When the level of the power supply voltage VDD increases, the delay value of the delay unit 642 decreases, and when the level of the power supply VDD pressure decreases, the delay value of the delay unit 642 increases. As the delay value of the delay unit 642 changes, the second comparator 640 may malfunction. This will be described below.

FIG. 7 is a diagram illustrating a case where a malfunction of the termination control circuit occurs due to a decrease in the delay value of the delay unit 642 due to variations in the power supply voltage VDD. The case where BL = 8 is illustrated.

With the activation of the write command WT_STARTP, the code value '2' of the external code EXTCNT <2: 0> is stored in the storage unit 610. In addition, the first comparator 620 is activated by the write command WT_STARTP. When the delay value of the delay unit 642 decreases, the second comparison unit 640 is activated immediately after the operation of the first comparison unit 620 starts. The adder 630 adds '6' to the external codes EXTLAT <2: 0> and '2' stored in the storage 610. The second comparison unit 640 activates the deactivation signal DYNAMIC_OFF as low when the code value of the internal code DLLCNT <2: 0> becomes '0' (= 2 + 6). Yet, the DYNAMIC ODTEN signal is not activated 'high' but the deactivation signal (DYNAMIC_OFF) is activated to 'low' in advance. The second comparator 640 stops the operation by activating the deactivation signal DYNAMIC_OFF.

Thereafter, when the code value of the internal code DLLCNT <2: 0> reaches '2', the first comparison unit 620 activates the activation signal DYNAMIC_ON to 'low'. Therefore, the DYNAMIC ODTEN signal is activated 'high'. However, since the second comparator 640 has stopped operating, the DYNAMIC ODTEN signal continues to be 'high'. In other words, the dynamic termination operation starts but does not end.

In summary, as a result of the delay value of the delay unit 642 becoming small, and the second comparison unit 640 is activated too soon, a dynamic termination operation starts but does not end.

In the above-described example, the delay value of the delay unit 642 is reduced and malfunction occurs in the termination control circuit. However, the same problem occurs even if the delay value of the delay unit 642 increases. When the write command WT_STARTP is applied at the minimum tCCD interval, the value of the external code EXTLAT <2: 0> stored in the storage unit 630 is continuously changed. In this case, if the delay value of the delay unit 642 is large, The operation timing of the second comparator 640 may be delayed, thereby causing a problem in that the termination of the dynamic termination operation is delayed.

 That is, in the conventional configuration, there is a problem in that a malfunction occurs in the dynamic termination operation, in which the delay value of the delay unit 642 is increased or decreased.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to prevent a malfunction of the termination control circuit.

The termination control circuit according to the present invention includes a storage unit for storing an external code in response to a write command; A first comparison unit configured to generate an activation signal of a dynamic termination operation by comparing the stored external code value with an internal code; An adder for adding a predetermined value to a value of the stored external code according to a burst length; And a second comparator configured to generate a deactivation signal of a dynamic termination operation by comparing the internal code with the value of the external code activated by the activation signal and added by the adder.

The second comparator may be deactivated in response to the deactivation signal.

The first comparator may be activated in response to the write command and inactivated in response to the activation signal.

In the termination control circuit according to the present invention, the second comparator, which serves to terminate the dynamic operation, starts operation in response to the activation signal. Therefore, there is an advantage that it is possible to stably control the termination of the dynamic termination operation without malfunction even if the surrounding conditions such as the power supply voltage is changed.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

8 is a configuration diagram of a termination control circuit according to the present invention.

The termination control circuit according to the present invention includes a storage unit 810 for storing an external code EXTCNT <2: 0> in response to a write command WT_STARTP; A first comparison unit 820 for generating an activation signal DYNAMIC_ON of the dynamic termination operation by comparing the value of the stored external code EXTLAT <2: 0> with the internal code DLLCNT <2: 0>; An adder 830 that adds a predetermined value according to the burst length BL to the value of the stored external code EXTLAT <2: 0>; And comparing the value of the external code EXTADD <2: 0>, which is activated by the activation signal DYNAMIC_ON and added by the adder 830, with the internal code DLLCNT <2: 0>, and deactivation signal of the dynamic termination operation ( DYNAMIC_OFF) to generate a second comparison unit 840. And a controller 850 for generating a signal enabled during the dynamic termination operation in response to the activation signal DYNAMIC_ON and the deactivation signal DYNAMIC_OFF.

Since the present invention aims to prevent a malfunction of the dynamic termination operation, a portion for controlling the normal termination operation not related to the present invention is omitted in the drawings. Also, the inner code DLLCNT <2: 0> and the outer code EXTCNT <2: 0> reflecting a skew between the inner clock DLLCLK and the outer clock EXTCLK may be generated in the same manner as in the prior art. Therefore, in the drawings, illustration of the configuration related thereto is omitted.

In the prior art, by determining the activation time of the second comparator 840 through the delay unit (642 of FIG. 6), there is a problem that a malfunction occurs in the dynamic termination operation. Therefore, in the present invention, the activation time of the second comparison unit 840 is controlled differently from the prior art.

The second comparator 840 is activated in response to the activation signal DYNAMIC_ON. The activation signal DYNAMIC_ON is a signal for starting the dynamic termination operation. And the second comparator 840 exists to end the termination operation already started. Therefore, if the second comparison unit 840 is configured to start the operation by the activation signal DYNAMIC_ON, the second comparison unit 840 always operates only after the termination operation is started. The problem that the 840 does not terminate the termination operation does not occur.

In addition, since the second comparator 840 starts operation in response to the activation signal DYNAMIC_ON, the second comparator 840 is not activated late. Anyway, the second comparison unit 840 exists to conventionally initiate the termination operation already started, and since the second comparison unit 840 starts operation as soon as the termination operation is started, the second comparison unit 840 as in the prior art. The problem of terminating the termination operation too late does not occur.

The second comparison controller 841 activates the CMPEN2 signal, which is the enable signal of the second comparison unit 840, in response to the activation signal DYNAMIC_ON, and deactivates the CMPEN2 signal of the second comparison unit in response to the deactivation signal DYNAMIC_OFF. Let's do it.

Since the configuration and operation of the other parts are the same as the conventional termination control circuit described in the background section, further description thereof will be omitted.

9 is a diagram illustrating that the dynamic termination operation is controlled by the termination control circuit according to the present invention. FIG. 9 illustrates a case where the inner code DLLCNT <2: 0> and the outer code EXTCNT <2: 0> have the same skew as in FIG. 7.

With the activation of the write command WT_STARTP, the code value '2' of the 'subcode EXTCNT <2: 0>' is stored in the storage unit 810. In addition, the first comparator 820 is activated by the write command WT_STARTP. The adder 830 adds '6' to the external code EXTLAT <2: 0> stored in the storage 810. The first comparator 820 activates the activation signal DYNAMIC_ON low when the internal code DLLCNT <2: 0> becomes '2'. This activates the DYNAMIC ODTEN signal, which starts the dynamic termination operation.

In addition, the second comparator 840 is activated in response to the activation signal DYNAMIC_ON. The second comparator 840 activates the deactivation signal DYNAMIC_OFF as low when the internal code DLLCNT <2: 0> becomes '0' (= 2 + 6). As a result, the DYNAMIC ODTEN signal is disabled and the dynamic termination operation is terminated.

In the present invention, since the second comparator 840 is designed to start the operation by the activation signal DYNAMIC_ON, the termination of the dynamic termination operation can be stably performed regardless of a change in the power supply voltage VDD.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a block diagram of a conventional termination control circuit.

2 is a view for explaining the operation of the dynamic controller 140 of FIG.

3 is a view to help understand the WT_STARTP pulse signal of FIG.

4 is a view for explaining the operation of the normal control unit 130 of FIG.

FIG. 5 is a diagram for better understanding of the ODT_STARTP signal and the ODT_ENDP signal of FIG. 4. FIG.

6 is a configuration diagram of the dynamic controller 140 of FIG. 1.

FIG. 7 is a diagram illustrating a case where a malfunction of the termination control circuit occurs due to a decrease in the delay value of the delay unit 642 due to variations in the power supply voltage VDD.

8 is a block diagram of a termination control circuit according to the present invention.

9 is a diagram illustrating a dynamic termination operation controlled by a termination control circuit according to the present invention.

Claims (7)

A storage unit to store an external code in response to a write command; A first comparison unit configured to generate an activation signal of a dynamic termination operation by comparing the stored external code value with an internal code; An adder for adding a predetermined value to a value of the stored external code according to a burst length; And A second comparison unit which is activated by the activation signal and compares the value of the external code added by the adder with the internal code to generate a deactivation signal of a dynamic termination operation; Termination control circuit comprising a. The method of claim 1, The second comparison unit, And a termination control circuit in response to the deactivation signal. The method of claim 2, The first comparison unit, And is activated in response to the write command and inactivated in response to the activation signal. The method of claim 1, The termination control circuit, A counter unit for counting an external clock to output the external code, and counting an internal clock to output the internal code; And A controller configured to generate a dynamic termination control signal activated in response to the activation signal and deactivated in response to the deactivation signal. Termination control circuit further comprising. The method of claim 4, wherein And an initial value at which the external code and the internal code starts to count is determined according to a cas light latency (CWL). The method of claim 5, And a time point at which the outer code and the inner code start counting is different by a skew of the outer clock and the inner clock. The method of claim 1, The predetermined value is A termination control circuit, characterized in that (burst length / 2) +2.

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