KR100920402B1 - Low Temperature Gate Stack - Google Patents

Abstract

The present invention relates to a method of forming a dielectric layer on a substrate such as an integrated circuit. In one aspect of the present invention, an interface thin layer is formed (30). The interfacial layer is preferably an oxide layer and a high-k material is preferably deposited by a process that does not cause substantial growth of the interfacial layer. For example, water vapor can be used as the oxidant source during high dielectric constant deposition at temperatures below about 300 ° C.

Description

Low Temperature Gate Stack

The present invention relates to a method and apparatus for forming a dielectric stack in an integrated circuit, and more particularly to forming a thin oxide interfacial layer under a high-k material. It's about things.

In fabricating integrated circuits, thin dielectric layers are often located on semiconductor surfaces. Conventional gate dielectrics are formed of high quality silicon dioxide and are commonly referred to as "gate oxide" layers. These layers typically grow from single crystal silicon wafers or epitaxial silicon layers. The gate oxide capacitively couples the gate electrode and the channel region between the source and the gate region of a typical transistor.

As the integrated circuit becomes smaller, it is desirable to reduce the thickness of the gate oxide layer. However, gate oxide ultrathin layers (eg 5nm and below) have been shown to exhibit high defect density, including pinholes, charge trapping states, and susceptibility to hot carrier injection effects. lost. This high defect density leads to current leakage through the gate dielectric and rapid component breakdown, which is unacceptable in circuit designs using gate spacing smaller than 0.25 [mu] m, i.e. sub-quarter-micron technology.                 

 In laboratory conditions, the density of defects can be adjusted with care, but such adjustments are difficult to obtain at commercial scale manufacturing conditions. Moreover, even if the integrity of the oxide is maintained perfectly, the quantum-mechanical influence imposes a near limiting limitation on the scaling of the gate oxide. In high fields, direct tunneling overpowers Fowler-Nordheim tunneling and sets an alternative oxide scaling limit. These scaling limits were predicted to be about 2 nm for logic circuits and about 3 nm for memory arrays in dynamic random access memory (DRAM), which are more susceptible to leakage. See Hugh et al., "Thin Gate Oxide promise high Reliability," Semiconductor International (July 1998), pages 215-222.

Theoretically, introducing a material with a higher permittivity than silicon dioxide into the gate dielectric can take component scaling a step further. Due to the higher dielectric constant, these materials can exhibit the same capacity as the thinner silicon dioxide layer, resulting in an equivalent and thin oxide thickness without tunnel-limited behavior. Other advantages of high dielectric materials are diffusion barrier properties such as resistance to boron passage and high thermal conductivity.

The use of high dielectric constant oxides such as Al ₂ O ₃ and ZrO ₂ as gate dielectrics has been the focus of recent research. Deposition of thin films from high dielectric materials has been performed in a number of ways including chemical vapor deposition, reactive sputtering, molecular beam epitaxy, atomic layer deposition (ALD). ALD is a very promising method because it can adjust the film thickness and composition at the atomic level, resulting in uniform, highly conformal deposition.

ALD is a self-limiting process where alternating pulses of the reactant precursor are saturated on the substrate surface, leaving only one monolayer of material per pulse. The deposition conditions and precursors are chosen to ensure self-saturation reactions, and the adsorption layer in one pulse leaves a surface termination that does not react with the gaseous reactants in the same pulse. Subsequent pulses of other reactants react with the previous end to allow for subsequent deposition. As such, each cycle of alternating pulses leaves only about one molecular layer of the desired material. The principle of the ALD type process is described by Suuntola, for example Handbook of Crystal Grouse 3, Thin Film and Epitaxy, Part B: Groats Mechanism and Dynamics, Chapter 14, Atomic Layer Epitaxy, pages 601-63. Elsevier Science BV Disclosed in 1994 and incorporated herein by reference.

In a typical ALD process for depositing metal oxides, one cycle of deposition involves exposing the substrate to a metal precursor, removing unreacted first reactants and reaction byproducts from the reaction chamber, and exposing the substrate to an oxygen precursor. Followed by a second removal step. A major problem for depositing high dielectric constant metal oxides on silicon using ALD has been proposed that when exposed to an oxygen source early in the process, the silicon surface is covered only with a single layer of metal. Thus, under typical growth conditions, a silicon dioxide layer is formed. In each subsequent cycle, the silicon dioxide layer grows and tends to limit the capacity that can be obtained. There have been many answers to this potential problem. For example, it has been found that metal alkoxides can be used to deposit aluminum oxide on a silicon substrate without creating a silicon oxide interfacial layer. Here metal alkoxides act as both metal and oxygen sources in the reaction with other metal compounds (Ritara et al., Science 288: 319-321 (2000)).

However, it has been suggested that very thin silicon oxide interface layers also exist for alternating gate dielectric materials, because the ultrathin silicon oxide interface layers provide excellent silicon / oxide interface properties. to be. For example, Yang et al. (Samsung Electronics (1999)) found that the silicon oxide layer between the aluminum oxide and the silicon substrate produced a better gate dielectric than the aluminum oxide alone. Similarly, forming silicon nitride on a thin oxide layer has been found to lower defect density while significantly lowering the overall gate dielectric equivalent thickness. See, eg, Kim et al., "Ultra Thin (<3 nm) High Quality Nitride / Oxide Stack Gate Dielectrics Fabricated by In-Situ Rapid Thermal Processing," IEDM 97 (1997), pages 463-466. A method of depositing an oxide interfacial layer between a substrate and a high dielectric constant material is disclosed, for example, in US Pat. No. 6,144,060 and US patent application Ser. No. 09 / 471,761, filed December 23,1999.

Prior to thermally growing silicon oxide, the silicon surface is preferably cleaned to avoid contamination and to make good tourmaline properties. Among other materials, the surface is usually cleaned of naturally formed oxides known as 'native oxides'. As is well known, natural oxides naturally form on silicon surfaces even by exposure in clean rooms at room temperature.

Typically, native oxides are formed of silicon oxide of several angstroms and thus make up a significant portion of the dielectric film to be formed. Although thermal oxide grows through the native oxide to complete the desired dielectric layer, the quality and thickness of the native oxide is nonuniform across the silicon surface. Moreover, native oxides resulting from long distance transport and / or storage are usually contaminated with impurities.

Accordingly, native oxide is often removed from the surface through a dilute hydrofluoric acid bath or hydrofluoric acid vapor etching. Dipping the wafer in a dilute hydrofluoric acid bath cleans the native oxide and allows the surface to be hydrogen terminated. Fluorine vapor etching similarly cleans the silicon surface and results in a dangling silicon bond end, but the end of the surface contains a significant amount of fluorine.

Hydrogen terminations are not very stable, especially at high temperatures. Hydrogen atoms are likely to desorb and leave dangling silicon bonds that tend to attract pollutants in the atmosphere. Although the hydrogen and fluorine terminations are in place, oxidants in the atmosphere can still diffuse through the termination layer between fluorine treatment and subsequent processing. Thus, fluorine treatment cleans the wafer surface but does not adequately protect the surface for the period between cleaning and subsequent processing.                 

One way to maintain a clean silicon surface for longer periods of time is to quickly grow a thin layer of silicon after cleaning the silicon surface. As mentioned above, the ultrathin silicon dioxide layer can provide improved interfacial properties between the silicon structure and the high dielectric constant material. Spontaneous oxide regrowth, such as exposure to typical oxidants such as air or water at room temperature, is a very slow reaction, which is not acceptable in commercial manufacturing processes.

As is well known, heating the wafer during oxidation can increase the oxidation rate. Unfortunately, thermal oxidation at temperatures above 500 ° C. desorbs the hydrogen terminations left by fluorine treatment before the temperature reaches a level where significant oxidation occurs. In the meantime, the silicon surface is not protected. Moreover, the thermal oxidation of early silicon substrates is faster than the subsequent step in which the oxidant diffuses through the already grown silicon oxide, although its mechanism is unknown. Accordingly, in providing a suitable oxide thickness for interfacial enhancement under high dielectric constant materials, oxidation is not easily adjusted and easily exceeds the desired thickness. In addition, even though the oxide ultrathin layer is effectively formed as an interfacial layer, the oxide layer further grows under typical growth conditions in which a high dielectric constant material is deposited. Too thick a silicon oxide interface lowers the overall dielectric constant.

It is desirable to have an ultra thin SiO ₂ interface layer between the substrate and the high dielectric constant material, but the thickness of the silicon dioxide interface determines the minimum thickness of the gate oxide layer. Therefore, it is necessary to form and maintain the silicon dioxide ultrathin interface layer. Preferably, such a method should be compatible with single-wafer process systems and sub-micron technologies, and have a high yield and throughput compared to the prior art.

One aspect of the present invention is that an interfacial dielectric oxide layer is grown from the substrate by thermal oxidation, and the interfacial dielectric layer has a thickness of about 15 s during deposition of a high-k layer. Under conditions of increasing below, a method of forming a gate dielectric on a semiconductor substrate by depositing the high dielectric constant layer on top of the interfacial dielectric layer by an atomic layer deposition (ALD) process.

Another aspect is directed to a method of forming a dielectric layer on a silicon substrate. The method preferably comprises forming an interfacial dielectric layer comprising less than about 15 microns thick nitrogen on a substrate and an atomic layer deposition (ALD) type process without further growth of the interfacial dielectric layer. Depositing a high-k material directly on top of it. Preferably, the deposition comprises maintaining the substrate at a temperature below 300 ° C. and supplying water vapor as the oxidant. The step of depositing a high dielectric constant material grows the interfacial layer to less than 15 GPa, preferably less than 10 GPa, more preferably less than 5 GPa.

In one embodiment the deposition comprises an ALD process. The ALD process consists of a number of alternating cycles. Each cycle preferably comprises reacting the substrate with the first reactant; Removing unreacted first reactant and possible reaction byproducts from the reaction chamber; Contacting the substrate with water vapor; Removing unreacted water vapor and possible by-products from the reaction chamber.

1 shows a general process sequence for depositing an ultrathin interface of dielectric material between a substrate and a high dielectric constant material in the gate dielectric.

As described above, it is desirable to replace silicon dioxide in the gate dielectric with a material having a high dielectric constant or high dielectric constant, but an ultra thin oxide interfacial layer between the substrate and the high dielectric constant material. Is advantageously included. Thus, it is desirable to deposit high dielectric constant materials without increasing the thickness of the oxide ultrathin layer previously formed. Accordingly, the present invention provides a method of forming an oxide ultrathin interface layer between a substrate and a high dielectric constant material, wherein the thickness of the interfacial layer is maintained during deposition of the high dielectric constant material.

In a preferred embodiment, by using a metal oxide as the high dielectric constant material, the silicon dioxide interfacial layer does not grow during the deposition of the high dielectric constant material. Oxidation occurs only through the activity of the oxygen source used in the deposition process. The growth of the silicon dioxide layer is further controlled by controlling the activity of the oxygen source. High dielectric constant materials can be deposited by ALD. In one embodiment the temperature is preferably maintained below 300 ° C. and water vapor is used as the ligand exchange agent, thereby preventing oxidation by the oxygen source during deposition of the high dielectric constant material. In another embodiment, a metal compound, such as a metal organic compound, is used as the oxygen source material of the ALD reaction to prevent further growth of the interfacial layer. In another embodiment, metal oxides that are thermodynamically more stable than silicon dioxide can be deposited by MOCVD, thereby completely eliminating the use of an oxygen source.

1 shows a general process sequence according to the present invention. Preferably the substrate is first cleaned 10 to remove native oxides and contaminants. The surface is optionally deformed 20, to facilitate the formation 30 of the subsequent ultra thin interfacial dielectric. Following formation 30 of the ultrathin interfacial dielectric, the surface is a selective strain 40 to facilitate subsequent deposition of the high dielectric constant dielectric layer 50. Preferred methods are described in the examples below and do not require modification of the oxide layer surface prior to high dielectric constant material deposition.

Although the case of a silicon substrate is taken as an example, those skilled in the art will readily find that the principles disclosed herein can be applied to control film growth in many other cases. The term substrate refers to all of the surfaces on which a layer is deposited. For example, an oxide thin layer and a layer of high dielectric constant material may be formed on the metal surface. Preferred substrates are semiconductor structures, such as epitaxial silicon layers or tops of monolithic silicon wafers. In this case, one skilled in the art will understand that the semiconductor substrate is the lowest level semiconductor material in which the mechanisms in the integrated circuit are formed.

As shown, the substrate is cleaned 10 to remove contaminants on the semiconductor structure and naturally occurring oxides or native oxides. You may use any of a well-known method for cleaning a board | substrate. Conventionally, wafer cleaning prior to gate oxide growth has been performed ex situ before the wafer is mounted in the process chamber. For example, the wafer may be cleaned in a hydrochloric acid / fluoric acid wet etch bath. Alternatively, the cleaning can be done in situ. For example, integrated hydrofluoric acid and acetic acid vapor cleaning can be done in modules within the cluster tool, which reduces transfer time and reduces the possibility of recontamination or reoxidation. Alternatively, a hydrogen bake step can be performed in the chamber to sublimate the native oxide. Small amounts of hydrochloric acid vapor may be added to help clean metal contaminants and the like during hydrogen baking. In another embodiment, the plasma may assist or perform in situ cleaning, such as by replacing hydrogen gas with hydrogen radicals. Preferably using activated or excited species can widen the process temperature window for proper cleaning.

In a preferred embodiment, the substrate can be APM (ammonium hydroxide / peroxide mixture) cleaned. This may be followed by a hydrofluoric acid bath, which removes oxides from the APM cleaning and allows the substrate surface to be primarily hydrogen-terminated.

After cleaning (10) and optional surface treatment (20), an interfacial dielectric layer is formed (30) on the substrate. The interfacial dielectric layer is preferably an ultrathin layer consisting of one or two monolayers. The interfacial dielectric preferably has a thickness of 15 kPa or less, more preferably 10 kPa or less, and most preferably 5 kPa or less. Formation 30 of the dielectric oxide ultrathin interface layer can be done by known techniques. Accordingly, it may be grown from the substrate by oxidation, or may be deposited on the substrate by a process such as ALD or CVD. Preferably the interfacial dielectric grows from the substrate.

If the interfacial oxide formation 30 is made by oxidation, the substrate surface may be selectively treated 20 in a direction that mitigates subsequent oxidation of the substrate and consequent growth of the interfacial dielectric oxide layer. It is disclosed in Copening Application No. 09 / 791,167, filed February 22, 2001 and incorporated by reference. Dangling bonds to the silicon surface after cleaning tend to bond with groups or radicals present in the ambient atmosphere. After hydrofluoric acid treatment, the silicon dangling bonds become hydrogen atom termination or fluorine termination substantially completely. Hydrogen is the smallest atom present and fluorine is the smallest halide atom. They do not provide any meaningful barrier for the oxidant to diffuse to the silicon surface. However, the hydrogen and fluorine terminations can be replaced with larger group terminations. This partially obstructs the surface, and the diffusion of oxide towards the surface proceeds more slowly. This substantially slows down the rate of oxidation, especially during the early stages of growth, which are typically relatively fast.

By selecting the size of the ligand, the permeability of the diffusion barrier can be adjusted, the oxidation rate can be controlled, and the final oxide thickness can be adjusted. In addition, increasing the oxide thickness can contribute to the overall diffusion barrier, and oxidation processes tend to be self-limiting in oxide thickness.

In one embodiment, exposing the silicon surface to water vapor changes the hydrogen end of the dangling bond to the OH end. OH groups are considerably larger than hydrogen atoms and already have a strong relaxation effect on the rate of oxidation. In addition to the diffusion barrier provided by the ligand termination of the surface, other effects such as bond strength, polarity, etc. affect the rate of oxidation. As a result, only occupying dangling bonds by the ligand can and can also affect the rate of oxidation. According to one embodiment, the ligand is an OH group formed by exposure to water.

More preferably, the ligand is larger than the OH group and should further mitigate oxidation. For example, in another embodiment, the ligand comprises an alkoxy tail formed by exposing the hydrofluoric acid cleaned surface to alcohols such as methanol, ethanol, propanol or alkoxides. In another embodiment, the ligand comprises a carboxylic tail obtained by exposure to a carboxylic acid such as formic acid or acetic acid. In these more preferred embodiments, the ligand is provided before oxidation of the surface and after cleaning of the native oxide (preferably by fluorine treatment). Optionally, the ligand is also provided during the oxidation step.

In one embodiment, with or without the optional redox ligand described above, the interfacial dielectric is silicon oxide grown by exposure to species reactive with the cleaned substrate, such as thermal oxidation of the cleaned substrate. The oxidant source includes known oxidants, in particular volatile oxidants such as oxygen, water, HCOOH, HClO ₄ . The rate of oxidation can preferably be increased by providing an oxidant that is more reactive than oxygen and / or by raising the temperature of oxidation. Here, the oxidation temperature is preferably between 50 ° C and 400 ° C, more preferably 300 ° C and 400 ° C. Preferably the process temperature is maintained below about 400 ° C. during oxidation. For example, a silicon dioxide layer having a thickness of 5 m can be grown by exposing the substrate to ozone gas at 400 ° C. for 100 seconds.

In one embodiment, the oxidant has a stronger oxidation effect than oxygen or water vapor alone. Oxidation with an oxidant may be carried out at lower temperatures, preferably up to about 300 ° C, more preferably up to about 200 ° C. An example of a strong oxidant is a gas containing ozone, according to this embodiment. In another embodiment, the gas containing ozone is mixed with water vapor, oxygen or an inert gas such as nitrogen or rare gas. Another example of a powerful oxidant is a gas comprising peroxide. A source gas comprising oxygen may be provided to the remote plasma generator to provide excited species for oxidation.

In another embodiment, the oxidant is water vapor. At room temperature, the rate of oxidation in water vapor is very slow but the temperature can increase to about 300 ° C. Further, in this case, a ligand for increasing the oxidation rate may be provided on the silicon surface, or water vapor may be mixed with a gas for increasing the oxidation rate, such as a gas containing halogen such as oxygen or hydrochloric acid. Stronger oxidants such as ozone or peroxide may be provided during oxidation and / or elevated temperatures of about 400 ° C. may be used.

Growth of the interfacial dielectric may include, for example, nitrogen introduction (oxidation such as NO or N ₂ O or nitriding with NH ₃ ) to form an oxynitride interfacial dielectric, for example. In one embodiment, after cleaning, the interfacial dielectric is grown by introducing 1.5 slm of NO gas while maintaining a nitrogen gas 15 slm flow, assuming a pure NO oxidant gas. Those skilled in the art will appreciate that other oxidant gases (eg, oxygen, water, N ₂ O, HCOOH, HClO ₄ , nitroalkanes such as CH ₃ NO ₂ , alkyl nitrates such as (CH ₃ ) ₂ CHONO ₂ , mixtures, diluted oxidants It will be appreciated that the flow rate may be adjusted depending on the use of). Temperature and pressure are maintained at 780 ° C and 50 Torr, respectively, and are similar to the nitrogen flow chart. After about 20 seconds, silicon oxynitride grows from the substrate to a thickness of 0.5 nm. Nitrogen and / or oxygen radicals may be used for the growth of oxides, nitrides or oxynitrides. In a preferred embodiment the outermost layer of silicon oxide is nitrided with a nitride layer that resists subsequent oxide growth. Thus, the interfacial dielectric layer preferably comprises SiO _x , SiN _y , and SiO _x N _y .

After oxidation is complete, the supply of oxidant to the surface (including the ligand if supplied during the oxidation) is stopped and the substrate is purged with an inert gas. Since grown from the substrate, the interfacial dielectric layer is compatible with the semiconductor substrate and also serves to prevent interface charge trapping sites.

Following the formation of the interfacial dielectric layer, if used, the surface termination provided by the optional surface reaction 20 is removed. In one embodiment, the organic ligand is replaced with a -OH term.

The interfacial oxide layer can also be formed by other known methods. For example, it may be formed by controlled deposition rather than oxidation of the substrate. In one embodiment, the interfacial dielectric layer of silicon dioxide is deposited by atomic layer deposition (ALD). In another embodiment, the interfacial dielectric layer of silicon dioxide is grown by chemical oxidation of the substrate.

The formation of an interfacial dielectric layer, such as a silicon dioxide layer, having a controlled thickness and optional -OH termination, is followed by laminating the second dielectric thin layer while preventing further growth of the underlying interfacial dielectric layer. The underlying interfacial dielectric layer is preferably grown on average 10 kPa or less during deposition of the second dielectric layer, more preferably 5 kPa or less, most preferably not grown at all during deposition of the second dielectric layer. The layer deposited on top of the interfacial dielectric layer is preferably a high dielectric constant material. High dielectric constant materials have a higher dielectric constant than silicon oxide, preferably with a dielectric constant greater than 5, more preferably with a dielectric constant greater than 10. The high dielectric constant material deposited on the interfacial dielectric layer may be deposited without substantially growing the interfacial dielectric layer and may be any high dielectric constant material. As the high dielectric constant material, a metal oxide is preferable. Examples of high dielectric constant materials that can be used in the present invention are ZrO ₂ , HfO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , BST, ST, SBT, Nb ₂ O ₅ , La ₂ O ₃ , and Sc , Y, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu oxides, solid solutions of metal oxides and nanolaminates of metal oxides (nanolaminate).

Adjusting the thickness of the underlying interfacial dielectric layer to a single layer scale to achieve several monolayer target thicknesses is particularly useful for such high dielectric constant applications, which limits the capacity that the total thickness can achieve. This is because the change in thickness seriously affects the overall uniformity of the compound dielectric. The nonuniformity is too thick in some places, because the nonuniformity results in a thickness larger than the required oxide thickness, since a minimum thickness must be used to avoid leakage. Moreover, excessive gate dielectric changes ultimately reduce yield.

Accordingly, any deposition process that no longer grows the interfacial oxide layer can be used to form a high dielectric constant layer. For example, ALD, CVD, PVD, MOCVD, MBE or other known methods can also be used to deposit high dielectric constant materials as long as they maintain conditions where no further oxidation of the underlying layer occurs. Such a method is preferably performed at about 400 ° C. or lower, more preferably at about 300 ° C. or lower, most preferably at 200 ° C. or lower. The second layer allows for full scaling of the sheet dielectric due to the higher dielectric constant while contributing to the barrier properties and resistance to hot carrier effects.

Depending on the source chemical used, additional surface treatment is optionally provided prior to the deposition of the high dielectric constant material. For example, excited species treatment modifies the surface termination of the interfacial layer and enhances subsequent deposition.

In a preferred embodiment, the deposition of the high dielectric constant material is performed by an ALD type deposition process where alternating pulses of reactant saturate the surface, each cycle leaving only one monolayer of dielectric material. In short, the substrate undergoes an alternating surface reaction of the source chemical. Each cycle deposits and reacts or adsorbs to the layer on the substrate in a self-limiting manner. Preferably each cycle comprises at least two separate phases, where each phase is a saturation reaction with a self limiting effect. Under the preferred conditions, the amount of reactants selected is determined by the number of available sites and the physical size of the incidentally chemisorbed species (including ligands). The layer left by the pulse self-terminates with a surface that does not react with the residual chemicals of the pulse. After the self-limiting reaction is complete, unreacted source chemicals are removed from the reaction space and the substrate is exposed to the next reactant.

Maximum step coverage on the substrate surface is obtained when only about a single molecular layer of the source chemical molecule is chemisorbed at each pulse. Each subsequent pulse reacts with the surface left by the preceding pulse in a similar self-limiting or self-terminating manner. The series of pulses is repeated until the dielectric layer has grown to the desired thickness.

Water vapor is preferably used as the oxygen source, replacing the ligand termination of the previous pulse. This is because water vapor no longer substantially grows a thin interfacial oxide below 300 ° C. Oxide regrowth is particularly problematic during the early stages of high dielectric constant deposition, since oxidants can easily diffuse several monolayers of high dielectric constant materials and thin interfacial oxides. In the example below, a pulse of an aluminum source or a pulse of a zirconium source is alternately repeated with a water vapor pulse in the presence of an intervening purge pulse. In a preferred embodiment the second dielectric layer comprises trimethyl aluminum (TMA) and Al ₂ O ₃ deposited from water.

The temperature at which the high dielectric constant dielectric is deposited is preferably kept low enough so that the thickness of the interfacial dielectric layer does not increase. Therefore, the deposition of the high dielectric constant material is preferably carried out at about 400 ℃ or less. More preferably, deposition is performed between 70 ° C and 300 ° C, most preferably between 200 ° C and 300 ° C. In one embodiment, the temperature is lowered from the temperature at which thermal oxidation occurs during interfacial dielectric growth to about 300 ° C. or less during high dielectric constant dielectric deposition. The pressure in the process is preferably maintained between about 1 Torr and 80 Torr, more preferably about 10 Torr.

In one embodiment, the silicon wafer is introduced into the reaction space of a Pulsa 2000 reactor (commercially available from US ASM America), designed for ALD processing, either before or after growth of interfacial oxide. The reaction space is vacuumed with a mechanical vacuum pump. After vacuum, the pressure in the reaction space is adjusted to about 5 to 10 mbar (absolute value) and nitrogen gas of 99.9999% purity flows. The reaction space is then stabilized at temperatures lower than 300 ° C. Alternatingly repeated vaporized trimethylaluminum ((CH ₃ ) ₃ Al) and water vapors from an external source are introduced into the reaction space and react with the substrate surface. Source chemical pulses are separated from each other with flowing nitrogen gas.

Each pulse cycle consists of four basic steps.

* (CH ₃ ) ₃ Al pulse

Nitrogen purge

* Water pulse

Nitrogen purge                 

Examples of aluminum oxide deposition cycles are summarized in Table 1.

The number of cycles determines the thickness of the layer. The growth rate of Al ₂ O ₃ from (CH ₃ ) ₃ Al and water is typically close to 0.1 nm / cycle or 1 Pa / cycle, or about 3 to 4 cycles / single layer at 300 ° C. (Al ₂ O ₃ is about 3 Pa Has a bulk lattice parameter). The methyl termination left with each TMA pulse self-terminates the adsorption of each pulse and reduces possible chemisorption sites, with each pulse lacking monolayer formation. The pulse cycle is repeated sufficiently to form the desired layer thickness. Aluminum oxide acts as the only high dielectric constant material in the gate dielectric or as a barrier thin layer before forming one or more additional dielectric layers.

In another embodiment, ZrO ₂ is deposited by an ALD type process. ZrCl ₄ vapor is introduced into the reaction chamber and exposed to the wafer surface for 1.5 seconds. This is referred to as pulse A in Table 2 below. The reaction chamber is purged with nitrogen gas for 3 seconds to remove excess ZrCl ₄ and by-products from the reaction chamber. This is referred to as purge A. Water vapor is then introduced into the reaction chamber and exposed to the wafer surface for 3 seconds. This is referred to as pulse B. Residual water and reaction byproducts are removed by a reaction chamber purge for 4 seconds. This is referred to as purge B. During each reaction phase, the reactants are supplied in an amount sufficient to saturate the surface, taking into account other factors.

Examples of high dielectric constant deposition cycles are summarized in Table 2.

The average deposition rate is about 0.59 kW / cycle at 300 ° C. The cycle of Table 2 consists of pulse A, purge A, pulse B, and purge B, and is repeated as many times as necessary to form a layer of desired thickness.

More generally, the temperature in the process is preferably between about 200 ° C and 300 ° C. For the amorphous ZrO ₂ layer, the temperature is preferably between 200 ° C and 250 ° C, most preferably about 225 ° C. For the crystal film, the temperature is preferably higher in this range, that is, between 250 ° C and 300 ° C, most preferably about 300 ° C. Those skilled in the art will appreciate that mixtures of amorphous and crystalline compositions are within the range of these two regions. The illustrated process forms mostly crystalline ZrO ₂ films.

In the above example, the metal monolayer formed by each ZrCl ₄ pulse self-terminates with chlorine, which does not readily react with excess ZrCl ₄ under preferred conditions. Preferred oxygen source gases react with or adsorb on the chlorine-terminated surface during the oxygen phase in the ligand exchange reaction. Ligand exchange reactions here are limited by the feed of previously adsorbed zirconium chloride complexes. Furthermore, the oxidation leaves hydroxyl and oxygen bridge terminations that no longer react with excess oxidant in the saturated phase.

Preferably enough cycles are performed to grow ZrO ₂ between about 20 kPa and 60 kPa. More preferably 20 kPa is grown to between 40 kPa and more preferably about 30 kPa. The dielectric constant of the layer is between about 18 and 24.

Following high dielectric constant dielectric deposition, the deposited dielectric layer is optionally annealed to improve the quality of this layer. For example, the deposited dielectric layer undergoes high temperature oxygen annealing, thereby crystallizing the layer and filling oxygen vacancies that would have been metal leakage paths. The annealing step is preferably done in situ in a reactor designed to minimize the risk of explosion or the risk of undesired reactions between a series of reactants. Preferably the annealing is carried out under conditions which prevent further growth of the interfacial oxide layer.

An ALD process using two metal compounds can be used to deposit a high dielectric constant layer, where one of the two metal compounds is an oxygen source material that reacts well with the other metal compound but does not oxidize the substrate. This process is disclosed in US patent application Ser. No. 09 / 687,355, filed Oct. 13, 2000, which is incorporated herein by reference. In this method, the surface of the substrate reacts alternately with the metal source material and the oxygen source material. However, the oxygen source material preferably has at least one organic ligand and oxygen is a metal alkoxide, metal compound bonded with at least one boron, silicon or metal atom. Metal alkoxides act as both oxygen and metal sources when reacted with a second metal compound, such as a metal halide or metal alkyl. In this process, the high dielectric constant metal oxide can be deposited without further oxidation of the underlying substrate and thus no further growth in the interfacial oxide layer.

High dielectric constant materials can be deposited by direct decomposition of the metal precursor without oxygen. These metal precursors preferably comprise both metal and oxygen and thus can form metal oxides without additional oxygen. In this case, the absence of an oxidant prevents further growth of the interfacial oxide layer. Preferred metal precursors are organometallic compounds. And also they may be volatile anhydrous metal nitrides.

Additionally, high dielectric constant materials can be deposited by metalorganic chemical vapor deposition (MOCVD). In such MOCVD processes, the oxidant used does not substantially grow the interfacial oxide layer at the temperature at which the process is performed.

After dielectric deposition, the formation of a transistor gate electrode over the dielectric stack is followed. Electrode formation is also advantageously done in situ. Accordingly, not only the dielectric stack is formed in situ, but the reactor and method in the preferred embodiment enable all steps of transistor gate stack formation to be in situ. Accordingly, interfacial dielectric growth and second high dielectric constant dielectric deposition can be performed in situ. Alternatively, some or all of the wafer cleaning, deposition of the dielectric layer, annealing, and electrode formation may be performed in situ, which is performed in the same process chamber or cluster tool without exposure to the atmosphere between steps.

Although the foregoing invention has been described as specific preferred embodiments, other embodiments will be apparent to those skilled in the art. For example, if a process for forming a gate dielectric in an integrated circuit is clearly provided, those skilled in the art will appreciate that the same principle can be applied in other cases, such as forming a high dielectric constant on a silicon bottom electrode for a capacitor. . In addition, other combinations, omissions, substitutions and variations will be apparent in light of the aspects disclosed herein. Accordingly, the invention is not limited to the description of the preferred embodiment, but is defined by reference to the appended claims.

The present invention is used in methods and apparatus for forming dielectric stacks in integrated circuits.

Claims (48)

In the method of forming a gate dielectric on a semiconductor substrate, Growing an interfacial dielectric oxynitride layer from the substrate by thermal oxidation; And Depositing a high-k layer, under conditions such that the thickness of the interfacial dielectric oxynitride layer increases to less than about 15 GPa during deposition of the high dielectric constant layer. And depositing the high dielectric constant layer on top of the interfacial dielectric oxynitride layer by an ALD process, The atomic layer deposition process includes a plurality of cycles, each cycle, Contacting the substrate with the first reactant in the reaction chamber; Removing the unreacted first reactant from the reaction chamber; Contacting the substrate with water vapor; And Removing unreacted water vapor from the reaction chamber, Wherein the water vapor is the only oxygen source used during the deposition of the high dielectric constant layer. The method of claim 1, And the temperature at which the high dielectric constant layer is deposited is 300 ° C. or less. delete The method of claim 1, And wherein said interfacial dielectric oxynitride layer is less than about 15 microns thick. The method of claim 4, wherein And wherein said interfacial dielectric oxynitride layer is less than about 10 microns thick. The method of claim 5, And wherein the interfacial dielectric oxynitride layer is less than about 5 GPa thick. The method of claim 1, Wherein said interfacial dielectric oxynitride layer is SiO ₂ N _y . delete The method of claim 1, The thermal oxidation comprises oxidation through oxidation-moderating surface termination. delete delete delete delete The method of claim 1, And wherein said high dielectric constant layer comprises Al ₂ O ₃ . The method of claim 14, The first reactant is trimethyl aluminum (TMA), characterized in that. The method of claim 1, Wherein said high dielectric constant layer comprises ZrO ₂ . The method of claim 16, Wherein the first reactant is ZrCl ₄ . In the method of forming a compound dielectric layer on the surface of the substrate, Forming an interfacial dielectric layer comprising less than about 15 microns thick nitrogen; And And depositing a high-k material directly on top of the interfacial dielectric layer by an atomic layer deposition (ALD) type process without further growth of the interfacial dielectric layer. Wherein the atomic layer deposition process comprises exposing the substrate sequentially and alternately to a first reactant comprising a metal source material and an oxygen source material. The method of claim 18, And wherein said interfacial dielectric layer is less than about 10 microns in thickness. The method of claim 19, And wherein said interfacial dielectric layer is less than about 5 microns thick. The method of claim 18, Cleaning the substrate prior to forming the interfacial dielectric layer. The method of claim 18, Wherein said substrate is a silicon substrate. The method of claim 22, And the interfacial dielectric layer is formed by thermally oxidizing the silicon substrate using an oxidant selected from the group consisting of NO and N ₂ O. delete The method of claim 18, The oxygen source material is a metal organic compound. The method of claim 18, Said metal source material is a metal halide and said oxygen source material is a metal alkoxide. The method of claim 18, The metal source material and the oxygen source material are both metal alkoxides. The method of claim 18, The high dielectric constant material is selected from the group consisting of ZrO ₂ , HfO ₂ , Ta ₂ O ₅ , TiO ₂ , BST, ST, SBT, Al ₂ O ₃ , Nb ₂ O ₅ , La ₂ O ₃ Way. The method of claim 18, The oxygen source material is water, and wherein the water is the only oxygen source used during the deposition of the high dielectric constant layer. The method of claim 18, Wherein the temperature of the substrate is less than 300 ° C. while deposition is performed. In the method of forming a gate dielectric on a semiconductor substrate, Growing an interfacial dielectric oxide layer from the substrate by thermal oxidation; And Depositing a high-k layer, under conditions such that the thickness of the interfacial dielectric layer increases to less than about 15 GPa during deposition of the high-k constant layer, atomic layer deposition (ALD) Depositing the high dielectric constant layer on top of the interfacial dielectric layer by a process; The high dielectric constant material is deposited by direct decomposition of a metal source compound. delete delete The method of claim 18, And the oxygen source material comprises water in the form of water vapor. The method of claim 18, Wherein said interfacial dielectric layer is selected from the group consisting of SiN _y and SiO _x N _y . delete The method of claim 18, And modifying surface termination on the interfacial dielectric layer prior to deposition of the high dielectric constant material. In the method of forming a dielectric layer on a silicon substrate, Growing a silicon oxynitride interface layer having a thickness of less than about 15 GPa on the substrate; Depositing a high-k material on top of the silicon oxynitride interfacial layer, The depositing includes maintaining the substrate below about 300 ° C. and supplying water vapor as an oxidant, The silicon oxynitride interfacial layer grows to less than about 15 GPa during deposition of the high dielectric constant material, Wherein the water vapor is the only oxidant supplied during deposition of the high dielectric constant material. The method of claim 38, The deposition comprising an atomic layer deposition (ALD) process. The method of claim 39, The atomic layer deposition process includes a plurality of cycles, each cycle, Contacting the substrate with a first reactant; Removing the unreacted first reactant from the reaction chamber; Contacting the substrate with water vapor; And Removing the unreacted water vapor from the reaction chamber. delete The method of claim 38, And the silicon oxynitride interfacial layer grows to less than about 10 GPa during deposition of the high dielectric constant material. The method of claim 42, wherein Wherein said silicon oxynitride interfacial layer grows to less than about 5 GPa during deposition of said high dielectric constant material. The method of claim 1, Wherein the thickness of the interfacial dielectric oxynitride layer increases to less than about 10 GPa during deposition of the high dielectric constant material. The method of claim 1, Wherein the thickness of the interfacial dielectric oxynitride layer increases to less than about 5 GPa during deposition of the high dielectric constant material. The method of claim 1, The thermal oxidation comprises exposing the substrate to an oxidant selected from the group consisting of NO and N ₂ O. The method of claim 38, The silicon oxynitride interface layer is formed by oxidizing the silicon substrate using an oxidant selected from the group consisting of NO and N ₂ O. The method of claim 31, wherein Wherein said single metal source compound is the only reactant used to deposit said high dielectric constant layer.

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