KR100919566B1 - Operating method of phase change memory device - Google Patents

Abstract

The present invention provides a method of operating a phase change memory device, wherein the temperature of the phase change resistor cell is prevented from rapidly rising under the operating conditions for writing the reset data in the write operation mode to prevent stress caused by the volume change of the phase change layer. It is a technology that can be reduced. To this end, the present invention applies a write voltage to the cell for a first time when writing the first data to the selected cell in the write operation mode, and a second time longer than the first time when writing the second data. It is characterized in that for applying to the cell.

Description

Operation method of phase change memory device {OPERATING METHOD OF PHASE CHANGE MEMORY DEVICE}

The present invention relates to a method of operating a phase change memory device, and in particular, to prevent a phenomenon in which a temperature of a phase change resistor cell rises rapidly in an operating condition for writing a reset day in a write operation mode, by a volume change of a phase change layer. It is a technique that can reduce stress.

In general, nonvolatile memories such as magnetic memory and phase change memory (PCM) have data processing speeds of about volatile random access memory (RAM), and preserve data even when the power is turned off. Has the property of being.

1A and 1B are diagrams for describing a conventional phase change resistor (PCR) device.

The phase change resistance element 4 inserts a phase change material (PCM) 2 between the upper electrode 1 and the lower electrode 3 to apply a voltage and a current to the phase change layer 2. The high temperature is induced to change the state of electrical conduction due to the change in resistance.

Here, AglnSbTe is mainly used as the material of the phase change layer 2. As a material of the phase change layer 2, a chalcogenide (Chalcogenide) mainly composed of chalcogen elements (S, Se, Te) may be used. The material (Ge2Sb2Te5) is used.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

As shown in FIG. 2A, when a low current below a threshold flows through the phase change resistance element 4, the phase change layer 2 is at a temperature suitable for crystallization. As a result, the phase change layer 2 becomes a crystalline phase and becomes a material of a low resistance state.

On the other hand, as shown in FIG. 2B, when a high current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change layer 2 becomes higher than the melting point. As a result, the phase change layer 2 is in an amorphous state and becomes a material of a high resistance state.

As described above, the phase change resistive element 4 can non-volatilely store data corresponding to the states of the two resistors. That is, when the phase change resistance element 4 is in the low resistance state, the data is "1", and in the high resistance state is the data "0", the logic state of the two data can be stored.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

When a current flows between the upper electrode 1 and the lower electrode 3 of the phase change resistance element 4 for a predetermined time, high heat is generated. Thereby, the state of the phase change layer 2 changes into a crystalline phase and an amorphous phase by the temperature state applied to the upper electrode 1 and the lower electrode 3.

At this time, when a low current flows for a predetermined time, a crystal phase is formed by a low temperature heating state, and the phase change resistance element 4, which is a low resistance element, is set. On the contrary, when a high current flows for a predetermined time, an amorphous phase is formed by a high temperature heating state, and the phase change resistance element 4, which is a high resistance element, is reset. Thus, these two phase differences are represented by electrical resistance change.

Accordingly, the low voltage V1 is applied to the phase change resistance element 4 for a long time to write the set SET state in the write operation mode. On the other hand, the high voltage V2 is applied to the phase change resistance element 4 for a short time to write the reset state in the write operation mode.

4 is a diagram illustrating a write voltage and a lead resistance region of a conventional phase change resistance cell.

In the write operation mode, a low voltage is applied to the phase change resistive element 4 for a long time to write the set data, and a high voltage is applied to the phase change resistive element 4 for a short time to write the reset data.

On the other hand, in the read operation mode, a current is applied to the phase change resistance element 4 to measure the resistance of the phase change layer 2, and the set resistance and the reset data are determined by comparing the measured resistance with the reference resistance.

At this time, the resistance of the phase change layer 2 depends on whether the state of the phase change layer 2 is crystalline or amorphous. That is, if the state of the phase change layer 2 is crystalline, it has low resistance, and if it is amorphous, it has high resistance.

However, since the state of the phase change layer 2 changes in accordance with the time for applying the voltage to the phase change resistance element 4 in the light operation mode, the resistance characteristic of the phase change resistance element 4 applies the write voltage. It can be distinguished by the long and short of time.

Therefore, the set state of the phase change resistance element 4 corresponds to the region (A) with low write voltage and read resistance, and the reset state corresponds to (B) region with high write voltage and read resistance.

5 is a view for explaining the write operation characteristics of a conventional phase change resistance cell.

In order to write the set state in the write operation mode, a low voltage of type A is applied to the phase change resistance element 4 for a long time. In the set state, since the state of the phase change layer 2 is a crystalline phase, the resistance of the phase change layer 2 in the read operation mode is measured to be lower than the reference resistance.

On the other hand, in order to write the reset state, a high voltage of type C is applied to the phase change resistance element 4 for a short time. In the reset state, since the state of the phase change layer 2 is amorphous, the resistance of the phase change layer 2 is measured higher than the reference resistance in the read operation mode.

Therefore, when writing reset data in the conventional phase change memory device, the rate of temperature rise of the phase change layer 2 becomes large. For this reason, there is a problem in that the stress is large while the volume of the phase change layer 2 suddenly changes.

The present invention can reduce the stress caused by the volume change of the phase change layer by preventing a phenomenon in which the temperature of the phase change resistance cell rises rapidly in the operating conditions for writing the reset data in the write operation mode.

A method of operating a phase change memory device including a phase change resistance element that senses a crystallization state that changes according to a magnitude of a current and stores data corresponding to a change in resistance, the method comprising: When writing one data, the write voltage is applied to the cell for a first time, and when writing the second data, the write voltage is applied to the cell for a second time longer than the first time.

According to the present invention, the temperature of the phase change resistance cell may be prevented from rising rapidly in the operating conditions for writing the reset data in the write operation mode, thereby reducing the stress caused by the volume change of the phase change layer and improving the reliability of the device. Provide the effect.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1A and 1B are diagrams for explaining a conventional phase change resistor (PCR) element.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

3 is a view for explaining a write operation of a conventional phase change resistance cell.

4 shows the write voltage and lead resistance area for a conventional phase change resistance cell.

5 is a diagram for explaining the write operation characteristics of a conventional phase change resistance cell.

6 is a block diagram of a cell array of a phase change memory device according to the present invention;

7 is a view for explaining a method of operating a phase change memory device according to the present invention;

8 is a view for explaining the relationship between the write time and the temperature according to the operating method of the present invention.

9 shows the write voltage and lead resistance region for the phase change resistance cell of the present invention.

10 is a view for explaining the light operation characteristics according to the present invention;

11 is a view for explaining the effect of the operation method of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

6 is a configuration diagram illustrating a cell array of a phase change memory device according to the present invention.

In the cell array of the present invention, a plurality of bit lines BL0 to BL3 are arranged in a column direction, and a plurality of word lines WL0 to WL3 are arranged in a row direction. The cell array includes a unit phase change resistance cell C disposed in a region where a plurality of bit lines BL0 to BL3 and a plurality of word lines WL0 to WL3 cross each other. Here, the unit phase change resistance cell C includes a phase change resistance element PCR and a PN diode D.

One side of the phase conversion resistance element PCR is connected to the word line WL, and the other side is connected to the N-type region of the PN diode. The P-type region of the PN diode D is connected to the bit line BL, and the N-type region is connected to the word line WL. The phase of the phase change resistance element PCR is changed in accordance with the set current Iset and the reset current Ireset flowing in each bit line BL to write data.

The sense amplifier S / A senses cell data applied through the bit line BL and distinguishes the set data from the reset data by comparing with the reference voltage ref. The reference current Iref flows through the reference voltage ref applying terminal. When the data write unit W / D writes data to the unit phase change resistance cell C, the write driver W / D supplies the write voltage corresponding to the data state to the bit line BL.

7 is a view for explaining a method of operating a phase change memory device according to the present invention.

When the data to be written in the write operation mode is set data, the write voltage V3 having a specific level is applied to the selected unit phase change resistance cell C through the write driver W / D during the first write time t1. At this time, the write voltage V3 is a pulse voltage and has a voltage level V1 < V3 < V2 between the conventional write voltage V1 and the reset voltage V2. The first write time t1 is a time required for the phase change resistance element PCR to be in a crystal state.

That is, while the write voltage V3 is applied for a short time, the temperature of the phase change resistance element PCR becomes maximum at low temperature, and then gradually decreases. As a result, the set data is written while the phase change resistance element PCR is in a crystalline state.

On the other hand, when the data to be written is reset data, the write voltage V3 is applied to the selected unit phase change resistance cell C through the write driver W / D for the second write time t2. At this time, the second write time t2 is longer than the first write time t1 and is a time required for the phase change resistance element PCR to be in an amorphous state.

That is, as the write voltage V3 is applied for a long time, the temperature of the phase change resistance element PCR continues to rise to its maximum at a high temperature, and then gradually decreases. As a result, the reset data is written while the phase change resistance element PCR is in an amorphous state. In the above-described embodiment, the time t1 required for the phase change resistance element PCR to be in the crystalline state and the time t2 required for the phase change resistance element PCR to be in the crystalline state are determined by the material used when the actual PCR is manufactured or the size of the PCR. It may vary depending on physical conditions. Therefore, those skilled in the art will be able to easily know this, so the time is not specifically limited herein.

8 is a view for explaining the write time and the temperature relationship according to the operating method of the present invention.

The resistance characteristics of the phase change resistance element PCR are distinguished by the long and short write times. That is, even when the write voltage V3 having the same level is applied to the phase change resistance element PCR, the set data and the reset data can be written by adjusting the write time.

In other words, the phase change resistance element PCR is in a crystalline state at a temperature below the melting point based on the melting point of the phase change resistance element PCR, and in an amorphous state at a temperature above the melting point. Therefore, if the write voltage V3 is applied only for a time until the temperature of the phase change resistance element PCR reaches a temperature below the melting point, the set state can be written to the phase change resistance element PCR. Similarly, when the write voltage V3 is applied for a time until the temperature of the phase conversion resistance element PCR reaches a temperature above the melting point, the reset state can be written to the phase change resistance element PCR.

9 is a diagram illustrating a write voltage and a lead resistance region of the phase change resistance cell of the present invention.

In the write operation mode, a medium level voltage is applied to the phase change resistance element PCR for a short time to write the set data, and a medium level voltage is applied to the phase change resistance element PCR for a long time to write the reset data.

Then, in the read operation mode, a current is applied to the phase change resistance element PCR to measure the resistance of the phase change layer, and the set resistance and the reset data are determined by comparing the measured resistance with the reference resistance. At this time, if the state of the phase change layer is a crystalline phase, it has a low resistance, and if it is amorphous, it has a high resistance.

Therefore, the set (SET) state of the phase change resistance element PCR corresponds to the region of the write voltage of the middle level and the (C) region of the low read resistance, and the RESET state corresponds to the write voltage of the same level as the set (SET) state. It corresponds to the area (D) of high lead resistance.

10 is a view for explaining the light operation characteristics according to the present invention.

In order to write the SET state in the write operation mode, a medium type voltage of type B is applied to the phase change resistance element PCR for a short time. In the SET state, the resistance of the phase change layer is measured to be lower than the reference resistance in the read operation mode because the state of the phase change layer is crystalline.

On the other hand, in order to write the RESET state, a medium level voltage of the same type B as the SET state is applied to the phase change resistance element PCR for a long time. In this RESET state, since the state of the phase change layer is amorphous, the resistance of the phase change layer is measured to be higher than the reference resistance in the read operation mode.

11 is a view for explaining the effect of the operation method of the present invention.

The present invention uses a voltage having an intermediate level between the reset write voltage and the set write voltage in the write operation mode. When the reset data is written, the voltage is applied for a long time, and when the set data is written, the voltage is applied for the short time.

Accordingly, in the conventional case, when the reset data is written, the temperature of the phase change resistance element PCR rapidly rises, whereas the temperature of the phase change resistance element PCR increases slowly. For this reason, the volume change of the phase change layer of the phase change resistance element PCR is small, and stress can be reduced compared with the conventional.

Claims (5)

A method of operating a phase change memory device including a phase change resistance element configured to store a data corresponding to a change in resistance by sensing a crystallization state that changes according to a magnitude of a current, In the write operation mode, when the set data is written to the selected cell, a write voltage is applied to the cell for a first time, and when the reset data is written, a write voltage having the same magnitude as that of the set data is longer than the first time. And applying to the cell for a second time period. The method of claim 1, wherein the first data is set data. The method of claim 1, wherein the second data is reset data. The method of claim 1, wherein the first time is a time until the phase change resistance element rises to a temperature below the melting point. The method of claim 1, wherein the second time is a time until the phase change resistance element rises to a temperature above the melting point.