KR100916215B1 - Protocol memory, memory module, protocl memory system and method for controlling thereof - Google Patents

Abstract

A protocol memory system for transmitting and receiving packet data is disclosed. A memory system according to the present invention includes a host generating one command packet including a primary command and a secondary command, and a memory module coupled to the host. The memory module mounts a primary memory device and a secondary memory device on a module substrate. The primary memory device receives a command packet provided from the host, transmits and receives data with the host in response to the primary command included in the command packet, and relays the secondary command including the secondary command in response to the secondary command included in the command packet. Relay a command packet. The secondary memory device receives the relay command packet relayed from the primary memory device, and transmits and receives data to and from the host through the primary memory device in response to the secondary command included in the received relay command packet. Accordingly, by controlling the sub-protocol memory device simultaneously with accessing the protocol memory device, the throughput of data and the concurrency can be greatly increased.

Description

Protocol memory, memory modules and protocol memory systems and control methods thereof. {PROTOCOL MEMORY, MEMORY MODULE, PROTOCL MEMORY SYSTEM AND METHOD FOR CONTROLLING THEREOF}

1 is a view showing the configuration of a memory system according to an embodiment of the present invention.

2A to 2C are side cross-sectional views illustrating various mounting states of a memory module of a second rank system according to the present invention.

Figure 3 is a block diagram of one preferred embodiment of a protocol memory device according to the present invention.

4 is a diagram showing the configuration of the downloading and uploading packet data of the offset method according to the present invention.

5 and 6 are diagrams showing the configuration of packets according to the present invention, respectively.

7 and 8 are diagrams showing the truth table of the functions of the command packet according to the present invention.

9 is a view for explaining the operation of the second rank memory system according to the present invention.

10 is a timing diagram of a read operation of the second rank memory system according to the present invention.

11 to 14 illustrate a configuration of a command and an address packet according to the read operation of FIG. 10.

15 is a write operation timing diagram of the second rank memory system according to the present invention.

The present invention relates to a high speed, high capacity memory system, and more particularly to a protocol memory system for sending and receiving packets between a host and a memory module.

In a computer system, a memory system typically includes a host including a memory controller and a memory module connected to the memory controller.

In order to increase the memory capacity of the memory system, the number of memory modules is increased or a memory chip mounted in the memory module is configured as a high capacity memory chip.

Increasing the number of memory modules results in a multi-drop bus structure in which data buses of memory modules are commonly connected. In the multi-drop bus structure, since a plurality of memory modules are commonly connected to one bus, a load is increased and a data transfer rate is lowered. Thus, the number of DRAMs connected to the bus is limited by a given operating speed, up to eight in SDRAM, four in DDR, and two in DDR2 / 3.

However, in a situation where the trend of computer systems to speed up cannot allow such a structure in which multiple DRAMs are connected to the controller, for example, the connection between the controller and the DRAM may be 1: 1 in 2 Gbps or more (PTP: point-to-point). There is only a point). This is true of the data bus, but the command and address buses are no exception.

The biggest problem in the PTP structure is that when a large number of memory devices are mounted in one memory module for increasing the capacity of the memory, the pin count of the memory module for connecting the memory controller and the memory module increases.

In order to overcome this problem, researches for constructing a transmission signal between a memory controller and memory devices in the form of a packet have been conducted.

SUMMARY OF THE INVENTION An object of the present invention is to provide a protocol memory device capable of receiving one packet including a plurality of commands and relaying some of the commands in order to solve the problems of the prior art.

Another object of the present invention is to provide a memory module comprising cascaded protocol memory elements.

It is still another object of the present invention to provide a memory system capable of increasing transmission capacity and increasing parallel processing capacity by providing each command of a plurality of cascaded memory elements in one packet and relaying the same between the memory elements; It is to provide a control method.

In order to achieve the above object, the protocol memory device of the present invention receives a first packet, a second port, a memory core for storing data, and a command packet provided from a host through the first port. A primary command and a secondary command, the primary command controls the memory data transmission and reception between the memory core and the host, and a relay command packet including the secondary command is transferred through the second port to another protocol memory device. It is characterized by including a link processing unit for relaying. In the present invention, the relay command packet is defined as a command packet relayed between the memory device and the memory device.

In the present invention, the link processing unit receives a data packet provided from another protocol memory device through the second port, and relays the received data packet to the host through the first port. The link processing unit relays the relay command packet in response to the relay instruction information included in the secondary command. If the relay instruction information is "0", the relay operation is not performed. If the relay instruction information is "1", the relay operation is preferably performed.

A memory system according to the present invention includes a host generating one command packet including a primary command and a secondary command, and a memory module coupled to the host. The memory module mounts a primary memory device and a secondary memory device on a module substrate. The primary memory device receives a command packet provided from the host, transmits and receives data with the host in response to the primary command included in the command packet, and relays the secondary command including the secondary command in response to the secondary command included in the command packet. Relay a command packet. The secondary memory device receives the relay command packet relayed from the primary memory device, and transmits and receives data to and from the host through the primary memory device in response to the secondary command included in the received relay command packet.

The host, that is, the memory controller, includes a recording medium capable of mechanical reading, and program code stored in the recording medium and capable of mechanical reading. The program code includes instructions for generating a primary command for operation of the primary memory device, generating a secondary command for operation of the secondary memory device, and generating one command packet including the primary command and the secondary command. do.

In the method of controlling dependently coupled memory devices of the present invention, a relay including a secondary command while receiving a command packet including a primary command and a secondary command in a first memory device, and performing a primary command of the received command packet The command packet is relayed to the second memory element. The relay command packet relayed from the first memory element is received by the second memory element, and the secondary command of the relay command packet received from the second memory element is performed.

The host and each of the plurality of primary protocol memories are directly connected through an n-bit downloading bus and an n-bit uploading bus. send command and address packets, or command and address packets, and write data packets from the host to the primary protocol memory device via the n bit downloading bus, and read data packets from the primary protocol memory device to the host via the n bit uploading bus. Send it. The primary protocol memory and the secondary protocol memory are directly connected through an n-bit downloading relay bus and an n-bit uploading relay bus. Send a command and address packet, or a command and address packet and a write data packet from a primary protocol memory device to a secondary protocol memory device via an n bit downloading relay bus, and from the secondary protocol memory device through an n bit uploading relay bus. The read data packet is transmitted to the primary protocol memory device.

The primary protocol memory relays data transmission and reception between the secondary protocol memory and the host at the same time as the read or write operation.

The primary protocol memory controls data transmission and reception between a first port, a second port, a memory core for storing data, and a host and a memory core connected through the first port, and at the same time, the other port connected with the second port. And a link processor for relaying data transmission and reception between the protocol memory device and the host.

In the present invention, the memory core is preferably composed of a DDR2 / 3 DRAM core.

The first port includes a download bus for downloading a download packet including command and address data and write data from the host, and an upload bus for uploading an upload packet including read data to the host.

In the present invention, the data line widths of the download bus and the upload bus are each m lines, and the download packet and the upload packet are each composed of parallel m-bit data provided q consecutive times during one clock period of the memory core. desirable. The downloading packet includes a command and address packet or a command address packet and a write data packet. The command and address packet includes main command and address information for controlling the memory core, and subcommand and address information relayed to the secondary protocol memory device connected through the second port.

The second port includes a downloading relay bus for downloading a download packet including command and address data and write data to the secondary protocol memory device, and an upload for uploading an upload packet including read data from the secondary protocol memory device. It includes a loading relay bus.

In the present invention, a smart state is a state in which a memory device is performing a task given by a certain logic smoothly, and a deliberate state is a state in which only a limited task is manually performed, and a dead state is a state in which a task is hardly performed. do.

The packet of the present invention may be provided in two forms. One is when the number of ranks is smaller than the number of commands and address groups of each rank that can be sent together in the command and address packets, and one is when the number of ranks is large. For example, when the number of bits and the number of command and address bits of each rank is allocated to 30 bits when the number of packet bits is 80 bits, the multiplexing method that includes both the command and address information of each rank may be included in one packet and sent together. Use However, in the case of 4 banks and 8 banks, limited background operation information using an offset method is used because it is not possible to carry all rank commands and addresses in one packet.

The operating method of the protocol memory system of the present invention receives packet data including respective commands for a plurality of ranks cascaded to a host, performs a command of a main rank directly connected to the host, and a sub connected to the main rank. Relaying a packet containing a rank command. The method may further include performing a command of the sub rank, and relaying the data packet transferred from the sub rank to the main rank to the host.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. This embodiment is described in sufficient detail to enable those skilled in the art to practice the invention.

<Example>

1 shows a configuration of a memory system according to an embodiment of the present invention.

Referring to the drawing, the memory system includes a host 100 and a memory module 200. The host 100 in the broad sense refers to a main board on which a memory module socket into which a memory module is inserted is mounted. In a narrow sense, it refers to a chip that directly communicates with a memory module, such as a memory controller chipset or a north bridge chipset.

The host 100 is connected to the memory module 200 through four channels CH0 to CH3. Each channel consists of an n-bit download bus (DLB) and an n-bit upload bus (ULB). The host 200 provides a plurality of reference clock signals FCLK to the memory module 200.

The n bit down downloading bus is formed in a differential input / output line structure and includes m bit packet data lines, a write clock line, and p power supply voltage lines. The n bit upload bus is likewise formed with a differential input / output line structure and includes m bit packet data lines, read clock lines, and p power supply voltage lines.

Therefore, since the pin number for connecting the host 100 and the memory module 200 is a differential input / output line structure, at least 2m (data line pairs) + 2 (clock line pair) + 2p (power line pairs) for each bus. ) Is required. Here, if m = 8 and p = 7, 64 (= 32 (up loading bus) +32 (down loading bus)) pins per channel are required, so the number of pins of the four-channel memory module is approximately 260 pins, including the other reference clock pins. To 280 pins. Therefore, the memory module of the present invention can be configured without a significant difference from the number of pins of the conventional DDR2 / 3 memory module.

In the present embodiment, the memory module 200 includes a primary memory element 210 and a secondary memory element 220 per channel. The primary memory device 210 is directly connected to the host 100 through an external bus OBUS. The primary memory device 210 is connected to the secondary memory device 220 through an internal bus (or relay bus) IBUS. Therefore, the secondary memory device 220 is connected to the host 100 through the primary memory device 210.

2A, 2B, and 2C are side cross-sectional views illustrating various mounting states in the memory module of FIG. 1. FIG. 2A illustrates a state in which the module substrate 202 is mounted on both surfaces thereof, and FIG. 2B illustrates an example in which a single layer structure is mounted on the front surface 202b of the module substrate 202, and FIG. 2C illustrates the module substrate 202. The state mounted in the multilayer structure on the front surface 202a is shown. In the double-sided mounting structure (FIG. 2A) and the single-layer mounting structure (FIG. 2B), an internal bus (IBUS) is formed by pattern formation of the multilayer printed circuit board of the module substrate 202, and the multi-layer mounting structure (FIG. 2C) is multiplied. An internal bus IBUS is formed by forming a layer chip.

3 is a block diagram of a preferred embodiment of a primary memory device according to the present invention.

Referring to FIG. 3, the primary memory device 210 includes a first port 212, a second port 214, a memory core 216, a link processor 218, and a phase synchronization circuit 219. The first port 212 is connected to an external bus (OBUS) that is directly connected to the host 100. The first port 212 is connected to the n-bit downloading bus (DLB) and the n-bit uploading bus (ULB). The second port 214 is connected to the n-bit downloading relay bus (DLRB) and the n-bit uploading relay bus (ULRB).

The memory core 216 is connected to the first port 212 and the second port 214 through the link processor 218. The phase synchronization circuit 209 receives the reference clock signal FCLK to generate the memory clock signal MCLK, the read clock signal RCLK, and the write clock signal WCLK, respectively.

The link processing unit 218 includes a control unit 218a, a first switch 218b, a second switch 218c, a downloading relay buffer 218d, and an uploading relay buffer 218e. The downloading bus DLB is connected to the control unit 218a and the downloading relay buffer 218d, respectively. The downloading relay buffer 218d is connected to the second switch 218c through the downloading internal relay bus DLIRB. The upload bus ULB is connected to the output terminal of the first switch 218b. The downloading relay bus DLRB is connected to the second switch 218c. The uploading relay bus ULRB is connected to the uploading relay buffer 218e. The uploading internal relay bus ULIRB is connected between the uploading relay buffer 218e and one input terminal of the first switch 218b. The uploading internal bus ULIB is connected between the controller 218a and the other input terminal of the first switch 218b. The controller 218a is connected to the memory core 216 through a memory bus MB. The controller 218a controls the first switch 218b on / off through the control signal line CSL1. The controller 218a controls on / off of the second switch 218c through the control signal line CSL2. The controller 218a controls the read write of the uploading relay buffer 218e and the downloading relay buffer 218d through the control signal lines CSL3 and CsL4.

The first switch 218b is switched so that ULIB is connected to the ULB during the read operation of the primary memory 210. The first switch 218b is switched so that the ULIRB is connected to the ULB during the read relay operation of the subprotocol memory 220. The second switch 218c is switched so that the DLIRB is connected to the DLRB during the downloading relay operation.

The downloading relay buffer 218d stores the downloading packet data received through the first port 212 and transmits the stored downloading packet data through the second port 214. The uploading relay buffer 218e stores the uploading packet data received through the second port 214 and transmits the stored uploading packet data through the first port 212.

The control unit 218a receives the downloading packet data in response to the write clock signal received with the packet to decode the command and address packets.

If the decoded command is a write command, the write packet data is converted into memory data. The converted memory data is written to the memory core 216 in response to the memory clock signal MCLK. If the decoded command is a read command, data is read from the memory core 216 to generate read packet data. The generated read packet data is transmitted to the host 100 through the first switch 218b and the upload bus ULB. At this time, the read clock signal RCLK is also transmitted.

If the decoded command is a downloading relay command, the packet data stored in the downloading relay buffer 218d is relayed to the secondary memory 220 through the DLIRB, the second switch 218c, and the DLRB. At this time, the write clock signal WCLK is also transmitted.

If the decoded command is an uploading relay command, the packet data stored in the uploading relay buffer 218e is relayed to the host 100 through the ULIRB, the first switch 218b, and the ULB. In this case, when the decoded command is simultaneously indicated by the read command and the uploading relay command, the decoded command may be simultaneously processed in parallel processing. A detailed description will be described later.

Figure 4 shows the configuration of the downloading and uploading packet according to the present invention. 5 and 6 are diagrams showing the configuration of packets according to the present invention, respectively. 7 and 8 are diagrams showing the truth table of the functions of the command packet according to the present invention. Referring to these drawings, the packet structure of the present invention will be described.

The downloading packet may include a command and address packet and a write data packet as shown in FIG. 4, or may consist of a command and address packet alone. The uploading packet includes one or more read data packets as shown in FIG. In the embodiment shown in the figure, the unit packet 400 has 8 vertical pins and 10 horizontal bursts to transmit m (= 8) bits of parallel data continuously q (= 10) times during one period of the memory clock. It consists of a size of 80 bits (= mxq) with size.

The packet type is divided into a command and address packet 410 and a data packet 420. The command and address packet 410 includes command and address information of the memory elements 210 and 220. Reference numeral 412 in FIG. 5 denotes command and address information of the primary rank, and reference numeral 414 denotes command and address information of the secondary rank.

FOP0 to FOP3 in one column of the region 412 provide a command combination of the primary memory element 210 as a Fore-Ground Operation command. The command combination is shown in FIG. Commands include general DRAM commands such as ACT, READ, WRITE, READ & APC, WRITE & APC, REF, ARF, SRF, PDM, MRS, and NOP, and offset commands such as BAOS, RAOS, CAOS, RDOS, and WTOS. Is provided.

BAOS is a bank address offset command. BAOS is a command for notifying the bank offset when the bank addresses of the primary memory and the secondary memory are different. That is, when this command is received, the secondary memory performs the same operation as that performed in the primary memory in addition to the offset value given to the bank address (where the bank address is the same as the bank address of the primary memory). . Therefore, the secondary memory performs an operation dependent on the primary memory. For example, if the primary memory precharges bank 0, and the secondary memory precharges bank 1, the preliminary command is given to the primary memory, and the BAOS command with a bank offset value of +1 is given to the secondary memory. do.

RAOS is a row address offset command, CAOS is a column address offset command, RDOS is a read offset command and WTOS is a write offset command. These offset commands are for delivering the same command as the command of the primary memory to the storage designated as the offset value of the secondary memory similarly to the BAOS command described above.

In this case, the offset value may be set to a specific value in advance through an MRS or the like, or may be simultaneously provided with a command through a combination of code values or an unused reserved bit portion in a packet.

Such an offset command is very useful for processing data having a relationship between main data and sub data (e.g., image data and attribute data, or independent field data and dependent field data in moving image compressed data).

CS0 to CS2 are bits for selecting a rank in the module and can be selected up to RANK0 to RANK7. Therefore, the rank protocol memory device corresponding to the rank designation signal of CS0 to CS2 executes the command of the region 412. Two columns, BA0 to BA4, can be assigned up to 16 banks as bank address. A0 to A10 of 2 to 4 columns are provided as row addresses or column addresses. Reserved for Future Use (RFU) are reserved bits for future expansion.

If the BGO of 5 columns in the area 414 is a relay instruction (Back-Ground Operation or Repeat Operation), if the value is “0”, the entire relay operation is ignored and only the Fore-Ground Operation command, that is, the command in the area 412 is executed. If it is “1”, FGO and BGO commands are executed simultaneously or only BGO commands are executed.

BP0 to BOP3 provide a command combination of the secondary memory device 220 as a back-ground operation command. The content of the command is the same as the Fore-Ground Operation command described above. RS0 to RS2 are bits for specifying secondary ranks to which a BGO instruction is to be performed. Secondary rank designation is possible to designate single or simultaneous grouping in the 4-rank structure as shown in FIG. In the eight-rank structure, it is possible to designate seven secondary ranks (RANK1 to Rank7) one by one.

Referring to FIG. 6, data packets 422 and 424 each have 8 consecutive bits of data and have a maximum size of 80 bits. The entire 80 bits are either data written to the memory element or composed of data read from the memory element. When the size of data to be written or read exceeds 80 bits, another data packet is continuously formed. Therefore, at least one data packet may be transmitted continuously.

<Description of operation>

1. Lead operation

9 is a view for explaining a read operation of the second rank memory system according to the present invention. FIG. 10 illustrates operation timings of each part of FIG. 9. 11 to 14 show the configuration of a command and an address packet according to each operation.

Referring to the drawings, reference numeral 902 denotes an FGO operation flow of rank 0 primary memory 210, and reference numeral 904 denotes a BGO operation flow of rank 1 secondary memory 220.

The protocol memory 210 receives the command and address packet of FIG. 11 from the host 100 via the DLB. Since CS0 ~ CS2 value is “000”, execute ACT command which is “0000” command of FOP0 ~ FOP3. That is, by activating the row address of bank 0 of the primary memory 210 (ie, opening the bank of the memory), the cell data is taken from a plurality of memory cells associated with the activated row and transferred to the sense amplifier. Next, since the BGO value is "1", the primary memory 210 relays the rank 1 command and the address packet of FIG. 12, that is, the relay command packet, to the secondary memory 220 through the DLRB at the tip of T4 of FIG. 10. . The secondary memory 220 interprets the relayed packet. Since CS0 ~ CS2 value is “001”, execute ACT command which is “0000” command of FOP0 ~ FOP3. That is, by activating the row address of the bank 0 of the secondary memory 220 (ie, opening the bank of the memory), the cell data is taken from the plurality of memory cells associated with the activated row and transferred to the sense amplifier.

At the tip of T7 in FIG. 10, the primary memory 210 receives the command and address packet of FIG. 13. Since CS0 ~ CS2 value is “000”, execute READ command which is “0001” command of FOP0 ~ FOP3. That is, the cell data sensed by the sense amplifier of the bank 0 of the primary memory 210 is transferred to the link controller through the input / output circuit of the memory core. The link control unit forms the transferred memory data into a read data packet. Thus, after 5 clock CAS latency, the read data packet is delivered to the host 100 via the ULB. Subsequently, since the BGO value is “1”, the primary memory 210 relays the rank 1 command and address packet of FIG. 14 to the secondary memory 220 through the DLRB at the tip of T10 of FIG. 10.

At the tip of T10 of FIG. 10, the secondary memory 220 receives the command and address packet of FIG. 14. Since CS0 ~ CS2 value is “001”, execute READ command which is “0001” command of BOP0 ~ BOP3. That is, the cell data sensed by the sense amplifier of the bank 0 of the secondary memory 210 is transferred to the link controller through the input / output circuit of the memory core. The link control unit forms the transferred memory data as a read data packet. Accordingly, after 5 clock CAS latency, the read data packet is transferred to the primary memory 210 of rank 0 through the ULRB. The primary memory 210 temporarily stores the transferred read data packet of the rank 1 in the upload relay buffer. Data packets stored in the upload relay buffer are immediately transferred to the host 100 through the switch 218b. That is, the relay delay time (˜3 ns) of the primary memory 210 is transmitted to the host 100 through the ULB at the front end of T18.

Therefore, the primary memory 210 processes the read command of the primary memory 210 and performs the relay operation of the read data following the relay of the read command of the secondary memory 220.

2. Light operation

15 is a view for explaining the write operation of the second rank memory system according to the present invention. In the write operation, a command and an address packet are transmitted to the primary memory 210 at the tip of T1 of FIG. 15 through the DLB. The primary memory 210 interprets the command to activate the row of bank 0 to be written. At the same time, since the BGO value is "1", the primary memory 210 generates a command and an address packet of the secondary memory 220 and relays it to the secondary memory 220. The secondary memory 220 receives a command and an address packet at the tip of T4. The secondary memory 220 interprets the received command and activates the row of bank 0 to be written.

The write data packets are delivered to the primary memory 210 in succession following the write command packet at the tip of T7. The primary memory 210 interprets the command to activate the corresponding column and writes the write data to the cell. At the same time, the primary memory 210 generates commands and address packets of the secondary memory 220 and relays them to the secondary memory 220. The secondary memory 220 receives a command and an address packet and a write data packet at the tip of T10. The secondary memory 220 interprets the received command and activates the corresponding column to write the write data into the cell.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, in the present invention, by controlling the sub-protocol memory device simultaneously with the access of the protocol memory device, the throughput of data can be increased and the concurrency can be greatly increased.

Claims (7)

First port; Second port; A memory core for storing data; Receiving a command packet provided from a host through the first port, the command packet including a primary command and a secondary command, controlling transmission and reception of memory data between the memory core and the host by the primary command, And a link processor for relaying a relay command packet including the secondary command to another protocol memory device through the second port, wherein the memory core is connected to the first port and the second port through the link processor. Protocol memory device characterized in that. The method of claim 1, wherein the link processing unit Receiving a data packet provided from the other protocol memory device through the second port, and relaying the received data packet to the host through the first port. The method of claim 1, wherein the link processing unit And relaying the relay command packet in response to the relay instruction information included in the secondary command. A primary memory element and a secondary memory element subordinately coupled on one module substrate, The primary memory device receives a command packet provided from a host, transmits and receives data with a host in response to a primary command included in the command packet, and sends the secondary command in response to a secondary command included in the command packet. Relay a relay command packet, The secondary memory device receives the relay command packet provided from the primary memory device, and transmits and receives data to and from the host through the primary memory device in response to the secondary command included in the received relay command packet. Memory module. A host for generating one command packet including a primary command and a secondary command; And A memory module coupled to the host, The memory module mounts a primary memory device and a secondary memory device on a module substrate. The primary memory device receives a command packet provided from the host, transmits and receives data with the host in response to a primary command included in the command packet, and responds to the secondary command included in the command packet. Relay a relay command packet including a command, The secondary memory device receives the relay command packet relayed from the primary memory device, and transmits and receives data to and from the host through the primary memory device in response to the secondary command included in the received relay command packet. Characterized by a memory system. delete Receiving a command packet including a primary command and a secondary command in a first memory device; Relaying a relay command packet including the secondary command to a second memory device while performing a primary command of the received command packet; Receiving the relay command packet relayed from the first memory device at a second memory device; And performing a secondary command of the received relay command packet in the second memory device.

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