KR100717113B1 - Semiconductor memory module and semiconductor memory system - Google Patents

Abstract

According to the semiconductor memory module and the semiconductor memory system of the present invention, when the command / address packet data and / or read packet data or write packet data are exchanged between the memory controller and the primary memory, the primary memory and the secondary memory are also paralleled. Send and receive different types of command / address packet data and / or packet data. Therefore, the throughput of data and the concurrency can be greatly increased. In addition, the number of pins of the secondary memory may be less than that of the primary memory, thereby greatly reducing the cost of the entire memory system. In addition, by placing the cache in the primary memory to increase the throughput (throughput) of the memory system, it is possible to organize the cache hierarchically.

Description

Semiconductor memory module and semiconductor memory system {SEMICONDUCTOR MEMORY MODULE AND SEMICONDUCTOR MEMORY SYSTEM}

1 is a block diagram illustrating an example of a memory module having a conventional multi-drop bus structure.

2 is a block diagram illustrating another example of a memory system having a conventional multi-drop bus structure.

3 is a block diagram illustrating a memory module according to an exemplary embodiment of the present invention.

4A and 4B are block diagrams illustrating example embodiments of the memory module of FIG. 3.

5 is a block diagram illustrating another embodiment of the memory module of FIG. 3.

6 is a block diagram illustrating still another embodiment of the memory module of FIG. 3.

FIG. 7 is a diagram illustrating a packet applied through the WR / CA pin of the memory module of FIG. 4A.

8 is a timing diagram illustrating downloading and uploading packet data according to an embodiment of the present invention.

FIG. 9 is a timing diagram for describing a detailed operation of the memory module of FIG. 4A.

FIG. 10A illustrates a command packet applied to a primary memory from the host of FIG. 6A during a data read operation.

FIG. 10B illustrates a command packet applied to the secondary memory from the primary memory of FIG. 6A during a data read operation.

11A and 11B are block diagrams illustrating memory systems according to other example embodiments of the inventive concepts.

12A through 12B are block diagrams illustrating memory systems in accordance with some example embodiments of the inventive concepts.

13A to 13B are block diagrams illustrating memory systems connected by a serial link between a primary memory and a secondary memory according to another embodiment of the present invention.

FIG. 13C illustrates a packet applied from a primary memory connected to a serial link to a secondary memory during a data read operation. FIG.

14A, 15, and 16 are block diagrams illustrating memory systems including a cache memory, according to another exemplary embodiment.

FIG. 14B is a block diagram illustrating an example of an internal block of the primary memory of FIG. 14A.

17 is a conceptual diagram illustrating a case in which memories of a second rank memory module have a stacked structure according to another embodiment of the present invention.

18 is a conceptual diagram illustrating a case in which memories of a 4 rank memory module have a stacked structure according to another embodiment of the present invention.

19 is a conceptual diagram illustrating a structure in which memories of a second rank memory module according to another embodiment of the present invention are arranged.

20 and 21 are conceptual views illustrating a structure in which memories of a 4 rank memory module according to still another exemplary embodiment of the present invention are arranged.

<Explanation of symbols for the main parts of the drawings>

Host: 300, 600, 1100, 1200a, 1200b, 1300a, 1300b, 1400, 1500, 1600

Primary memory: 310, 610, 1110, 1210a, 1210b, 1310a, 1310b, 1410, 1510, 1610

Secondary memory: 320, 620, 1120, 1220a, 1220b, 1320a, 1320b, 1420, 1520, 1620

Memory module: 350, 650, 1150, 1250a, 1250b, 1350a, 1350b, 1450, 1550, 1650

1415: cache

The present invention relates to a memory system, and more particularly, to a semiconductor memory module and a semiconductor memory system for transmitting and receiving packet data between a host and a memory.

The operating speed of the CPU of a computer system is very high, for example several GHz or more, while the operating speed of the memory is relatively low, for example several hundred MHz, so that a chipset called a memory controller can be connected for interfacing between the computer system and the memory. do. Data transfers between the computer system and the memory controller at high speed. Data is transferred between the memory controller and the memory at the operating speed of the memory.

1 is a block diagram illustrating an example of a memory module having a conventional multi-drop bus structure.

Referring to FIG. 1, a plurality of memories M1 to M8 are connected to a signal of a memory controller (not shown) in a multi-drop manner.

As shown in FIG. 1, in general, DRAMs such as Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate (DDR) 1, DDR 2, and DDR 3 are provided with a command / address of a memory controller (not shown). ) A multi-drop bus structure in which a plurality of DRAMs are simultaneously connected to the buses CA and 12 is used. The write / read data buses 14 and DQ are each independently wired to the host with respect to the plurality of memories M1 to M8.

2 is a block diagram illustrating a memory system having a conventional multi-drop bus structure, in which a plurality of memory modules are configured to increase a memory capacity.

As illustrated in FIG. 2, a plurality of memories M11 to M1N and M21 to M2N in each memory module 210 and 220 are connected to a command / address bus CA of the memory controller 200, and different memories are provided. Module selection is achieved via chip select signals (/ CS0, / CS1, ...). Each write / read data bus of the plurality of memories M11 to M1N in the memory module 210 is connected to each write / read data bus of the plurality of memories M21 to M2N and wired to the host.

As described above, in the case of the conventional multi-drop bus structure, more memory modules are connected to one memory controller in order to increase capacity. As the number of memory modules increases, the memory connected to the write / read data bus increases. That is, the loading of the write / read data bus becomes large, which is a limiting factor in the high speed of operation. For example, the maximum number of SDRAMs connected to a single write / read data bus is limited to eight, four DDR 1s and two DDR 2 / DDR 3s.

Therefore, when the memory module having DDR 1, DDR 2, DDR 3 memory is mounted using a memory module having a conventional multi-drop bus structure, there is a limit in speeding up the memory operation speed.

Accordingly, it is a first object of the present invention to provide a memory module capable of high speed and high capacity.

In addition, a second object of the present invention is to provide a memory system using the memory module.

Memory module according to an aspect of the present invention for achieving the first object of the present invention described above transmits and receives the first packet data with the host through the first port of the N pin (N is a positive integer), K ( K is an integer smaller than N) at least one primary memory for transmitting and receiving second packet data through the second port of the pin; And at least one secondary memory receiving the corresponding primary memory and the second packet data through a third port of the K pins. The at least one secondary memory may be point-to-point connected with the corresponding primary memory. The at least one primary memory may read the predetermined first data from the corresponding secondary memory through the second port through a background operation and store the read first data in the first cache memory.

In addition, a memory system according to an aspect of the present invention for achieving the second object of the present invention is a host; And transmitting and receiving first packet data with the host through a first port of N pins (N is a positive integer) and transmitting and receiving second packet data through a second port of K pins (K is an integer less than N). And a memory module having at least one primary memory, a corresponding primary memory and at least one secondary memory receiving the second packet data through a third port of the K pins. The memory system may include a cache memory between the host and the primary memory that pre-stores predetermined data frequently accessed by the host.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.

The embodiments of the present invention described below provide a point-to-point connection between a host and a primary memory, and between a primary memory and at least one secondary memory in connecting a host and a plurality of memories. Points are connected. Here, the number of buses between the host and the primary memory, the interface method and / or the protocol may be implemented differently from the number of buses between the primary memory and the secondary memory, the interface method and / or the protocol. As a result, when the primary memory and the host exchange data of some type, the background memory can be simultaneously transferred between the primary memory and the secondary memory so that the efficiency of the entire memory system can be improved. Can increase.

Here, primary memory refers to a memory that is point-to-point connected to a host. Secondary memory refers to a memory that is point-to-point coupled to the primary memory or memory that is point-to-point coupled to the primary memory.

Hereinafter, the primary memory and the secondary memory dependent on the primary memory may be connected on the same plane (planar structure). The primary memory may be mounted on one surface of the memory module and the secondary memory may be mounted on the other surface of the memory module. Alternatively, the primary memory and the secondary memory dependent on the primary memory may be implemented to have a stacked structure such as a die stack or a package stack.

In the following drawings, only one primary memory in each memory module is illustrated, but the present invention may be applied to a case in which two or more primary memories in each memory module are in parallel.

Memory in the memory module according to an embodiment of the present invention may be composed of DRAM, for example DDR2, DDR3.

<Example>

3 is a block diagram illustrating a memory system according to an example embodiment.

Referring to FIG. 3, the memory system includes a host 300 and a memory module 350. In this case, the host refers to a main board in which a memory module socket in which a memory module is inserted is mounted. The host in a narrow sense refers to a chip that directly communicates with a memory module, such as a memory controller chip set or a north bridge chip set. In FIG. 3, one primary memory 310 and one secondary memory 320 are illustrated in one memory module 350, but two or more primary memories 310 and one primary memory 310 are included in one memory module 350. Two or more secondary memories 320 may be included.

The host 300 has a first port of X pins connected point-to-point with the primary memory 310 of the memory module 350 through a primary bus (PB), and In the head memory 310, a second port of Y pins is point-to-point connected to the secondary memory 320 through the secondary bus SB. Where Y has a value less than X. Command / address signals and write / read data are transmitted through the primary bus PB and the secondary bus SB.

The host 300 provides the memory module 350 with a reference clock REFCLK and a write reference clock WCLK (not shown) for command / address and / or writing. The memories in the memory module 350 generate a read reference clock RCLK (not shown) for transmitting read data to the host 300 using the reference clock REFCLK. The clocks REFCLK, WCLK, and RCLK may be configured as a group of typical data bus pins, for example, one per four or eight bytes.

Referring to FIG. 3, the pin number Y of the secondary memory 320 is smaller than the pin number X of the primary memory 310. The protocol used between the host 300 and the primary memory 310 and the protocol used between the primary memory 310 and the secondary memory 320 may be different. In detail, the number and function of buses of the second ports connected to the secondary memory 320 are different from the number and function of buses of the first ports connected to the primary memory 310. In addition, a differential input / output signal may be transmitted to the primary bus PB, and a single ended signal may be transmitted to the secondary bus SB.

In this case, the memory of one memory system may have at least two types. Specifically, in the case of the primary memory 310, a function of repeating command / address and write packet data to the secondary memory 320, and temporarily storing data read from the secondary memory 320 or directly by a host ( Logic circuits capable of performing various functions, such as a function of transferring to 300, may be further added.

On the other hand, the number of pins of the second port of the secondary memory 320 is less than that of the primary memory 310, and mainly depends on the primary memory 310 to significantly reduce the cost of the entire memory system. Can be. In particular, when the input / output signal serially connected to the secondary bus of the secondary memory 320 can significantly reduce the number of pins of the second port, when a large number of memories are stacked for high capacity as shown in FIGS. 12A to 16. The number of wirings can be greatly reduced.

4A and 4B are block diagrams illustrating example embodiments of the memory module of FIG. 3. FIG. 4A illustrates a secondary memory 620 and a primary memory 620 through a background operation 682 simultaneously during a foreground operation 680 in which the host 600 and the primary memory 610 exchange data. 610 indicates a case of sending and receiving data. 4B conceptually illustrates an operation 684 of exchanging data by accessing the secondary memory 620 in the host 600.

Referring to FIG. 4A, a point-to-point connection between the host 600 and the primary memory 610 is performed through an N pin WR / CA port and an M pin read data (RD) port. In addition, the primary memory 610 and the secondary memory 620 are point-to-point connected through the WR / CA ports of the K pins and the read data (RD) ports of the L pins. N, M, K, and L are positive integers. For example, N may be 8, K is 4, M is 8 and L may be 4.

The write data bus WR and the command / address bus CA are merged to form the downloading buses 601 and 611. The read data bus RD constitutes the uploading buses 603 and 613. Alternatively, as shown in FIG. 5, the command / address bus CA may be separated, and the read data bus RD and the write data bus WR may be merged. Alternatively, as shown in FIG. 6, the command / address bus CA, the read data bus RD, and the write data bus WR may be separated from each other.

Command / address packet data and / or write packet data from the host 600 to the primary memory 610 or from the primary memory 610 to the secondary memory 620 is transmitted via the download buses 601 and 611. It is transmitted in one direction in the form of.

In addition, the read data is unidirectionally through the uploading buses 603, 613, that is, from the primary memory 610 to the host 600 or from the secondary memory 620 to the primary memory 610 in the form of packet data. Is sent.

Where K is less than N. L is less than M That is, since the number of pins of the secondary memory 620 is smaller than the number of pins of the primary memory 610, when the plurality of memories are stacked in one memory module for high capacity, the number of wirings may be greatly reduced.

FIG. 7 illustrates a packet applied from the host of FIG. 4A to the primary memory through the WR / CA pin of the memory module, and FIG. 8 is a timing diagram illustrating downloading and uploading packet data according to an embodiment of the present invention. FIG. 9 is a timing diagram for describing a detailed operation of the memory module of FIG. 4A. 10A illustrates a command / address packet applied to the primary memory from the host of FIG. 4A during a data read operation, and FIG. 10B illustrates a command / address applied to the secondary memory from the primary memory of FIG. 4A during a data read operation of FIG. 10A. Represents an address packet.

Hereinafter, the operation of the memory module of FIG. 4A will be described with reference to FIGS. 7 to 10B.

7 illustrates command / address packet data and write packet data input through the WR / CA port of the primary memory.

Referring to FIG. 7, command / address packet data is applied through eight pins PIN0 to PIN8 of the WR / CA port for one period of the reference clock REF CLOCK or the write reference clock WCLK, and a write packet Write packet data is applied through eight pins of the WR / CA port in accordance with a reference clock (REF CLOCK) or a write reference clock (WCLK). In FIG. 7, for example, it is assumed that 20 burst packet data are input for two periods. Here, although the number of information input per one reference clock period is assumed to be 10 and the number of pins of the WR / CA port is 8, it can be reduced or increased according to the reference clock frequency.

Operand 3/2/1/0 is input to pin 0/1/2/3 of the WR / CA port of burst 1, and row address activation and read (by combination of 16 operands) Commands such as read, write, precharge, and refresh operations may be indicated. In addition, a rank selection signal CS2 / CS1 / CS0 is input to pins 5/6/7 of the WR / CA port of the burst 1, and up to eight ranks can be selected.

In burst 2, four memory bank addresses BA3 / BA2 / BA1 / BA0 are applied to pins 0/1/2/3 of the WR / CA port so that up to 16 memory banks can be selected. Addresses A10 through A0 are inputted through pins 5/6/7 of the WR / CA port of burst 2 and pins 0 through 7 of the WR / CA port of burst 3, so that the corresponding row address or You can select a column address.

After burst 4, it is represented by a reserved for future use (RFU) field, and the RFU field may be used as an area for a background operation to be described later. The data after the T1 cycle is an example of a write data packet input under the assumption that a write command is input in the T0 cycle. 80 bits of data are transmitted in one cycle.

Referring to FIG. 8, the downloading packet is composed of one unit packet (CA packet) or three unit packets (CA packet, WR0 packet, WR1 packet) as a basic unit of transmission. The WR0 packet and the WR1 packet represent write packet data. The uploading packet data uses two unit packets (RD0 packet and RD1 packet) as basic units of transmission. The RD0 packet and the RD1 packet represent read packet data.

For example, the unit packet may consist of 80 bits of data having a length of 8 pins and a width of 10 bursts in order to transmit 8 bits of parallel data 10 times in succession during one cycle of the clock.

Packet types are classified into command / address packets (CA packets) and data packets. The command / address packet contains command and address information.

Referring again to FIG. 4A, primary memory 610 reads packet data from secondary memory 620 during foreground operation 680 where host 600 reads packet data from primary memory 610. Performs a background operation 682.

While the host 600 only accesses the primary memory 610, the primary memory 610 operates in a “smart” state, and the secondary memory 620 does not operate at all “stand-by”. ) "State.

When writing data to the secondary memory 620, the primary memory 610 receives a command, address packet data, and write packet data from the host 600, and repeats the packet data necessary for the secondary memory 620. It acts as a (repeater).

When reading packet data from the secondary memory 620, the primary memory 610 operates as a repeater for relaying read packet data read from the secondary memory 620 to the host 600.

Hereinafter, a case in which the host 600 reads packet data from memory bank 0 of the primary memory 610 having rank 0 and reads packet data from memory bank 0 of the secondary memory 620 having rank 1 is described below. It demonstrates by an example.

Referring to FIG. 9, first, a command ACT R0B0 for activating a row address of memory bank 0 in rank 0 and a command for activating row address of memory bank 0 in rank 1 from the host 600 through the WR / CA bus The packet data 701 including the ACT R1B0 is transmitted to the primary memory 610 in synchronization with the reference clock REF CLK at the time T1.

Packet data 701 including the ACT R0B0 and the ACT R1B0 commands is shown in FIG. 10A, and packet data 703 including the ACT R1B0 command is shown in FIG. 10B. The primary memory 610 converts the N packet data transmitted through the N pins per burst from the host 600 to be transmitted to the K packet data through the K pins per burst and transmits the data to the secondary memory 620. do. Conversely, read packet data consisting of K bits per burst transmitted from the secondary memory 620 is converted into N read packet data per burst and transmitted to the host 620.

Referring to FIG. 10A, '0100' indicating the activation command of the row address of the primary memory is input to pins 0/1/2/3 of the WR / CA port of the burst 1, and the burst 1 '000' indicating the rank 0, which is the primary memory, is input to pins 5/6/7 of the WR / CA port. The memory bank address and memory address for the remaining primary memories of bursts 2 and 3 are the same as described in FIG.

Also, for background operation, '0100' indicating the activation command of the row address of the secondary memory is input to pin 0/1/2/3 of the WR / CA port of the burst 4, and the WR of the burst 4 is input. '001', which indicates rank 1, the secondary memory, is input to pin 5/6/7 of the / CA port. The memory bank address and the memory address for the second memories of the remaining bursts 5 and 6 are the same as described with reference to FIG. 8.

Referring to FIG. 10B, '0100' indicating the activation command of the row address of the secondary memory is input to pin 0/1/2/3 of the WR / CA port of burst 1, and the WR of burst 1 is input. '001', which indicates rank 1, the secondary memory, is input to pin 5/6/7 of the / CA port. The memory bank address and the memory address for the secondary memories of the remaining bursts 2 and 3 are the same as described with reference to FIG. 7.

Referring again to FIGS. 4A and 9, the primary memory 610 activates a row address of memory bank 0 of rank 0 in response to the ACT R0B0 command, and predetermined packet data 703 including the ACT R1B0 command. After the delay time (repeater delay) of the T4 instantaneous synchronization with the reference clock (REF CLK) and outputs to the secondary memory 620 through the WR / CA port.

The host 600 reads the packet data from the memory bank 0 of the rank 0 and the packet from the memory bank 0 of the rank 1 from the output of the ACT R0B0 command after the predetermined delay time tRCD, at the time T7. The packet data 705 including the command RD R1B0 for reading data is transmitted to the primary memory 610 via the WR / CA bus in synchronization with the reference clock REF CLK.

The primary memory 610 reads the packet data from the memory bank 0 of rank 1 from the time of T10 at which the ACT R1B0 command is relayed to the secondary memory 620 after a predetermined delay time tRCD. The packet data 707 including R1B0 is transmitted to the secondary memory 620 through the WR / CA bus in synchronization with the read clock.

In response to the RD R0B0 command, the primary memory 610 transmits the data 709 indicated by the address through the WR / CA bus at a T13 instant after a predetermined column address strobe latency. Will output

The secondary memory 620 outputs the data 711 indicated by the address to the primary host 610 through the WR / CA bus at the time T16 after a predetermined CAS latency in response to the RD R1B0 command.

The primary memory 610 outputs the data 713 inputted from the secondary memory 620 to the host 600 through the WR / CA bus at a time T18 after a predetermined repeater delay.

11A through 11D are block diagrams illustrating a memory system according to other example embodiments of the inventive concepts.

11A and 11B, the host 1100 is connected to the memory module 1150 through a plurality of channels, for example, CH0 to CH3 or CH0 to CH7. Each channel consists of an N bit down loading bus 1101 and an M bit up loading bus 1103. Here, N and M may be different values, and the same value, for example, N may have 8, and M may have 8.

Hereinafter, the downloading bus 1101 may be a bus in which the write data bus WR and the command / address bus CA are merged (see FIG. 4A), or only the command / address bus CA is used. The write data bus WR and the command / address bus CA (see Fig. 6) wired independently of each other may be shown.

The uploading bus 1103 may be a bus in which the write data bus WR and the read data bus RD are merged (see FIG. 5), or may represent only the read data bus RD (see FIGS. 6 and 4A). ).

The host 1100 provides a clock signal 305 to the memory module 350. The clock signal 305 may be a write reference clock (WCLK, not shown) or a command / address clock (CACLK, not shown). The host 300 provides a power supply voltage (not shown) to the memory module 350. The memories in the memory module 1150 generate a read reference clock RCLK (not shown) for transmitting read data to the host 1100.

Hereinafter, the clock signals CACLK, WCLK, and RCLK are used to input and output command / address packet data, write data, and read data, respectively, and are not shown in the drawings for convenience of description.

11A and 11B illustrate an example in which one memory module 1150 includes four and eight primary memories and four and eight secondary memories, respectively, but one memory module 1150 is represented by four. Other n primary memories and n secondary memories may be included. 4A and 4B illustrate only one of the plurality of primary memories and the secondary memories of FIG. 11A.

Referring back to FIGS. 11A and 11B, the host 1100 and the primary memory 1110 may have N pins through the downloading bus 1101 in which the write data bus WR and the command / address bus CA are merged. A point-to-point connection is made between the WR / CA port of M and the read data (RD) port of M pins.

In addition, the primary memory 1110 and the secondary memory 1120 may be connected to the WR / CA ports of N pins through the downloading bus 1111 in which the write data bus WR and the command / address bus CA are merged. Point-to-point connections between the read data (RD) ports of the M pins.

Command / address packet data and / or write packet data from the host 1100 to the primary memory 1110 or from the primary memory 1110 to the secondary memory 1120 via the download buses 1101 and 1111. It is transmitted in one direction in the form of data.

In addition, the read data is unidirectionally through the uploading buses 1103 and 1113, that is, from the primary memory 1110 to the host 1100 or from the secondary memory 1120 to the primary memory 1110 in the form of packet data. Is sent to.

For example, N = 8, K = 4, M = 4, L = 2, where K is less than N and L is less than M. That is, since the pin count of the secondary memory is smaller than the pin count of the primary memory, when a plurality of memories are stacked in one memory module for high capacity, the number of wirings of the memory module can be reduced.

12A and 12B are block diagrams illustrating memory systems in accordance with some example embodiments of the inventive concepts.

12A shows an example in which a write data bus, a command and an address bus are merged, and FIG. 12B shows an example in which the write data bus WR and the command / address bus CA are independently wired. Although not shown, the write data bus WR and the read data bus RD may be merged.

12A and 12B, the host 1200a and 1200b and the primary memory 1210a and 1210b exchange address / command, write packet data and read packet data through N pins and M pins. The primary memory 1210a and 1210b and the secondary memory 1220a and 1220b exchange address / command, write packet data and read packet data through K pins and L pins. Where K is less than N and L has a value less than M.

In addition, the primary memory 1210a and 1210b and the third memory 1230a and 1230b exchange address / command, write packet data and read packet data through K pins and L pins. The 1212a and 1210b and the fourth memory 1230a and 1230b exchange address / command, write packet data and read packet data through K pins and L pins.

Background operations may occur in parallel while foreground operations between the hosts 1200a and 1200b and the primary memories 1210a and 1210b exchange data.

In this case, the background operation may be performed by the secondary memories 1220a and 1220b and the primary memories 1210a and 1210b exchanging address / command packet data, write packet data, and / or read packet data, or by third memory 1230a and 1230b. And primary memory 1210a and 1210b exchange address / command packet data, write packet data and / or read packet data, or pod memory 1240a and 1240b and primary memory 1210a and 1210b address / command packet. A case of exchanging data, write packet data, and / or read packet data is shown.

13A and 13B are block diagrams illustrating memory modules connected by a serial link between a primary memory and a secondary memory according to another embodiment of the present invention. Although not shown, the write data bus WR and the read data bus RD may be merged.

The primary memories 1310a and 1310b include a serializer (not shown) for converting N-bit parallel data into serial data therein and a deserializer for converting serial data to N-bit parallel data. City).

Referring to FIGS. 13A and 13B, the primary memory 1310a and 1310b and the secondary memory 1320a and 1320b are compared with the number of pins of the primary link between the hosts 1300a and 1300b and the primary memories 1310a and 1310b. The number of pins on the secondary link is greatly reduced and connected to the serial link.

That is, between the primary memories 1310a and 1310b and the other dependent memories 1320a, 1320b, 1330a, 1330b, 1340a, and 1340b, the address / command packet data, write packet data, and read packet data are serially transmitted. .

Host 1300a, 1300b reads packet data from memory bank 0 of rank memory primary memory 1310a, 1310b, and reads packet data from memory bank 0 of rank memory secondary memory 1320a, 1320b. The timing diagram for the operation is the same as in FIG. 7 except that the packet transmission is serial, and thus description thereof is omitted.

FIG. 13C illustrates a command packet serially transmitted from the primary memory of FIGS. 13A and 13B to the secondary memory in the data read operation of FIG. 7. FIG. 13C shows the packet data of FIG. 10B in series. 1301 of the serialized packet indicates an activation command of a row address of the primary memory, and 1305 indicates rank 1, which is a secondary memory. 1309 indicates a memory bank address and a memory address for the secondary memory, and 1311 indicates a reserved for future use.

When the required memory capacity of the memory system of the present invention is increased and a memory module is composed of three or more ranks, a latency for accessing dependent memories such as secondary, third, and pod memories other than the primary memory is provided. ) May increase.

In addition, from the host's point of view, command scheduling may become difficult and bus efficiency may be reduced due to different read or write latency for each rank.

In order to solve the above problems, by installing a cache of a predetermined size inside the primary memory adjacent to the host, the necessary data is pre-loaded from the secondary memory into the cache memory in advance. In terms of access as a whole, the access probability with the primary link can be maximized.

14A, 15, and 16 are block diagrams illustrating memory modules including a cache memory, according to another exemplary embodiment. FIG. 14B illustrates an example of an internal block of the primary memory of FIG. 14A, in which the primary memory is implemented as a DRAM and the number I of WR / CA pins is 1. Embodiments of the present invention are not limited to the internal block configuration of the memory illustrated in FIG. 14B, and a memory having a cache memory may also be applied to other memory devices having a modified structure of the internal block of FIG. 14B.

Referring to FIGS. 14A and 14B, a memory 1415 is placed in the primary memory 1410 to access data frequently accessed by the host 1400 through a predetermined background operation 1462 through a memory background in the primary memory 1410. The data is read from the array 1476 and stored in the cache 1415 in advance. For example, data frequently accessed by the host 1400 may be determined to reflect the past memory data access trend of the host. Therefore, since only the primary memory 1410 needs to be accessed through the foreground operation 1480 during the page hit in the host 1400, the frequency of connecting the dependent memories 1430 after the secondary memory 1420 may be determined. This reduces the throughput of the overall memory system.

Referring to FIG. 14B, the packet decoder 1452 receives a WR / CA packet (write data, command / address packet) synchronized with the WCLK clock from the host 1400 through the xN pin, and decomposes the packet to write data and command. To decompose it into addresses. The command is interpreted by the command decoder 1456 and the address is interpreted by the address decoder 1458. Write data is provided to the input buffer 1454 and provided to the memory cell array 1415 via the data input register 1472, the cache buffer 1415, or the data buffer 1492, the serializer 1494 and the repeater. Via 1496, it is provided to the secondary memory 1420. The demultiplexer 1464 selects one of the two paths through which the write data is transmitted by a predetermined control signal control 1. The repeater 1496 operates as a kind of output driver. The data input register 1472 functions as a buffer for temporarily storing data, and the data input register 1472 of FIG. 14B may be omitted.

On the other hand, read data received from the secondary memory 1420 through the xJ pin is provided to the memory cell array 1415 via the input buffer 1454, or the deserializer 1466, the multiplexer 1468, and the output buffer 1470. It is provided to the host 1400 via. The demultiplexer 1462 selects one of the two paths through which the read data is transmitted by a predetermined control signal (control 2).

The cache 1415 reads data from or writes data to the memory cell array 1415 based on the predetermined control signal control 3. Frequently needed data in the host 1500 may be read from the secondary memory 1420 and / or the third memory 1430, and may be stored in advance in the memory cell array 1415 of the primary memory 1410. It may be previously stored in the memory cell array 1415 of the memory 1410.

Data read from the memory cell array 1476 of the primary memory 1410 is provided to the host 1400 via the cache 1415, the prefetch unit 1474, the multiplexer 1468, and the output buffer 1470. Here, the multiplexer 1468 selects either read data transmitted from the secondary memory 1420 or read data read from the memory cell array 1476 of the primary memory 1410 based on a predetermined control signal control 4. To the output buffer 1470. In this case, the clock driver 1490 may generate a read reference clock RCLK using the reference clock REF CLK and provide the read reference clock RCLK to the host 1400.

FIG. 15 fetches and stores data frequently needed by the host 1500 in the first cache 1515 of the primary memory 1510 in advance through a predetermined background operation 1852 and frequently stores the data in the primary memory 1510. The required data is brought into the second cache 1525 of the secondary memory 1520 in advance through a predetermined background operation 1584 and stored therein. Accordingly, since only the primary memory 1510 needs to be accessed through the foreground operation 1580 when the page hits the host, the overall memory is reduced by reducing the frequency of accessing the slave memories 1530 after the secondary memory 1520. It can increase the throughput of the system. The cache sizes of the first cache 1515 and the second cache 1525 may be different. In other words, the cache size may be different for each memory rank depth. Therefore, the data distribution effect according to page locality can be obtained.

14A and 15, the host 1400 and 1500 and the primary memory 1410 and 1510 exchange command / address packet data and packet data through N pins and M pins, whereas primary The memory 1410 and 1510 and the secondary memory 1420 and 1520 exchange command / address packet data and packet data through I and J pins. In addition, the secondary memory 1420 and 1520 and the third memory 1430 and 1530 exchange command / address packet data and packet data through I and J pins. Where I is less than N and J has a positive integer value less than M.

FIG. 16 illustrates that an external cache 1605 is mounted in the memory module 1650 and the data frequently used by the host 1600 is brought to the external cache 1605 in advance through predetermined background operations 1802 and 1684. Save it. Since the host 1600 only needs to access the external cache 1605 through the foreground operation 1680 when a page hit occurs, the slave memories 1620a and 1630a, 1620b, and 1630b, 1620c, and 1630c after the secondary memories 1610a through 1610d. 1620d and 1630d may be reduced to increase throughput of the overall memory system.

FIG. 17 illustrates a case where a primary memory and a secondary memory of a second rank memory module as shown in FIG. 11A according to another embodiment of the present invention have a stack structure of a die stack or a package stack. Indicates.

Referring to FIG. 17, the primary memory 310 located below one of the first stack memories on the memory module 350 may transmit command / address packet data through a host (not shown) and a downloading bus, for example, a WR / CA bus. And the write packet data is received, and the primary memory 310 retransmits the received command / address packet data and the write packet data to the secondary memory 320 on the memory module 350.

Data read from the upper secondary memory 320 is retransmitted to the primary memory 310 and output to a host (not shown) through an upload bus, for example, a read data bus RD.

FIG. 18 illustrates a stack structure of a die stack or a package stack of primary and secondary memories of a 4 rank memory module as shown in FIGS. 12A through 16 according to another embodiment of the present invention. The implementation case is shown.

Referring to FIG. 18, the primary memory 1810 located below one of the first stack memories on the memory module 350 may transmit command / address packet data through a host (not shown) and a downloading bus, for example, a WR / CA bus. And write packet data, the primary memory 1810 retransmits the received command / address packet data and write packet data to the secondary memory 1820 on the memory module 350. The primary memory 1810 retransmits the received command / address packet data and write packet data to the third memory 1830 on the memory module 350. The primary memory 1810 retransmits the received command / address packet data and write packet data to the pod memory 1840 on the memory module 350.

Data read from the upper secondary memory 1820, the third memory 1830, or the pod memory 1840 is retransmitted to the primary memory 1810 to be transferred to the host via an upload bus (eg, a read data bus RD). (Not shown).

19 is a conceptual diagram illustrating a structure in which memories of a second rank memory module according to another embodiment of the present invention are arranged, and FIGS. 20 and 21 illustrate arrangements of memories of a fourth rank memory module according to another embodiment of the present invention. Is a conceptual diagram showing a structured structure.

The memory module 350 of FIG. 19 illustrates a second rank memory system in which a primary memory 310 of rank 0 and a secondary memory 320 of rank 1 are disposed on a first surface 302a of a semiconductor substrate 302.

In the memory module 1250 of FIG. 20, a primary memory 1210 of rank 0 and a secondary memory 1220 of rank 1 are disposed on a first surface 1202a of a semiconductor substrate 1202, and a second surface of a semiconductor substrate 1202. A rank 3 third memory 1230 and rank 4 pod memory 1240 are disposed at 1202b. The memories 1210 to 1240 are connected in a point-to-point manner by the internal buses 1215, 1225, and 1235.

The memory module 1200 of FIG. 21 includes a primary memory 1210 of rank 0, a secondary memory 1220 of rank 1, a third memory 1230 of rank 3, and a pod memory of rank 4 on a first surface 1202a. 1240 illustrates a four rank memory system. The memories 1210 to 1240 are connected in a point-to-point manner by the internal buses 1215, 1225, and 1235.

The external buses 305 and 1205 and the internal buses 315, 1215, 1225 and 1235 may include a command / address (CA) bus, a write data (WR) bus, and a read data (RD) bus. Alternatively, the external buses 305 and 1205 and the internal buses 315 and 1215 may include a command / address (CA) bus, a write data (WR) bus, and a read data (RD) bus. Alternatively, the external buses 305 and 1205 and the internal buses 315 and 1215 may include a write data and command / address (WR / CA) bus and a read data (RD) bus.

According to the memory module and the memory system as described above, when a command / address and / or data is exchanged between the host and the primary memory, another type of command / address and / or data can be simultaneously exchanged between the primary memory and the secondary memory. Can be. When the host accesses the primary memory, the host issues a command for a transaction of necessary data to the port of the secondary memory. As a result, the host exchanges commands / addresses and / or data with the primary memory, while at the same time the necessary data is inputted and outputted through the other resting ports of the secondary memory. Therefore, the throughput of data and the concurrency can be greatly increased.

In addition, since the number of pins of the secondary memory is smaller than that of the primary memory, it is possible to operate dependently on the primary memory, thereby significantly reducing the cost of the entire memory system. In particular, when the serial link between the primary memory and the secondary memory is used, the number of pins of the secondary memory can be greatly reduced, and thus the number of wires can be greatly reduced when the memory stacking structure is used for high capacity.

 In addition, the cache is stored in the primary memory to store the data that is frequently needed by the host in advance, and reduces the frequency of accessing the subordinate memories after the secondary memory at the time of page hit. throughput can be increased.

In addition, a first cache is placed inside the primary memory, and a second cache having a different cache size from the first cache is placed inside the secondary memory so that data frequently needed by the host is brought into the first cache of the primary memory in advance. In order to store the data frequently needed in the primary memory, the secondary memory is stored in advance in the second cache of the secondary memory. By varying the cache size for each memory link depth, data distribution effect according to page locality may be obtained.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (20)

Transmitting and receiving first packet data with a host through a first port of N (N is a positive integer) pins, and transmitting and receiving a second packet data through a second port of K (K is an integer less than N) pins. At least one primary memory; And And a corresponding primary memory and at least one secondary memory for receiving the second packet data through a third port of the K pins. The memory module of claim 1, wherein the at least one secondary memory is point-to-point coupled with the corresponding primary memory. The memory module of claim 1, wherein the second packet data includes one burst of K bits, and the first packet data includes one burst of N bits. The memory module of claim 3, wherein the at least one primary memory converts the first packet data consisting of N bits per burst to have K bits per burst to generate the second packet data. The memory module of claim 3, wherein the at least one primary memory converts second packet data consisting of K bits per burst to have N bits per burst to generate the first packet data. The method of claim 1, wherein when the host performs a write operation to the secondary memory, the primary memory receives command packet data, address packet data, and write packet data from the host through the first port. And relay to the secondary memory through a port. The method of claim 1, wherein when the host performs a read operation from the secondary memory, the primary memory receives read packet data from the secondary memory through the second port to the host through the first port. And a memory module for relaying. 2. The memory module of claim 1 wherein K is one. The method of claim 8, wherein when the host performs a write operation to the secondary memory, the primary memory receives and serializes command packet data, address packet data, and write packet data from the host through the first port. And relay to the secondary memory through a second port. The method of claim 8, wherein when the host performs a read operation from the secondary memory, the primary memory receives and deserializes read packet data from the secondary memory through the second port and through the first port. And relay to the host. The memory module of claim 1, wherein the at least one primary memory comprises a first cache memory that stores in advance predetermined first data frequently accessed by the host. The method of claim 11, wherein the at least one primary memory reads the predetermined first data from the corresponding secondary memory through the second port through a background operation and stores the first data in the first cache memory. Memory module. 12. The memory module of claim 11, wherein the at least one secondary memory further comprises a second cache memory that pre-stores predetermined second data frequently accessed from the corresponding primary memory. The memory module of claim 13, wherein sizes of the first cache memory and the second cache memory are different from each other. The memory module of claim 1, wherein the at least one secondary memory transmits third packet data to a corresponding primary memory through a third port of the K pins. 16. The memory module of claim 15, wherein the at least one primary memory receives the third packet data from a corresponding secondary memory through second ports of the K pins. Host; And Transmitting and receiving first packet data to and from the host through a first port of N (N is a positive integer) pins, and transmitting and receiving second packet data to and from a second port of K (K is an integer less than N) pins. And a memory module having at least one primary memory, a corresponding primary memory and at least one secondary memory receiving the second packet data through a third port of the K pins. 18. The memory system of claim 17 wherein K is one. 18. The memory system of claim 17 wherein the at least one primary memory comprises a cache memory that pre-stores predetermined data frequently accessed by the host. 18. The memory system of claim 17 wherein the memory system includes a cache memory between the host and the primary memory that pre-stores predetermined data frequently accessed by the host.

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