KR100909057B1 - Data driving device and method of liquid crystal display - Google Patents

Abstract

The present invention distributes the data output timing of the data driver by delaying the source output enable signals out of phase with each other in order to reduce the peak current of the data driver. Accordingly, the peak current of the data driver is reduced while being dispersed, thereby reducing EMI noise and power consumption due to the peak current, and stably driving the liquid crystal display.

Description

Data driving apparatus and method for a liquid crystal display device {APPARATUS AND METHOD FOR DRIVING DATA OF LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display device, and more particularly, to a data driving device and a method of a liquid crystal display device capable of minimizing electromagnetic interference noise by reducing an output peak current of a data driver.

The liquid crystal display displays an image by using the electrical and optical characteristics of the liquid crystal. Liquid crystals have different anisotropy in refractive index, dielectric constant, etc. according to molecular long axis direction and short axis direction, and can easily adjust molecular arrangement and optical properties. The liquid crystal display using the same displays an image by controlling the light transmittance by changing the arrangement direction of the liquid crystal molecules according to the size of the electric field.

The liquid crystal display includes a liquid crystal panel in which a plurality of pixels are arranged in a matrix, a gate driver driving a gate line of the liquid crystal panel, a data driver driving a data line of the liquid crystal panel, and the like.

Each pixel of the liquid crystal panel implements a desired color by using a combination of red, green, and blue subpixels that adjust light transmittance according to a data signal. Each subpixel includes a thin film transistor connected with a gate line and a data line, and a liquid crystal capacitor connected with the thin film transistor. The liquid crystal capacitor charges a difference voltage between the data signal supplied to the pixel electrode and the common voltage supplied to the common electrode through the thin film transistor and drives the liquid crystal according to the charged voltage to adjust the light transmittance.

The gate driver sequentially drives the gate lines of the liquid crystal panel.

Each time the gate lines are driven, the data driver converts the digital data signals into analog data signals and supplies them to the data lines of the liquid crystal panel. In this case, the data driver simultaneously outputs data signals Vout corresponding to one horizontal line in response to a Source Output Enable (SOE) signal as shown in FIG. 1. Due to the simultaneous output of the data signals Vout, a peak current in which the output current Iout rises sharply at the output timing of the data driver is generated.

Due to the high peak current of the data driver, electromagnetic interference (EMI) noise is generated in the conventional liquid crystal display. As the liquid crystal display becomes larger, the output channel and the load of the data driver are increased, and accordingly, the peak current of the data driver is further increased, thereby increasing the EMI noise. In addition, the high peak current of the data driver increases the power consumption, affects the liquid crystal panel, and may cause the gate line and the gate driver to malfunction.

Accordingly, an object of the present invention is to provide a data driving apparatus and method for a liquid crystal display device capable of stably driving the liquid crystal display device by reducing EMI noise and power consumption by dispersing peak currents of the data driver. .

To this end, the data driving device of the liquid crystal display according to the present invention includes a timing controller for supplying a reference source output enable signal and a source shift clock; A plurality of phase delayers for counting a source shift clock from the timing controller with different coefficients according to an option signal of an option pin, and delaying and outputting phases of the reference source output enable signal differently by different count coefficients; A plurality of data ICs for driving the data lines of the liquid crystal panel into a plurality of data blocks, the plurality of data in response to each of the plurality of source output enable signals output from the plurality of phase delayers in different phases. A data driver for distributing the data output timing of the IC is provided. Here, the plurality of phase retarders are mounted on a printed circuit board connected between the timing controller and the data driver, or embedded in each of the plurality of data ICs.

According to another aspect of the present invention, a data driving apparatus of a liquid crystal display includes: a timing controller configured to supply a reference source output enable signal and a source shift clock to first and second signal lines separated from each other; A first data driver connected to the first signal line and including a plurality of data ICs for driving the data lines of the first portion of the liquid crystal panel separately; A second data driver connected to the second signal line and including a plurality of data ICs for driving the data lines of the second portion of the liquid crystal panel separately; A plurality of phase delayers of a first group each embedded in data ICs of the first data driver to count the source shift clock to delay the reference source output enable signal from the first signal line to a different phase and; A plurality of phase delayers of a second group each embedded in the data ICs of the second data driver to count the source shift clock to delay the reference source output enable signal from the second signal line to a different phase The plurality of phase delayers may delay the reference source output enable signal to different phases in response to an option value of an option pin included in each of the plurality of data ICs.

The plurality of phase delayers delay the reference source output enable signal to different phases in response to an option value of an option pin included in each of the plurality of data ICs.

The phase differences of the multiple source output enable signals respectively output from the multiple phase delay units are equally set.

Phase delay times of the plurality of source output enable signals increase or decrease sequentially as the plurality of data ICs move away from the timing controller.

Each of the plurality of phase delayers may include a counter for counting a source shift clock supplied from the timing controller and outputting a plurality of clocks having different phases; A first multiplexer for selecting and outputting one of a plurality of clocks from a counter in response to the option value; A shift register configured to sequentially shift the reference source output enable signal in response to a clock from the first multiplexer to output a plurality of source output enable signals having different phases; And a first multiplexer for selecting and outputting one of a plurality of source output enable signals from the shift register in response to the option value.

A data driving method of a liquid crystal display according to another aspect of the present invention includes generating a reference source output enable signal and a source shift clock; A plurality of sources having different phases by counting a source shift clock from the timing controller with different coefficients according to an option signal of an option pin and delaying the phase of the reference source output enable signal by different count coefficients Generating an output enable signal; Distributing output timing of data output to the plurality of data lines in response to the plurality of source output enable signals.

The data driving apparatus and method of the liquid crystal display according to the present invention delay the phase of the SOE signal to distribute the output timing of the data signal so that the peak current of the data driver is reduced while being dispersed. Accordingly, EMI and power consumption due to the peak current of the data driver can be reduced, and malfunction of the gate line and the gate driver can be prevented.

Other features and advantages of the present invention in addition to the above features will become apparent from the following description of the preferred embodiments of the present invention with reference to the accompanying drawings.

2 is a block diagram schematically illustrating a data driving device of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 3 is a driving waveform diagram of the data driving device shown in FIG. 2.

The data driving device of the liquid crystal display shown in FIG. 2 includes a timing controller 2 for supplying control signals and image data including an SOE signal, and data lines DL of the liquid crystal panel under control of the timing controller 2. By delaying the phase of the SOE signal from the data driver 4 and the timing controller 2 including a plurality of integrated circuits (ICs) (D-IC1 to D-ICn) to be driven differently from each other. And a phase delay circuit 6 including a plurality of phase retarders D1 to Dn for controlling the data output timings of the plurality of data ICs D-IC1 to D-ICn to be distributed. FIG. 3 illustrates SOE1 to SOEn outputted with different phase delays from the output voltages Vout_1 to Vout_n, the output current Iout, and the plurality of phase delays D1 to Dn of the data driver 4 shown in FIG. Indicates.

The timing controller 2 sorts and supplies the image data from the outside to the data driver 4. In addition, the timing controller 2 controls a plurality of data drivers 4 by using a synchronization signal from the outside, for example, a data enable signal for notifying a valid section of data, and a dot clock for determining a data transmission frequency. The data control signal is generated and supplied, and at this time, a horizontal sync signal and a vertical sync signal from the outside may be further used. The plurality of data control signals include an SOE signal for controlling the data output period of the data driver 4, a source start pulse for instructing the start of data sampling, and a source shift clock (SSC) for controlling the sampling timing of the data. And a polarity control signal for controlling the polarity of the data voltage.

The plurality of phase retarders D1 to Dn included in the phase delay circuit 6 delay the SOE signals from the timing controller 2 to different phases so that the SOE1 to SOEn signals having different phases as shown in FIG. Print each one. Each of the plurality of phase delays D1 to Dn counts the SSCs from the timing controller 2 with different coefficients according to the option signal OP, and delays the phase of the SOE signal by different count coefficients so that SOE1 to SOEn Output each signal. Detailed circuits of the phase retarders D1 to Dn will be described later.

A plurality of data ICs D-IC1 to D-ICn of the data driver 4 generate a sequential sampling signal while shifting the source start pulse from the timing controller 2 in accordance with SSC in one horizontal period, The data from the timing controller 2 is sequentially latched in response to the sampling signal. Each of the plurality of data ICs (D-IC1 to D-ICn) parallelly latches data of one horizontal line latched sequentially in one horizontal period at the rising time of each of the SOE1 to SOEn signals of the next horizontal period. Convert to a signal. Each of the plurality of data ICs D-IC1 to D-ICn outputs an analog data signal at different data output timings in response to the polling time of each of the SOE1 to SOEn signals that are phase-delayed differently. DL). As a result, the output timings of the data of the plurality of data ICs D-IC1 to D-ICn are distributed, that is, the data voltages Vout_1 to Vout_n output from the plurality of data ICs D-IC1 to D-ICn. As the rising or falling timing is dispersed as shown in FIG. 3, the peak value of the output current Iout is also decreased while being dispersed. Therefore, the present invention can reduce EMI noise and power consumption due to the peak value of the output current Iout, and prevent malfunction of the liquid crystal panel.

On the other hand, the phase delay time of the SOE1 to SOEn signals is such that the data charge amount variation due to the output timing difference of the data voltages Vout_1 to Vout_n output from the plurality of data ICs D-IC1 to D-ICn does not appear. It is preferable to determine within a range that can sufficiently secure the data charging time of the field DL, for example, a range larger than 0 and smaller than 500 ns. Moreover, it is preferable that the phase difference of SOE1-SOEn signal is uniform.

The phase delay circuit 6 is mounted on a printed circuit board (PCB) (not shown) that relays the timing controller 2 and the data driver 4, or a plurality of data ICs (D-IC1 to D). -ICn) may be embedded in each.

4 is a block diagram schematically illustrating a data driving device of a liquid crystal display according to another exemplary embodiment of the present invention.

4 includes a plurality of data ICs (D-IC1 to D-IC4) commonly connected to the first SOE signal line 11 for supplying the SOE signal from the timing controller 10. FIG. A second including a plurality of data ICs (D-IC5 to D-IC8) commonly connected with the first data driver 32 and the second SOE signal line 13 for supplying the SOE signal from the timing controller 10. A data driver 34 is provided, and each of the plurality of data ICs D-IC1 to D-IC8 includes phase delayers D1 to D8 that delay the phase of the SOE signal differently from each other. In FIG. 4, only the SOE signal lines 11 and 13 connected between the timing controller 10 and the first and second data drivers 32 and 34 are omitted, and other signal lines are omitted.

The timing controller 10 sorts the data input from the outside and separates and outputs the first data to be supplied to the first data driver 32 and the second data to be supplied to the second data driver 34. In addition, the timing controller 10 separately supplies the first and second data control signals including the SOE signal to the first and second data drivers 32 and 34. The first data control signal is the same as the second data control signal.

The data ICs D-IC1 to D-IC4 of the first data driver 32 sequentially latch the first data from the timing controller 10, and at the same time, the data ICs of the second data driver 34. (D-IC5 to D-IC8) also sequentially latch the second data from the timing controller 10. FIG. The data ICs D-IC1 to D-IC8 convert the latched data into analog data in response to SOEs having different phase delay times by the built-in phase delayers D1 to D8. Analog data is fed to the corresponding data lines at different output timings.

Each of the phase retarders D1 to D8 built in the data ICs D-IC1 to D-IC8 delays the phase of the SOE signal differently in response to the option value S1S2S3. The option value S1S2S3 for determining the phase delay time depends on the power supply VCC and GND to which the three option pins S1, S2, and S3 are provided in each of the data ICs D-IC1 to D-IC8. Any one of "000" to "111". For example, when the option value S1S2S3 increases in the order of D-IC1, D-IC2, ... D-IC8 as shown in FIG. 4, the phase delay time of the SOE signal is also D-IC1, D-IC2,. Increment in order of D-IC8. In contrast, the data ICs of the first data driver 32 and D-IC4, D-IC5, D-IC3, D-IC6, D-IC2, D-IC7, D-IC1, and D-IC8 are used. In this order, the phase delay time of the option value S1S2S3, that is, the SOE signal may increase in the order in which the data ICs of the second data driver 34 are alternated. In the latter case, the phase delay time of the SOE signal set for each data IC is shown in Table 1 below, and the phase difference between the data ICs is preferably set equally in order to prevent data charge variation.

D-IC Option value (S1S2S3) Delay time1 Delay time2 D-IC4 000 10ns 20ns D-IC5 001 20ns 40ns D-IC3 010 30ns 60ns D-IC6 011 40ns 80ns D-IC2 100 50ns 100ns D-IC7 101 60ns 120 ns D-IC1 110 70ns 140ns D-IC8 111 80ns 160 ns

Accordingly, in the present invention, since the data output timings of the data ICs D-IC1 to D-IC8 are distributed in response to different phase delay times of the SOE, the peak value of the output current Iout is dispersed and decreased. Therefore, the present invention can reduce EMI noise and power consumption due to the peak value of the output current Iout, and prevent malfunction of the liquid crystal panel.

FIG. 5 is a block diagram showing an internal configuration of one of the phase retarders D1 to D8 shown in FIG. 4, and FIG. 6 is a detail of the binary counter 12 shown in FIG. 7 shows a detailed circuit of the shift register 16 shown in FIG.

The phase retarder illustrated in FIG. 5 counts SSCs and outputs four clocks CLK1 to CLK4 having different phases, and four clocks CLK1 output from the binary counter 12. SOE1 which is sequentially phase-delayed by shifting the SOE signal in response to a clock CLK from the first MUX 14 and a first multiplexer 14 to select and output any one of ~ CLK4). And a shift register 16 for outputting the SOE8 signal, and a second MUX 18 for selecting and outputting one of the SOE1 to SOE8 signals output from the shift register 16.

The binary counter 12 counts SSCs and outputs first to fourth clocks having different phases, that is, four-phase clocks CLK1 to CLK4. To this end, the binary counter 12 includes first to fourth JK flip-flops FF1 to FF4 as shown in FIG. 6. The SSC is commonly input to the clock terminals of the first to fourth JK flip-flops FF1 to FF4, and the AND gate 15 that performs an AND operation on the enable signal and the output Q of the previous flip-flop to the JK input terminal. ) Are supplied sequentially. Accordingly, the first to fourth JK flip-flops FF1 to FF4 count the SSCs and output the first to fourth clocks CLK1 to CLK4 in which the high state is shifted for each period T of the SSCs. Accordingly, each of the first to fourth clocks CLK1 to CLK4 has a period 4T corresponding to four times the SSC period, a duty ratio of 1/4, and shifts the phase by the SSC period T. Output from each of the first to fourth JK flip-flops (FF1 to FF4) in the form.

The first MUX 14 selects and shifts one of the first to fourth clocks CLK1 to CLK4 from the binary counter 12 in response to the option value S1S2 of the upper two bits among the option values S1S2S3. Output to register 16.

The shift register 16 sequentially shifts the SOE signal in response to the clock CLK output from the first MUX 14 to output SOE1 to SOE8 which are sequentially delayed in phase. To this end, the shift register 16 includes first to eighth JK flip-fills FF1 to FF8 connected to an input line of the SOE signal as shown in FIG. 7. The clock terminal of the first to fourth JK flip-flops FF1 to FF8 has one clock CLK among the first to fourth clocks CLK1 to CLK4 selected and output from the first MUX 14 in common. Is entered. The first JK flip-flop FF1 inputs the SOE signal to the J input terminal and the SOE signal inverted by the inverter to the K input terminal, and J, K of each of the second to eighth JK flip-flops FF1 to FF8. The input terminal is connected to the Q and QB output terminals of the previous flip-flop, respectively. Accordingly, the first to eighth JK flip-flops FF1 to FF8 sequentially output the SOE1 to SOE8 signals whose SOE signals are sequentially delayed by the high period of the clock CLK.

The second MUX 18 selects and outputs any one of the SOE1 to SOE8 signals output from the shift register 16 in response to the option value S1S2S3.

As a result, the plurality of data ICs (D-IC1 to D-IC8) of the present invention output data in response to each of SOE1 to SOEn delayed in different phases, so that the peak value of the output current is dispersed by dispersion of the data output timing. Can be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

It is a data drive waveform diagram of the conventional liquid crystal display of FIG.

2 is a block diagram schematically illustrating a data driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a driving waveform diagram of the data driving device shown in FIG. 2.

4 is a block diagram schematically illustrating a data driving device of a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 5 is a block diagram showing the internal configuration of one phase retarder shown in FIG.

FIG. 6 is a detailed circuit diagram of the binary counter shown in FIG. 5.

FIG. 7 is a detailed circuit diagram of the shift register shown in FIG. 5.

<Brief description of symbols for the main parts of the drawings>

2, 10: timing controller 11: first SOE signal line

12 binary counter 13 second SOE signal line

14: first MUX 16: shift register

18; 2nd MUX 32: 1st Data Driver

34: second data driver

Claims (8)

A timing controller for supplying a reference source output enable signal and a source shift clock; A plurality of phase delayers for counting a source shift clock from the timing controller with different coefficients according to an option signal of an option pin, and delaying and outputting the phases of the reference source output enable signal differently by different count coefficients; ; A plurality of data ICs for driving the data lines of the liquid crystal panel into a plurality of data blocks, the plurality of data in response to each of the plurality of source output enable signals output in different phases from the plurality of phase delayers. A data drive device for a liquid crystal display device comprising a data driver for dispersing the data output timing of the IC. The method according to claim 1, Many phase delayers And a data driver mounted on a printed circuit board connected between the timing controller and the data driver or embedded in each of the plurality of data ICs. A timing controller for supplying a reference source output enable signal to the first and second signal lines separated from each other; A first data driver connected to the first signal line and including a plurality of data ICs for driving the data lines of the first portion of the liquid crystal panel separately; A second data driver connected to the second signal line and including a plurality of data ICs for driving the data lines of the second portion of the liquid crystal panel separately; A plurality of phase delayers of a first group each embedded in data ICs of the first data driver to count a source shift clock to delay the reference source output enable signal from the first signal line to a different phase; ; A plurality of phase delays of a second group each embedded in data ICs of the second data driver to count a source shift clock to delay the reference source output enable signal from the second signal line to a different phase; Include, And the plurality of phase delayers delay the reference source output enable signal to different phases in response to an option value of an option pin included in each of the plurality of data ICs. delete The method according to any one of claims 1 and 3, And a phase difference between the plurality of source output enable signals respectively output from the plurality of phase delay units is equal. The method according to any one of claims 1 and 3, The phase delay time of the plurality of source output enable signals respectively output from the plurality of phase delay units increases or decreases as the plurality of data ICs move away from the timing controller. Data drive unit. The method according to claim 3, Each of the plurality of phase retarders A counter for counting a source shift clock supplied from the timing controller and outputting a plurality of clocks having different phases; A first multiplexer for selecting and outputting one of a plurality of clocks from a counter in response to the option value; A shift register configured to sequentially shift the reference source output enable signal in response to a clock from the first multiplexer to output a plurality of source output enable signals having different phases; And a second multiplexer for selecting and outputting one of a plurality of source output enable signals from the shift register in response to the option value. Generating a reference source output enable signal and a source shift clock; According to the option signal of the option pin, the source shift clock from the timing controller is counted with different coefficients, and the phase of the reference source output enable signal is delayed by different count coefficients. Generating a signal; And distributing output timings of data output to a plurality of data lines in response to the plurality of source output enable signals.

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