KR100903695B1 - Information setting method of nonvolatile storage device, and nonvolatile storage device - Google Patents

Abstract

The verify sense amplifier 19 reads data of the nonvolatile memory cell to be rewritten. The read data is compared with the expected data in the comparison circuit 21. As the rewrite is completed, the matching signal MCH is output from the comparing circuit 21. From the selector 23, the decode signal STR (i) / SWAP (i) of the volatile data holding unit 25 is output in correspondence with the nonvolatile memory cell MC to be rewritten. In accordance with the verify instruction signal PGV / ERV, the data read into the verify sense amplifier 19 is stored in the volatile data holding unit 25. If control is performed by the coincidence signal (MCH) in place of the verification instruction signal PGV / ERV, the data is stored and stored in the volatile data holding unit 25 in accordance with rewrite completion. There is no need to read back the operation information from the volatile storage.

Rewrite, Nonvolatile Memory, Volatile Memory, Operation Information

Description

Information setting method of nonvolatile memory and nonvolatile memory {INFORMATION SETTING METHOD OF NONVOLATILE STORAGE DEVICE, AND NONVOLATILE STORAGE DEVICE}

The present invention relates to setting of operation information in a nonvolatile memory device. In particular, the present invention relates to a technique for storing operation information in a nonvolatile storage area, and storing the operation information in a volatile data storage area during a power-on period.

In the semiconductor device disclosed in Patent Document 1, as shown in FIG. 7, the memory cell array 110 composed of non-volatile memory cells that can be electrically rewritten is used for storing initial setting data. An initial setting data area is provided. In addition, a bad column address register 190 is provided for storing a bad column address corresponding to a bad column generated in the memory cell array 110. In addition, trimming data registers 210 for storing the adjustment data used when generating various voltages in the internal voltage generation circuit 200 and the adjustment data used when generating various timing pulses in the timer circuit 220, respectively. 230 is installed.

By the wafer test, adjustment data for various voltages generated in the internal voltage generation circuit 200 and adjustment data for various timing pulses generated in the timer circuit 220 are stored in the trimming data registers 210 and 230. Bad column addresses are set in the bad column address register 190.

The contents of the data set in the trimming data registers 210 and 230 and the bad column address register 190 are stored as initial setting data in the initial setting data area in the memory cell array 110 composed of nonvolatile memory cells.

In addition, in the image input device disclosed in Patent Document 2 shown in Fig. 8, when the power switch is turned on and the system power is supplied, it is checked whether or not there is an update of control information from the remote control device or a computer to be connected externally. (S100, S200) If there is an update request, the control information stored in the RAM is updated according to the update request, or the new control information is stored in the RAM, and the update fact is stored in a predetermined position of the RAM ( S300).

When the power is turned off, the RAM is referenced to check whether the updated control information exists or does not exist (S500). If the update is made, the control information stored in the RAM is written to the EEPROM (S600). The voltage holding circuit is designed to maintain the system power supply voltage for a period of time after the power supply switch is turned off, at least until step S600 is completed.

Patent Document 1: Japanese Patent Application Laid-Open No. 2002-117699

Patent Document 2: Japanese Patent Application Laid-Open No. 1996-125914

Patent Documents 1 and 2 described above store various setting values and control information in various registers and RAM, such as the trimming data registers 210 and 230 and the bad column address register 190, and then store these various setting values as necessary. The present invention also relates to a technique for writing control information to the memory cell array 110 or the EEPROM.

However, the memory cell array 110 or the EEPROM is composed of nonvolatile memory cells, and these techniques sometimes require a lot of time because a predetermined bias voltage must be repeatedly applied to rewrite the data. Therefore, until the setting values / control information stored in the register or the RAM are stored in the memory cell array 110 or the EEPROM, the state in which the setting values or control information stored therebetween continue. When a long time is required for data rewriting of a nonvolatile memory cell, there is a fear that a mismatch between set values and control information may continue for a long time. This is a problem because in the circuit operation, an unstable state is maintained for a long time.

In addition, when rewriting data to a nonvolatile memory cell, a program operation (i.e., rewriting to change data to "0") is different from an erase operation (i.e., rewriting to change data to "1"). All are different from each other in terms of the bias voltage applied to the nonvolatile memory cell, the reference threshold voltage used in the verify operation for determining the rewrite state, and the operation sequence during the rewrite. Therefore, if the rewrite operation includes both changing data "0" to data "1" and changing data "1" to data "0", both the program operation and the erase operation must be performed. As a result, the rewrite time may be longer. This can further prolong the state in which the set values or the control information are inconsistent, resulting in a problem that the unstable state is maintained for a longer time in the circuit operation.

Further, Patent Document 1 relates to a technique for storing trimming information such as internal set voltages and timing pulses and redundancy address information such as bad column addresses in a nonvolatile memory cell by a vendor during wafer testing before shipment. However, no user setting information such as write protect information that the user should set properly is disclosed. When patent document 1 is applied to user setting information, there is a problem that a period in which user control information is inconsistent between various registers and nonvolatile memory cells continues.

In addition, according to Patent Document 2, the control information is updated at any time, but the updated control information is stored in the EEPROM as the power is shut off. Therefore, in order to continue to supply power even after a power supply interruption, the voltage holding circuit is provided. However, in order to enable the power supply even after the power is cut off, energy must be stored in the capacitor or the like, so that a circuit for maintaining the voltage at a predetermined voltage value during the power supply period also has a disadvantage. Depending on the time it takes to store data in the EEPROM and the amount of data to be stored, it may also be expected that a long time power supply is required. In such a case, there is a problem that a capacitor having a sufficient size and a regulator circuit for maintaining at a predetermined voltage value must be provided. As a result, the circuit size becomes larger and the consumption current also increases. do.

It is also conceivable to record the setting values and the control information in the nonvolatile storage area and then transfer them to a volatile data storage unit such as a register or a RAM. However, in this case, in order to read the set value and the control information from the nonvolatile storage area, readout (hereinafter referred to as read) access control is required. After writing the set value or the control information into the nonvolatile storage area, a read time is required to read back from the nonvolatile storage area until it is stored in the volatile data storage area. This is a problem because the updating of setting values and control information in the volatile data storage section is delayed.

Means to solve the problem

SUMMARY OF THE INVENTION The present invention solves at least one problem of the background art, wherein the operation information of the nonvolatile memory device is stored in the nonvolatile memory area and the same information as the operation information of the nonvolatile memory area during the power-on period. A nonvolatile memory device for storing operation information in a volatile data storage area, wherein the operation information is stored in the volatile data storage area without delay after the rewriting of the nonvolatile storage area is preceded in setting or updating the operation information. It is an object of the present invention to provide a method for setting information of a nonvolatile memory device capable of storing data and a nonvolatile memory device.

The information setting method of the nonvolatile memory device according to the present invention for achieving the above object includes a nonvolatile memory unit for storing operation information and a volatile memory unit for storing operation information stored in the nonvolatile memory unit during power supply. An information setting method of a nonvolatile memory device, comprising: rewriting a nonvolatile memory unit when setting or updating operation information; And at the end of the rewrite step, storing the operation information in the volatile storage unit on the basis of a logic signal according to the operation information held so that logic processing is possible. In addition, a nonvolatile memory device of the present invention for achieving the above object comprises a nonvolatile storage unit for storing operation information and a nonvolatile storage unit for storing operation information stored in the nonvolatile storage unit during power supply. In a volatile memory device, when setting or updating operation information, an identification unit for outputting a logic signal that can be processed logically in accordance with the operation information at the end of rewriting of the nonvolatile storage unit is provided, and is based on a logic signal output from the identification unit. The operation information is stored in the volatile memory.

The information setting method and nonvolatile memory device of the nonvolatile memory device according to the present invention includes a nonvolatile memory unit for storing operation information and a volatile memory unit for storing operation information stored in the nonvolatile memory unit during power supply. Doing. In the setting or updating of the operation information, rewriting of the nonvolatile storage unit is performed first, and at the time point when the rewriting is completed, the logic signal in accordance with the set or updated operation information is maintained in a logic process. On the basis of this logic signal, the operation information is stored in the volatile storage. In this case, a logical signal that can be processed logically is output by the identification section in accordance with the operation information.

Effects of the Invention

According to the present invention, the operation of storing the operation information to be set or updated in the nonvolatile storage unit is preceded, while the logic signal corresponding to the operation information is maintained in the nonvolatile storage unit at the time of completion of storage. When storing the information in the volatile storage, it is not necessary to perform an access operation for reading the operation information from the nonvolatile storage again. As a result, the setting or updating process of the operation information from storing the operation information in the nonvolatile storage to the operation information in the volatile storage can be performed very quickly.

The operating conditions of the nonvolatile memory device during the power supply period are set according to the operation information stored in the volatile storage unit. However, when the operation information is changed during the power supply period, the operation information is stored in the nonvolatile storage unit prior to storage. At this point in time, the contents of the volatile storage can be updated without delay and reflected in the circuit operation. Therefore, according to the present invention, there is a problem that the inconsistency period between the contents of the nonvolatile storage unit and the contents of the volatile storage unit becomes long when the contents of the volatile storage unit are changed first, the problem of ensuring the rewrite control of the nonvolatile storage unit after the power is cut off, and the like. At the same time, the operation information can be changed without delay, and the operating conditions can be changed quickly.

In addition, in setting or updating the operation information, the operation information stored in the volatile storage unit does not need to be read from the nonvolatile storage unit again, thereby reducing the current consumption due to the readout access operation. . Therefore, in setting or updating the operation information, the consumption current can be reduced.

1 is a circuit diagram according to a first embodiment.

2 is a first implementation of the selector of the first embodiment.

3 is a second embodiment of the selector of the first embodiment.

4 is a timing chart showing a program operation in the first embodiment.

Fig. 5 is a circuit block diagram of the second embodiment.

Fig. 6 is a circuit diagram of a volatile memory section and a circuit portion for performing write control to the volatile memory section of the second embodiment.

7 is a circuit block diagram of the semiconductor device of Patent Document 1. FIG.

8 is an operation flowchart of Patent Document 2. FIG.

9 is a detailed circuit of the volatile memory unit 25 of the first embodiment.

10 is a third implementation of the selector of the first embodiment.

Fig. 11 is a decode circuit of the Y decode signal SEL_Y (i) (i = 0 to 7).

Fig. 12 is a correspondence table of sector addresses, second operation information, and memory cells in the nonvolatile memory unit.

Fig. 13 is a correspondence table of sector addresses, first operation information, and memory cells in the nonvolatile memory unit.

Fig. 14 is a timing chart showing a read operation of first operation information and second operation information after power supply in the first embodiment.

Fig. 15 is a timing chart showing a program operation of operation information of sector O in the first embodiment.

Fig. 16 is a timing chart showing an erase operation of the selector's operation information in the first embodiment.

Explanation of the sign

11 nonvolatile memory

13 Word Driver

15 Y decoder

17 bias control circuit

19 proven sense amplifier

21 comparison circuit

23, 27 selector

25 volatile memory

Decoding section for 27A program

27B erasing decode section

29 Transmission data generator

BL (i) bit line group

D1, D2, D3 data lines

MC nonvolatile memory cells

WLTR, WLWP Word Line

ER clear indication signal

MCH match signal

PG (j) program indication signal

PGV, ERV Verification Indication Signal

SEL_TR, SEL_WP selection signal

SEL_Y (i) Y decode signal

STR (i), SWP (i) decode signal

T output timing signal

POR power supply detection signal

VERIFY verify mode signal

Hereinafter, an embodiment of the information setting method and the nonvolatile memory device of the nonvolatile memory device of the present invention will be described in detail with reference to FIGS.

In a nonvolatile memory device, when performing a circuit operation, operating conditions are set according to various operation information. Operation information is largely classified into two types.

The first operation information is information set by the vendor before the product is shipped and is information necessary for causing the nonvolatile memory device to perform a predetermined operation. For example, adjustment of bias voltage values used in various operations such as program operation, erase operation, read operation, adjustment of timing in various operations, adjustment of oscillation frequency of the built-in oscillator, and redundancy of defective memory cells. Redundancy address information and the like at the time of rescue may be considered. These operation information is determined in the test process before shipment.

The second operation information is information set in accordance with the use situation by the user, and is information necessary for customizing the nonvolatile memory device according to the function of the system. For example, when a memory cell array in a nonvolatile memory device is partitioned for each predetermined area and whether or not rewrite is possible for each partitioned area, a so-called sector or sector group write protection function is set. I can think of the case. It is also possible to set whether or not to rewrite operation information. In the case where it is desired to limit the degree of freedom of rewriting, it is conceivable to set a function for enabling rewriting only when a predetermined code input is accepted. These functions or predetermined codes are set by the user.

In the nonvolatile memory device, the above operation information needs to be maintained even after the power is turned off. This is because if the first operation information is not retained, the circuit operation set at the time of factory shipment cannot be maintained, which may cause problems such as deterioration of operation performance and inoperability. This is because if the second operation information is not retained, the performance and function of the system in which the nonvolatile memory device is mounted cannot be maintained. Therefore, the operation information set by the vendor or the user needs to be stored in the nonvolatile storage.

The operation information stored in the nonvolatile storage unit is appropriately referred to in accordance with the operation state of the nonvolatile storage unit, whereby the desired circuit operation is realized. These operation information are the information which is always referred to as the power is turned on, and the desired operating conditions must be secured, or the information should be set without delay depending on the operating state.

Examples of the operation information belonging to the former include adjustment of the bias voltage value, adjustment of the operation timing, adjustment of the oscillation frequency of the internal oscillator, redundancy address information, and the like. Depending on the power supply, the circuit parameters need to be fixed. The internal voltage generator circuit, the various timing circuits, the built-in oscillator, etc. need to be provided with various circuit constants without delay depending on the power supply, in order to have the adjusted voltage value, operation timing, and oscillation frequency. In addition, with respect to the redundancy address information, it is desirable to determine whether redundancy relief is necessary without delay with respect to the input address information, and the redundancy address information for the defective memory cell needs to be provided without delay depending on the power supply.

As the operation information belonging to the latter, there is information such as write protection information, rewrite restriction information, designation code information for rewriting permission, and the like. Such operation information is also preferably provided without delay for the access.

For this reason, some nonvolatile memory devices sometimes take a two-stage structure of the nonvolatile memory unit and the volatile memory unit to maintain operation information. In order to prevent the loss of operation information even after the power is cut off, a nonvolatile memory unit is provided, and the operation information is stored in the nonvolatile memory unit. The operation information is transferred from the nonvolatile memory to the volatile memory so that operation information is supplied without delay to the circuit operation during the power supply period. This transfer is performed in response to a reset operation to initialize the power supply or non-volatile memory. During the power supply period, various operating conditions are determined based on the operation information stored in the volatile storage. Also, even when the operation information stored in the nonvolatile storage unit is updated (changed) during the power supply period, the operation information (update information) input from the outside of the nonvolatile storage unit is first stored in the nonvolatile storage unit (that is, "update"). After the information previously stored in the memory cells of the nonvolatile storage unit is updated), then the same update information is also stored in the volatile storage unit. Therefore, even when operation information is updated during the power supply period, various operation conditions are determined based on the operation information of the updated volatile storage unit.

According to the above, the nonvolatile memory device can perform a desired circuit operation with reference to the operation information without delay in the circuit operation after the power supply and each operation request during the circuit operation.

At this time, the two-step memory structure of the nonvolatile memory unit and the volatile memory unit provided in the nonvolatile memory device has the following characteristics. The two-stage memory configuration described above is configured for a purpose different from that of a cache system, which is a multilayer memory configuration consisting of a main memory and a cache memory in a computer system, and thus has a different function and effect than a cache system. In addition, the main memory is generally composed of memory such as DRAM, and the cache memory is generally composed of memory such as SRAM. It is common for either to be composed of volatile memory.

That is, in a computer system, a multilayer memory system is configured to realize high speed memory access. In some areas of the main memory, a cache memory capable of high-speed access such as SRAM is provided, and high-speed data read / write is performed to the cache memory. As the movement of the access area and the amount of writing to the cache memory reach a predetermined level, data is read from the new data area of the main memory to the cache memory at an appropriate timing, and the contents of the cache memory are written to the main memory. Also, if the access request matches the address space maintained by the cache memory when there is an access request from the outside of the memory device, the cache memory is connected to the external I / O and provides high speed access. For this reason, cache memory is connected to external I / O.

In contrast to the memory system described above, the two-stage memory configuration included in the nonvolatile memory device has the following characteristics.

First, although a nonvolatile memory unit is provided to retain operation information even after the power is cut off, high-speed operation is required during a power supply period, and sufficient circuit operation may not be secured at an access speed of the nonvolatile memory unit. In order to compensate for this, a volatile memory unit is provided, and a limited access speed of the nonvolatile memory unit is compensated for. Therefore, the two-stage memory configuration is composed of a nonvolatile memory that enables the operation information to be retained even after the power is cut off, and a volatile memory that can provide the operation information to the internal circuit at high speed during the power supply period.

In addition, the same operation information is stored in the nonvolatile storage unit with or without power supply, and after the power supply, the same operation information is transferred to the volatile storage unit so that the operation information of the volatile storage unit is used to determine the operating conditions in the circuit operation. Therefore, the nonvolatile storage unit storing the operation information and the volatile storage unit storing the operation information have the same storage capacity.

Further, the flow of newly setting or updating the operation information is fixed such that the operation information is first stored in the nonvolatile storage unit and then stored in the volatile storage unit. The time taken to rewrite operation information in the nonvolatile memory is longer than the time taken to rewrite in the volatile memory. For example, the nonvolatile memory stores physical data such as charge and discharge of a floating gate. It has a mechanism. Volatile storage, on the other hand, has an electrical mechanism. According to the flow of one direction of the setting or updating, after the storage is completed in the nonvolatile storage unit, the operation information of the set or updated volatile storage unit is applied to the circuit operation, and the contents of the nonvolatile storage unit and the contents of the volatile storage unit are inconsistent. Can eliminate the period of time, thereby preventing the wrong circuit operation. Therefore, according to the one-way flow of setting or updating described above, the volatile storage unit is not connected to the external I / 0, and all the setting or update information of the volatile storage unit is received from the nonvolatile storage unit. In addition, the internal circuit which requires the operation information receives the operation information from the output of the volatile memory.

The two-step memory structure of the nonvolatile memory unit and the volatile memory unit is different from a cache system composed of volatile memory. The nonvolatile storage unit and the volatile storage unit have the same storage capacity, which is different from the cache system having the cache memory in a part of the main memory. In addition, the point that the flow of the operation information to be set or updated is fixed in the direction from the nonvolatile storage to the volatile storage differs from the cache system that is bidirectionally transferred between the main memory and the cache memory. The nonvolatile storage unit is connected to the external I / 0, and the volatile storage unit is not connected to the external I / 0, which is different from the cache system in which the cache is connected to the external I / 0.

The nonvolatile memory unit in which the operation information is stored may have the same nonvolatile memory cell structure as that of the memory cell array of the nonvolatile memory device indicating an address space as a storage area requested by the user. In this case, the nonvolatile memory may be arranged in the same area as the nonvolatile memory, or may be arranged in another area. To arrange in the same area is to share the well area, for example. By making the arrangement areas common, it is possible to arrange them in a compact area without unnecessary parts, without particularly providing a boundary area between the nonvolatile memory unit and the memory cell array of the nonvolatile memory device. In addition, in the nonvolatile memory cell of the nonvolatile memory unit and the nonvolatile memory cell of the memory cell array, any one of a configuration in which bit lines and / or word lines are separated or shared may be used. In the case of a separate structure, the nonvolatile storage unit and the memory cell array can each independently perform parallel access. The operation information stored in the nonvolatile storage can be updated without stopping the normal access operation on the address space which serves as a normal storage area used by the user. In the case of the shared configuration, the row / column decoder, the readout / rewrite control unit, and the like can be shared in the nonvolatile memory unit and the memory cell array, thereby improving the degree of integration.

The volatile memory may use a latch circuit or a register circuit. When it is comprised by a latch circuit or a register circuit, it can arrange | position adjacent to the circuit block which requires operation information, and it becomes possible to always read out and output operation information. This is preferably applied to the storage of operation information, such as a circuit constant or a redundancy address, which is the first operation information, which is always referenced during the power supply period after the power is turned on, and a desired operating condition is to be secured. In addition, the latch circuit and the register circuit are arranged in a so-called peripheral circuit region in which a circuit block composed of a logic control circuit or the like for controlling a memory cell array of a nonvolatile memory device is arranged. The layout pattern of the device in the peripheral circuit area has a looser line width and space width than the memory cell. This is because a logic control circuit does not have a redundancy function while a memory cell has a redundancy function. Therefore, the latch circuit and the register circuit are also laid out with a loose line width and a space width.

In addition, if the volatile memory unit has a RAM configuration in which volatile memory cells are arranged in an array shape with word lines and bit lines, and data reading and writing is performed in accordance with addressing, in the case of storing a large amount of operation information data. It is good to apply. In the case where the number of the areas where the write protection function is set is increased due to the increase in the capacity of the nonvolatile memory device due to the increase in the capacity of the mounted sector, the write protection information as the second operation information can be stored in the RAM. In this case, it is preferable to make the RAM structure a layout pattern with a fine pitch such as SRAM (which is substantially equivalent to a memory cell array of a nonvolatile memory device). Since the number of bits of operation information is much smaller than the number of memory cells in the nonvolatile memory device, considering the defect density, the redundancy function for the SRAM is practically unnecessary. In addition, the SRAM is disposed in the peripheral circuit, and the SRAM can provide the operation information at a high speed to the circuit requiring the operation information. The device area of the SRAM is much smaller than the latch circuit or the resistor circuit laid out with loose line width and space width, so that the die size can be reduced.

To rewrite a nonvolatile memory cell including the nonvolatile memory with new operation information, a program operation or an erase operation is performed. This rewrite operation is caused by a change in the threshold voltage of the nonvolatile memory cell, and the change in the threshold voltage is caused by charge discharge / injection into the floating gate by applying a bias to each terminal of the nonvolatile memory cell. The discharge / injection of the charge is performed by a physical phenomenon called the FN tunnel phenomenon / hot electron phenomenon, but the desired threshold value change is not obtained by one bias application, and the discharge / injection is performed by multiple bias applications. Is common. In addition, since the variation width of the threshold voltage due to the bias application is also uneven due to the characteristic nonuniformity of the nonvolatile memory cell, a verify operation for verifying the rewrite state is generally performed after the bias application. The rewrite state is determined by reading data stored in the nonvolatile memory cell to be rewritten by the verify operation.

In the first embodiment shown in Fig. 1, in the verification operation performed for each rewrite operation to the nonvolatile storage unit, data read from the nonvolatile memory cell to be rewritten is stored in the volatile storage unit. The storage operation is repeatedly performed in the volatile storage unit on the basis of a logic signal in accordance with the operation information held so that logic processing from the verification sense amplifier can be repeated for each verification operation after the rewrite operation. Alternatively, the storage operation is performed in the volatile storage unit based on the logic signal corresponding to the operation information held in the logic process from the verification sense amplifier in accordance with the verification agreement.

In the nonvolatile memory unit 11, nonvolatile memory cells MC are arranged in a matrix in a row direction / column direction. In the row direction, a plurality of non-volatile memory cells MC to be selectively controlled are arranged in alignment with each of the word lines WLTR and WLWP driven by the word drivers 13 and 13. In the first embodiment, the word drivers 13 and 13 are controlled according to the selection signals SEL_TR and SEL_WP. For example, it is assumed that the word line WLTR is activated by the selection signal SEL_TR, and the trimming information for adjusting the operating conditions of the circuit operation is stored in the nonvolatile memory cell MC selected in the word line WLTR. Similarly, the word line WLWP is activated by the selection signal SEL_WP, and the non-volatile memory cell MC selected in the word line WLWP is configured to set rewrite of a predetermined area (not shown) of a memory cell array such as a sector. It is assumed that write protection information is stored.

In the column direction, nonvolatile memory cells MC in the same column are connected by bit lines. The bit lines are divided into bit line groups from BL (1) to BL (M), each of which consists of N bit lines and constitutes a basic unit of access. The bit line groups BL (1) to BL (M) are connected to the data line D2 having an N bit width through the Y decoder 15. The Y decoder 15 is configured to include an NMOS transistor group between the bit lines group BL (1) to BL (M) with the data line D2 having an N bit width. The NMOS transistor group of the Y decoder 15 is electrically controlled by the Y decode signals SEL_Y (1) to SEL_Y (M) for each NMOS transistor group. One set of bit line groups BL (1) to BL (M) is connected to the data line D2.

The data line D2 is connected to a read sense amplifier (not shown), read access of data is performed, and connected to the data line D1 connected to the data terminal via the bias control circuit 17. It is also connected to the verification sense amplifier 19.

In response to the program instruction signal PG (j) (j = 1 to N) or the erase instruction signal ER, the bias control circuit 17 instructs whether the operation mode at the time of rewriting is a program operation or an erase operation. And a control circuit for applying a bias to the drain terminal of the nonvolatile memory cell MC from the data line D2 via the bit line. The program instruction signal PG (j) and the erase instruction signal ER are output from the command decoder 16. As the command signal CMD input from the outside is input to the command decoder 16, the command signal CMD is decoded, and the program instruction signal PG (j) and the erase instruction signal ER are output.

In the program operation, the bit position at which the program operation is to be performed is determined with respect to the data expected value input to the data line D1, and the program instruction signal PG (j) (j = 1 according to the bit line position in the corresponding bit line group). To N) is activated. This applies a bias to the corresponding data line D2. In the erase operation, a batch erase is performed, so that a bias is commonly applied to the data line D2 having a width of N bits. After the bias application is continued for a predetermined time, the verify instruction signal PGV / ERV is output to the verify sense amplifier 19.

The verify sense amplifier 19 amplifies the stored information stored in the nonvolatile memory cell MC during the rewrite operation read out to the data line D2 via the Y decoder 15. Each time the bias is applied, in response to the verify instruction signal PGV for the program operation or the verify instruction signal ERV for the erase operation, which are output from the bias control circuit 17, each reference has a corresponding threshold voltage. The memory cell is selected and the readout data is amplified.

The amplified data is input to the comparison circuit 21 and the volatile storage section 25 via the data line D3. Expected data is input to the comparison circuit 21 via the data line D1 and compared with the readout data amplified and output from the verification sense amplifier 19. If the rewrite is completed and the readout data matches the expected data, the comparing circuit 21 outputs the matching signal MCH.

The data read from the nonvolatile memory cell MC is stored in the storage area of the volatile memory 25 via the data line D3, and the storage area is selected by the selector 23. The verification instruction signals PGV / ERV, the selection signals SEL_TR and SEL_WP and the Y decode signals SEL_Y (i) (i = 1 to M) in the program operation / erase operation are input to the selector 23. Volatile for each of the nonvolatile memory cells MC connected to the bit line group BL (i) of the nonvolatile memory unit 11 selected by the selection signals SEL_TR and SEL_WP and the Y decode signal SEL_Y (i). The decode signal STR (i) or SWP (i) indicating the storage position of the storage unit 25 is output. In this case, the decode signal STR (i) / SWP (i) is output in response to the verify instruction signal PGV / ERV. By outputting the verification instruction signal PGV / ERV, the readout data amplified by the verification sense amplifier 19 (that is, a logic signal corresponding to the operation information held in a logic processable manner) is stored in the volatile memory unit 25. )

In addition, instead of the verification instruction signal PGV / ERV or in addition to the verification instruction signal PGV / ERV, the coincidence signal MCH output from the comparison circuit 21 may be input. By this, the rewrite operation is completed, and if the stored information stored in the nonvolatile memory cell MC to be rewritten matches the expected data, the decode signal STR (i) / SWP (i) is generated. Is output. The operation information is stored in the volatile memory section 25 only once when the rewrite is completed, and unnecessary storage operation is not performed. Therefore, unnecessary circuit operation can be stopped, and current consumption can be reduced.

In FIG. 1, i (i = 1 to M) represents the number of bit line groups BL (i). For example, it can consist of eight groups (M = 8). In addition, j (j = 1 to N) is the bit width of the bit lines constituting the bit line group, and is the bit width of the data lines D1, D2, and D3. For example, it can be configured with 16 bit width (N = 16).

In the first embodiment shown in FIG. 1, when rewriting the trimming information or the write protection information stored in the nonvolatile memory unit 11, the rewriting target is performed through a verification operation performed after bias application of the rewriting operation. The storage information read out from the nonvolatile memory cell MC is written into the volatile storage unit 25. According to this, when storing the operation information stored in the nonvolatile storage unit 11 in the volatile storage unit 25, after the rewrite is completed, the data is read back from the nonvolatile storage unit 11 by a readout sense amplifier (not shown). There is no need to read it. As a result, the lead-out time can be shortened.

Storing data in the volatile memory 25 may be repeated one or more times in response to the verification indication signal PGV / ERV which is repeated a plurality of times. Alternatively, in response to the matching signal MCH obtained as a result of the comparison with the expected data, the readout data when it is confirmed that the rewrite operation is completed may be stored. In the latter case, it is not necessary to store the stored information before rewriting reflecting the contents of the nonvolatile memory cell MC during rewriting, and unnecessary circuit operation can be reduced to reduce current consumption.

2 and 3 are specific examples of the selector 23. The selection signals SEL_TR, SEL_WP and the Y decode signal SEL_Y (i) (i = 1 to M) are respectively combined and input to the NAND gate. The output timing signal T is input to each NAND gate in common. At the timing when the output timing signal T becomes high and is activated, any decode signal STR (i) / SWP (i) selected by the selection signals SEL_TR, SEL_WP and the Y decode signal SEL_Y (i) is activated to a high level. Is output.

In the case of FIG. 2, the output timing signal T is logic-operated by the verification instruction signals PGV and ERV through the Noah gate and the inverter gate, input to the NAND gate together with the coincidence signal MCH, and then logic through the inverter gate. It is output as a multiplied signal. Regardless of the type of the program operation and the erasing operation, the output timing signal T is output when it is determined that the rewrite operation is completed as the timing at which the instruction of the verify operation is output. The readout data that confirms completion of rewrite is stored in the volatile storage unit 25 as it is. The output timing signal T is output only once at the timing of completion of rewrite to store data.

In the case of FIG. 3, the output timing signal T is output as a signal in which the verification instruction signals PGV and ERV are ORed through the NOA gate and the inverter gate. Regardless of the type of the program operation and the erase operation, the output timing signal T is output for each timing at which the instruction of the verify operation is output. In each of the bias applications, read data for confirming the rewrite state is stored in the volatile storage unit 25. At the timing of rewrite completion, the rewritten data is stored.

4 shows a timing chart of a program operation with respect to operation information. This is a timing chart when the selector 23 has the configuration shown in FIG. 2. For example, a program command for setting operation information, such as trimming information for adjusting operation conditions, write protection information, or the like, is input together with address information ADD (when the set operation information is write protection information, the address is entered. Information indicates sectors for which write protection is to be set). In response to the program command, the selection signals SEL_TR, SEL_WP, and the Y decode signal SEL_Y (i) (i = 1 to M) are output in accordance with the target operation information.

Prior to the program operation, a nonvolatile connected to the bit line group BL (i) (i = 1 to M) selected by the Y decode signal SEL_Y (i) (i = 1 to M) and selected by the selection signals SEL_TR and SEL_WP. Data of the memory cell MC is read by the verify sense amplifier 19 as the verify instruction signal PGV becomes high level. Each readout data is compared with expected data in comparison circuit 21, and a check is performed on a bit basis to determine whether each nonvolatile memory cell is in a program state.

As a result of the determination, a program operation is performed on the nonvolatile memory cell MC that is not in the programmed state. The bit line to which this nonvolatile memory cell MC is connected is one of the N bit lines in the bit line group BL (i), but the bit line is the program instruction signal PG (j) (j = 1 to N). Is selected, and a program bias voltage is applied to the bit line. After the bias is applied, data is read from the nonvolatile memory cell MC by the high level verify instruction signal PGV and compared with expected data. The bias application and data comparison are alternately repeated until the comparison results match. The data stored in the nonvolatile memory cell MC to be programmed is compared with the expected data, and in turn, a bias is applied and a program operation is performed. When the read data coincides with the expected data, the program operation is completed and a high level coincidence signal MCH is output. According to the output of the coincidence signal MCH, the decode signals STR (i) / SWP (i) selected by the Y decode signals SEL_Y (i) (i = 1 to M) and the selection signals SEL_TR and SEL_WP are Output is at high level. Read data when the coincidence signal MCH is output is stored in the volatile storage unit 25 selected by the decode signal STR (i) / SWP (i).

At this time, the timing chart in the case of having the configuration of FIG. 3 as the selector 23 is not shown. However, the Y decode signal SEL_Y (i) (i = 1 to M) for each timing at which the verify instruction signal PCV becomes a high level. And the decode signal STR (i) / SWP (i) selected by the selection signals SEL_TR and SEL_WP are output at a high level. For each verification operation after bias application, the decode signal STR (i) / SWP (i) is output, and the read data is stored in the volatile storage 25.

Moreover, although the timing chart of the erase operation | movement with respect to operation information is not shown, performing the erase operation collectively with respect to all the nonvolatile memory cells MC of the nonvolatile memory part 11, the bias voltage for a program, The same operation as the timing chart of the program operation is performed except that another erase bias voltage is applied. That is, as the Y decode signal SEL_Y (i) (i = 1 to M) is sequentially increased, the nonvolatile connected to the bit line group BL (i) selected by the respective Y decode signal SEL Y (i). An erase operation is performed on the memory cell MC. As in FIG. 4, the application of the erase bias voltage according to the erase instruction signal ER and the verify operation according to the verify instruction signal ERV subsequent thereto are performed repeatedly, and at the time when the read data matches the expected data, the erase operation is performed. Is completed, a high level coincidence signal MCH is output. In response to the output of the coincidence signal MCH, the decode signal STR (i) / SWP (i) selected by the Y decode signal SEL_Y (i) and the select signals SEL_TR, SEL_WP are output at a high level. The read data when the coincidence signal MCH is output is stored in the volatile storage unit 25 selected by the decode signal STR (i) / SWP (i).

In the erase operation as in the case of the program operation, the decode signal STR (i) / SWP (i) is output for each verify operation after bias is applied, and the operation of storing the readout data in the volatile memory 25 can be realized. Needless to say.

If the data stored in the nonvolatile memory cell MC are not inverted through the rewrite, the original data will be read. In the state where rewriting is not completed, the nonvolatile memory device preferably operates based on the operation information before the change, and the volatile storage unit continues to store the previous operation information. In the state where the write operation is incomplete, even if the data read by the verify operation is stored in the volatile storage, the stored contents will be unchanged and the set operation information will not be changed.

The initial setting of the operation information is transferred and stored from the nonvolatile memory to the volatile memory in accordance with the power-on. More detailed specific examples of the embodiment of FIG. 1 incorporating this function are shown in FIGS.

9 is a detailed circuit of the volatile storage unit 25 shown in FIG. As described later with reference to FIG. 10, the volatile memory unit 25 stores data stored in the storage area, read from the nonvolatile memory cell MC and transferred to the verification sense amplifier 19 via the data line D3. The storage area is configured to be selected in the manner described in the third embodiment of the selector 23 of FIG. 9, the transistors N10 and N11 are turned on by the decoded signals STR (i) / SWP (i) indicating the storage positions of the volatile storage, and the information on the data line D3 is latched. It is transmitted to and maintained at L10. The transistor N12 is a compensation element of the N-channel transistor N10, compensates for the decrease in the N10 output voltage due to the threshold when the information on the data line D3 is "1", and inverts the latch circuit L10. Accelerate

N12 is not necessary when installing a P-channel transistor in parallel with N10.

FIG. 10: is a 3rd specific example of the selector 23 shown in FIG. 1, and it is a case where M = 8. 9 is a selector circuit for selecting the volatile memory of FIG. 2, the selector includes a logic gate N100 to which a power supply detection signal POR is input. According to the power supply, the power supply detection signal (POR) is activated, and the operation information sequentially transmitted from the nonvolatile memory to the volatile memory is sequentially selected by the selection signals SEL_TR, SEL_WP, and the Y decode signal SEL_Y (i). Put in wealth.

That is, the selector acts by the logic gates N100 and N103 in the initial setting of the operation information after power supply. In addition, at the time of rewriting operation information by the user, the selector acts on the logic gates N101, Nl02, and Nl03 as shown in FIG. 2 described above. At this time, the signal VERIFY in FIG. 10 is a signal in which the verification instruction signals PGV and ERV are ORed through the NOA gate and the inverter gate and outputted in FIG. 2.

As shown in Fig. 11, the Y decode signal SEL_Y (i) (i = 0 to 7) is a logical sum of the decode logic output of the sector addresses SA (0) to SA (6) and the selection signals SEL_TR and SEL_WP described later. Is generated from the output.

12 is a correspondence table of sector addresses, second operation information, and memory cells in the nonvolatile memory unit. The sector addresses SA (0) to SA (6) and the protection information, which is the second operation information of each sector, are assigned to any column address on the word line WLWP of the nonvolatile memory in SEL_Y (i) (i = 1 to 8), and It indicates which I / O is stored in D2 (0) to (l5). In this example, the sector has 128 sectors from 0 to 127. For example, when programming sector 0, select SEL_Y (0) and program only D2 (0) of the 16 data buses.

13 is a correspondence table of sector addresses, first operation information, and memory cells in the nonvolatile memory unit. The sector addresses SA (0) to SA6 and the trimming data which is the first operation information are stored in which I / Os of which column addresses on the word line WLTR of the nonvolatile storage unit. In this example, the trimming information has 128 bits from 0 to 127. In this case, the sector address is used for addressing when programming the trimming data. Rewriting of each data, which is the first operation information and the second operation information, is made to the nonvolatile storage unit. Each operation information is read out from the nonvolatile memory at the time of power supply and stored in the volatile memory. Therefore, the circuit which performs the operation using the protection information or the trimming information does not directly read the operation information from the nonvolatile memory unit every time, but performs the operation by referring to the operation information held by the volatile memory unit. It is shown in FIG.

14 is a timing chart showing a read operation of the first operation information and the second operation information after power supply in the first embodiment. The power supply detection signal POR signal is a signal that becomes high when the device is powered on and reads the information in the nonvolatile storage unit and stores the information in the nonvolatile storage unit. In this example, when starting, SEL_TR = High is first selected, and then SEL_Y (i) (i = 0 to 7) is sequentially selected to read redundancy address information and trimming information from the nonvolatile memory unit, and stored in the volatile storage unit. Subsequently, SEL_WP = High, so that the protection information is read from the nonvolatile storage unit and stored in the volatile storage unit.

Sector protection information stored in the volatile storage unit is always output to the signal lines of the WP (0) to WP 127, and redundancy address information and trimming information are always output to the signal lines of the TR (0) to TR 127. The circuit operated by the operation information can always refer to these signals to perform the operation. For example, in the case of programming or erasing sector O, the operation information of the WP (0) is first referred to, and control is performed so as not to program or erase if the protection is applied. If the trimming information of the oscillator period is allocated to TR (0) to TR (2), control is made to change the period according to the TR (0) to TR (2) states.

15 shows, for example, a program operation waveform of operation information of sector 0 in the first embodiment. This changes the data of a nonvolatile memory cell that stores operation information corresponding to sector 0 of the nonvolatile memory from "1" to "0". In this case, the program information needs to be retained even when the power supply is cut off, so that the program is executed at a pre-assigned address of the nonvolatile storage unit. In the case of sector 0, SEL_Y (0) is selected, and a program is performed on I / O to which D2 (0) is connected among 16 bit lines connected to word line WLWP selected by SEL_WP. A verification operation that actually reads from the nonvolatile storage to verify that the program has been completed and verifies is performed, and the program operation is repeated until the verification passes. If the verification passes, the readout data at that point is already output on the data bus D3 by the verification amplifier. Therefore, the SWP (0) is set high and stored in the volatile memory. The contents of the written nonvolatile memory can be stored in the volatile memory to immediately reflect the rewrite operation information. The same applies to the program of redundancy and trimming information.

Fig. 16 shows an erase operation waveform of operation information of a sector in the first embodiment. In this case, unlike the above program, the erase operation collectively erases operation information of all sectors. This changes the data of 128 nonvolatile memory cells that store operation information corresponding to sectors of the nonvolatile storage unit from "0" to "1". Therefore, the verify operation is also performed with respect to the operation information of all the erased sectors. As in the case of the program, a verification operation is performed to actually read and verify whether the erasing is completed from the nonvolatile storage unit, and the erase operation is repeated until the verification passes. If the verification passes, the readout data at that point is already output on the data bus D3 by the verification amplifier. Therefore, the SWP is set high and stored in the volatile memory, thereby rewriting. The contents of the volatile storage unit can be stored in the volatile storage unit to immediately reflect the rewrite operation information. This is done with respect to the protection information of all sectors. The same applies to the redundancy and erasing of the trimming information.

In the second embodiment shown in Fig. 5, the data after the rewrite is determined in accordance with the type of the rewrite operation to the nonvolatile memory unit, and upon completion of the rewrite operation, in accordance with the instruction signal of the rewrite operation. This is the case where the determined data is stored in the volatile storage. That is, the rewriting of data in the nonvolatile memory cell is performed by the transition of data, such as a program operation that is a rewrite of data "1" to "0" and an erase operation that is a rewrite of data "O" to "1". The direction is determined, using the characteristics of the rewrite of the nonvolatile memory cell As the command signal CMD input from the outside is input to the command decoder 16, the command signal CMD is decoded and the program is decoded. The instruction signal PG (j) and the erase instruction signal ER are outputted as the logic signal in accordance with the operation information held by the program instruction signal PC (j) and the erase instruction signal ER in a logic processable manner. It is held in the command decoder 16 and controls the inversion of the stored data in the volatile storage.

The circuit block diagram of the second embodiment shown in FIG. 5 is provided with a selector 27 and a transfer data generation unit 29 in place of the selector 23 in the circuit block diagram (FIG. 1) of the first embodiment. .

The selector 27 matches the outputs from the selection signals SEL_TR, SEL_WP, the Y decode signal SEL_Y (i) (i = 1 to M), the program instruction signal PG (j) (j = 1 to N) and the comparison circuit 21. The signal MCH is input. For each nonvolatile memory cell MC connected to the bit line group BL (i) of the nonvolatile memory 11 selected by the selection signals SEL_TR, SEL_WP and the Y decode signal SEL_Y (i), the volatile storage 25 The decode signal STR (i) / SWP (i) indicating the storage position of the " In the case of a program operation, among the N bit lines in the bit line group BL (i), the bit line to which the nonvolatile memory cell MC to be programmed is connected is selected. In this case, the output of the decode signal STR (i) / SWP (i) is output as the coincidence signal MCH becomes high level. At the completion of the rewrite, the data storage position in the volatile storage unit 25 is instructed.

The transmission data generating unit 29 receives the coincidence signal MCH and the program instruction signal PG (j) (j = 1 to N) / erase instruction signal ER, and bit in accordance with the output of the coincidence signal MCH. Data is output corresponding to the N bit lines constituting the line group BL (i). Of the N bit lines, all bit lines constituting the bit line group BL (i) for generating data in a program state corresponding to a bit line to which a nonvolatile memory cell MC to be programmed is connected or for an erase operation. In response to this, the erased data is generated.

Thereby, in response to the output of the coincidence signal MCH indicating completion of the rewrite operation, the selector 27 outputs the decode signal STR (i) / SWP (i) corresponding to the rewrite target, and simultaneously generates transmission data. In the unit 29, data according to the rewrite operation can be output according to the bit position of the object to be rewritten.

6 shows a circuit example in which the volatile storage section 25, the selector 27 and the transfer data generation section 29 are embodied. A circuit configuration for storing one bit of data is shown.

The volatile memory section 25 has a shift register configuration in which two latch circuits L1 and L2 are connected with a transfer gate T2 interposed therebetween. The input terminal D is connected to the latch circuit L1 via the transfer gate T1, and the latch circuit L2 is connected to the output terminal Q. Although not shown, the volatile storage section 25 has a configuration in which the output terminal Q is connected to the input terminal D of the next volatile storage section 25, and is connected in series to multiple stages, and the volatile storage section 25 of the first stage is provided. Is a configuration in which data is transmitted in sequence from an input terminal of (). At the time of power supply, operation information stored in the nonvolatile memory unit 11 is read out from the first input terminal D, and transferred in order, and stored in the volatile memory unit 25.

In the storage node N1 of the latch circuit L1 and the storage node N2 of the latch circuit L2, respectively, the PMOS transistors P1 and P2 are connected between the power supply voltage VCC and the ground potential. NMOS transistors N1 and N2 are connected. The inverter gate I1 is connected from the gate terminal of the NMOS transistor N2 toward the gate terminal of the PMOS transistor P1, and the inverter gate I2 is connected from the gate terminal of the NMOS transistor N1 toward the gate terminal of the PMOS transistor P2. Is connected. The transfer data generator 29 is configured by the PMOS transistors P1 and P2, the NMOS transistors N1 and N2, and the inverter gates I1 and I2.

The selector 27 is a program decoding section 27A for driving the NMOS transistor N1 and the inverter gate I2 and an erasing decoding section 27B for driving the NMOS transistor N2 and the inverter gate I1. Consists of. The former program decoding section 27A includes one of the program instruction signals PG (j) (j = 1 to N), the coincidence signal MCH, the selection signal SEL_TR or SEL_WP and the Y decode signal SEL_Y (i) (i = One signal of 1 to M) is input to the NAND gate, and the decoded signal is output from the NAND gate via the inverter gate. In the latter erasing decoding unit 27B, the erasing instruction signal ER and the coincidence signal MCH are input to the NAND gate, and the decoded signal is output from the NAND gate via the inverter gate.

In the program decoding section 27A, a set of bit line groups BL (i) (i = 1 to M) are selected according to the Y decode signal SEL_Y (i), and the selected bit lines in accordance with the selection signal SEL_TR or SEL_WP. The row direction position of the nonvolatile memory cell MC to be connected to the group BL (i) is determined. Further, according to the program instruction signal PG (j), the nonvolatile memory cell MC to be programmed is determined among the selected nonvolatile memory cells MC. A volatile memory unit 25 is provided for each nonvolatile memory cell MC disposed in the nonvolatile memory unit 11. Of the program decoding units 27A that can be provided for each of the volatile storage units 25, any one of the program decoding units 27A is in accordance with the combination of the signals according to the output of the high level signal of the coincidence signal MCH. The NMOS transistor N1 and the PMOS transistor P2 are conducted by being activated and outputting a high level. The low level is stored in the storage node N1, and the high level is stored in the storage node N2. The output terminal Q of the volatile storage section 25 is held as a low level signal, and data "0" indicating a program state is output.

In the erasing decoding section 27B, all the nonvolatile memory cells MC arranged in the nonvolatile storage section 11 are erased in a batch. Therefore, also in the corresponding volatile memory 25, it is necessary to store data "1" that is indicative of the erase state uniformly regardless of the Y decode signal SEL_Y (i) and the selection signals SEL_TR and SEL_WP. All of the erasing decoding sections 27B provided for each section 25 are activated in accordance with the output of the high level signal of the coincidence signal MCH and output a high level, so that the NMOS transistor N2 and the PMOS transistor P1 become conductive. A high level is stored in the storage node N1 and a low level in the storage node N2. The output terminal Q of all the volatile storages 25 is held as a high level signal to indicate the erase state. Is output.

At this time, the verification sense amplifier 19 is an example of an identification unit and an amplifier, and is an example of a logic signal in accordance with operation information in which the readout data amplified and output from the verification sense amplifier 19 is maintained in a logic process. In addition, the command decoder 16 is an example of an identification unit and a rewrite control unit, and operation information in which the program instruction signal PG (j) and the erase instruction signal ER output from the command decoder 16 are maintained in a logic process. It is an example of a logic signal according to the present invention. The comparison circuit 21 is an example of the coincidence determination unit or the completion determination unit. The transmission data generation unit 29 is an example of the rewrite information indicating unit.

When the data stored in the nonvolatile memory cell MC are not inverted through rewrite, the operation information stored in the volatile storage unit is also converted into previous information by the matching signal MCH indicating completion of the rewrite operation. maintain. In the state where rewriting is not completed, it is preferable that the nonvolatile memory device operates based on the operation information before the change.

As can be seen from the above description, according to the present embodiment, operation information such as trimming information or write protection information is stored in the nonvolatile storage unit 11 when it is set after the power supply or updated during the power supply period. Preced the action. In the first embodiment, since data from the rewritten nonvolatile memory cell MC is read into the verification sense amplifier 19 at the time of completion of storage, according to the output of the coincidence signal MCH indicating completion of rewrite. The readout data can be transferred to the volatile storage 25. In the second embodiment, a rewrite is a program operation or an erase operation, and the logical value of the data rewritten in each is known. That is, when the program operation is completed, the rewritten data becomes "0", and when the erase operation is completed, the rewritten data becomes "1". Accordingly, according to the program instruction signal PG (j) (j = 1 to N) or the erase instruction signal ER, the logic value of the data after the rewrite can be determined, and the output of the coincidence signal MCH indicating completion of the rewrite. In this way, the data that can be determined in advance can be stored in the volatile storage unit 25.

The read access operation of the operation information from the nonvolatile memory unit 11 is performed only at the time of power supply or at the reset operation of initializing the nonvolatile memory device. When there is an update of the operation information or the like during the power supply period, It is not necessary to read again after the storage of the nonvolatile storage unit 11, and operation information can be stored in the volatile storage unit 25. The reread operation of the operation information from the nonvolatile storage unit 11 becomes unnecessary, and the update time of the operation information can be shortened. In the shipment test of the nonvolatile memory device, the time for storing redundancy address information and various trimming information can be shortened, and the shipment test time can be shortened. In addition, after being put into the application system, it is possible to shorten the update time in operation information such as write protection information whose settings are changed in accordance with the requirements of the system.

It is conceivable that the number of defective memory cells to be repaired for redundancy increases and the number of partitions of a memory area such as a sector to which a write protection function is applied increases as the capacity of the nonvolatile memory device increases and the performance increases. It is also conceivable that the circuit function to adjust the operating conditions increases. It is conceivable to increase operation information such as redundancy address information, write protection information, and various trimming information to be stored in the nonvolatile storage unit. In this case, if the storage function of the operation information of the present embodiment is provided, the operation information can be set or updated quickly.

During the power supply period, when the operation information for determining the operation conditions of the circuit is changed, at the time when the storage is completed in the nonvolatile storage unit 11, the contents of the volatile storage unit 25 are immediately updated and reflected in the circuit operation. can do. In addition, since it is not necessary to perform the read access operation after storing the operation information in the nonvolatile storage unit 11, there is no current consumption in accordance with the read access operation. The current consumption can be reduced in the processing of setting or updating operation information.

In addition, this invention is not limited to the said Example, Needless to say that various improvement and modification are possible in the range which does not deviate from the meaning of this invention. For example, the trimming information and the write protection information have been described in the case where the storage in the nonvolatile storage unit and the subsequent storage in the volatile storage unit are described, for example. However, the present invention is not limited thereto. . The same can be applied to other operation information such as redundancy address information.

The second operation information may be information such as read protection information, read restriction information, designation code information for allowing read, and the like.

Claims (15)

An information setting method of a nonvolatile memory device comprising: a nonvolatile memory unit for storing operation information; and a volatile memory unit for storing the operation information stored in the nonvolatile memory unit during power supply. Rewriting the nonvolatile memory unit when the operation information is set or updated; And At the end of the rewrite step, storing the operation information in the volatile storage unit on the basis of a logic signal according to the operation information held in a logic processable manner; Information setting method of the nonvolatile memory device comprising a. The method of claim 1, The rewrite step, Applying a bias to the nonvolatile memory; And Reading out the stored information being rewritten by the bias applying step, as the stored information in the nonvolatile storage unit; Including; The logic signal according to the operation information is the storage information, and the storage information is stored in the volatile memory. The method of claim 2, The bias applying step and the reading step are alternately repeated until the operation information is stored in the nonvolatile memory unit, The storing of the stored information in the volatile storage unit is performed for each read step. The method of claim 2, Determining whether the stored information read out by the reading step is consistent with the operation information, And the storing information is stored in the volatile storage unit in accordance with the result of the determination step. The method of claim 1, The setting or updating of the operation information is performed according to a rewrite indication signal. Determining whether or not the rewrite step is completed; And the logic signal according to the operation information is the rewrite instruction signal. The method of claim 5, wherein And determining the operation information to be stored in the volatile memory according to the rewrite instruction signal. The method of claim 5, wherein And the rewrite instruction signal is a program instruction signal or an erase instruction signal. The method of claim 1, And said operation information stored in said non-volatile memory is transferred to said volatile memory in accordance with power supply. A nonvolatile memory device having a nonvolatile memory for storing operation information and a volatile memory for storing the operation information stored in the nonvolatile memory during power supply. When the operation information is set or updated, an identification unit for outputting a logic signal that can be logically processed in accordance with the operation information at the end of rewriting of the nonvolatile memory unit, And the operation information is stored in the volatile storage unit on the basis of the logic signal output from the identification unit. The method of claim 9, The identification unit is an amplifier for reading out the stored information in the nonvolatile memory unit, The logic signal output from the identification unit is the stored information read by the amplifier, And the storage information is stored in the volatile memory unit. The method of claim 10, Rewriting of the nonvolatile memory unit is repeated until the storage information read out by the amplifier matches the operation information, The storing of the stored information in the volatile memory is performed whenever the stored information is read by the amplifier. The method of claim 10, And a coincidence determination section for determining whether the stored information read out by the amplifier is consistent with the operation information, The storing of the storage information in the volatile storage unit is performed according to a matching result by the matching determination unit. The method of claim 9, A completion judging unit which determines whether or not rewriting of the nonvolatile storage unit is completed; The identification unit is a rewrite control unit for performing a rewrite control in accordance with the transition direction of the operation information is set or updated, The logic signal output from the identification unit is a rewrite instruction signal set by the rewrite control unit according to the transition direction of the operation information, And the operation information according to the rewrite instruction signal is stored in the volatile storage unit according to the determination by the completion determination unit. The method of claim 13, And a rewrite information indicating unit for indicating the operation information to be stored in the volatile storage unit in accordance with the rewrite instruction signal. The method of claim 13, And the rewrite instruction signal is a program instruction signal or an erase instruction signal.

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