KR100900058B1 - Method and Circuit Operation for Motion Estimation of Deverse Multimedia Codec - Google Patents

Abstract

The present invention relates to a motion estimation calculation method and a calculation circuit used in various multimedia codecs such as MPEG-2, MPEG-4 and H.264 / AVC next generation multimedia codec. The present invention provides a motion estimation algorithm and a calculation circuit that reduce the amount of computation and power consumption used in a multimedia codec by estimating the motion of adjacent M × N blocks by sharing one search area in a motion estimation process.

H.264 / AVC, Motion Estimation, Motion Estimation (ME), Memory Reuse Algorithm, Data Reuse Algorithm

Description

Motion Estimation Algorithm Used in Various Multimedia Codecs and Its Circuits [Method and Circuit Operation for Motion Estimation of Deverse Multimedia Codec}

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing the overall configuration of an encoder of a conventional H.264 / AVC.

2 is a diagram illustrating a method for obtaining a search area center of a conventional current block.

3 is a diagram illustrating the amount of computation of each block of a conventional encoder.

4 is a diagram showing the amount of computation of each block of a conventional decoder.

5 is a diagram illustrating a process of finding a block that most matches a current block in a search area of a current block expanded in a reference frame according to the present invention.

FIG. 6 is a diagram illustrating regions overlapping each other between a current block and a search area of three adjacent blocks according to the present invention; FIG.

FIG. 7 is a diagram illustrating a process of finding, in a search region of a current block, the most matching block of three blocks adjacent to the current block according to the present invention; FIG.

8 is a diagram illustrating a motion estimation calculation circuit used in various multimedia codecs according to the present invention.

9 is a diagram showing the configuration of a calculation unit for obtaining SAD values of 4x1 blocks in a motion estimation calculation circuit used in various multimedia codecs according to the present invention.

FIG. 10 is a diagram illustrating a configuration of a buffer for storing SAD values of 4 × 1 blocks in a motion estimation arithmetic circuit used in various multimedia codecs according to the present invention. FIG.

11 is a diagram illustrating SAD operation of pixel data in a search region of a reference frame and pixel data of a current block in a motion estimation arithmetic operation circuit used in various multimedia codecs according to the present invention.

<Description of Symbols for Major Parts of Drawings>

110: register 120: divider

130 to 160: SAD calculator 170, 220: switching block

180 to 210: buffer 230 to 260: SAD comparison operation unit

300 ~ 330, 350, 360, 380: Adder

340, 370: pipeline register 400: demultiplexer

410 ~ 440: Adder 450 ~ 480: Buffer

The present invention relates to a motion estimation calculation method and a calculation circuit used in various multimedia codecs such as MPEG-2, MPEG-4 and H.264 / AVC next generation multimedia codec. The present invention provides a motion estimation algorithm and a calculation circuit that reduce the amount of computation and power consumption used in a multimedia codec by estimating the motion of adjacent M × N blocks by sharing one search area in a motion estimation process.

Recently, multimedia signal processing technology has reached the stage of compressing still image and video signal and transmitting it wirelessly with the development of semiconductor process and design technology and broadband wireless communication system. Research continues to maintain the image. International standards for multimedia signal processing technology include ISO / IEC MPEG-2, MPEG-4 or ITU-T H.263 and ISO / IEC and ITU-T jointly developed H.264 / AVC.

In addition, commercially available satellite and terrestrial DMB services are in the spotlight in that they can use multimedia data while moving, and the demand is expected to increase explosively. The next generation mobile communication is a communication method that transmits and receives multimedia information such as voice, pictures, and videos at high speed and high quality. Therefore, there is a need for a technology capable of maintaining high quality while maintaining a high compression rate in order to implement high quality multimedia services at a limited data rate. H.264 / AVC technology is known to have compression efficiency of about 40% compared to MPEG-4 and about 60% for MPEG-2. Therefore, H.264 / AVC is used in VOD service, digital camera, video camera, DVD, etc. through internet and wireless because it can maintain the broadcasting quality of DVD level even under transmission speed of 1Mbps or less.

The H.264 / AVC makes prediction data by estimating the motion from a reference frame (image frame used for motion estimation) like the existing video compression encoding method such as MPEG-2 and MPEG-4, and most matches with the image to be encoded. Discrete cosine transform / quantization is performed after making the difference data with the predictive data. Finally, entropy coding (also called variable length coding) is performed. It is based on a technique called motion estimation and compensation, discrete cosine transform / quantization, and entropy coding.

In addition, the H.264 / AVC defines three profiles that support a specific function: a baseline profile (BP), a main profile (MP), and an extended profile (EP). The requirements for the decoder are defined to be compatible with each profile. A profile is a standardization of technical components entered in an algorithm during video decoding. In other words, it can be referred to as a set of descriptive elements necessary for decoding a bit string of a compressed image.

The H.264 / AVC sets the image processing unit to a smaller block size (4 pixels x 4 lines = 16 pixels) compared to the conventional MPEG method, and uses precise pixel precision (up to 1/4 pixel) for very precise movement. Estimation is possible. In addition, we use motion estimation to select the best prediction signal by using multiple reference frames.

FIG. 1 shows the structure of the H.264 / AVC coder, which has an Fn (current frame) and an F'n-1 (reference frame) in units of macro blocks (16 x 16). It operates in Intra mode. In inter mode, motion estimation is performed by inter picture encoding, and in intra mode, the current frame is encoded by intra picture coding.

In the inter-mode operation order of the motion estimation operation, the input Fn for encoding is processed in macroblock units, and Fn is compared with F'n-1. The motion estimation portion finds a macroblock that matches the current macroblock in Fn within F'n-1, and the difference between the position of the current macroblock and the selected reference region becomes a motion vector. A motion compensated prediction region is generated according to the selected motion vector MV, and an error macro block is generated by subtracting the prediction region from the current macroblock.

The error macroblock is transformed using a discrete cosine transform (DCT), and is generally divided into 8 × 8 or 4 × 4 subblocks, and each subblock is transformed independently. Each subblock is quantized through Q (Quantization) and the quantized coefficients are relocated by scan and run-level coded. Finally, coefficients, motion vectors, and associated header information of each macro block are entropy encoded to generate a compressed bit stream, which is then passed to the decoder.

In the motion estimation method, the following process is performed on each block having M × N samples in the current frame. Firstly, a certain area of a reference frame (previous or subsequent frame) is searched to find an M × N sample area that matches the M × N sample block of the current frame. This process consists of (Full-Search) or part of (Fast-Search) all M × N blocks in the current frame and the possible M × N blocks in the search area (typically a constant area within the reference frame relative to the current block's position). By comparison, it is the process of finding the best match among them. A method of selecting a candidate region having the smallest sum of Absolute Difference (SAD) obtained by subtracting the candidate region from the current M × N block as the most matching region is used. In order to search a certain region of a reference frame, MVp (Motion Vector Prediction), which is the center of the search region, must first be obtained. In order to obtain the MVp, the MV (Motion Vector) of the upper, upper right and left blocks of the current block is obtained by performing median filtering.

2 illustrates a method of generating MVp of a current block. The next selected candidate region becomes a prediction block for the current M × N block, and M × N difference data is generated by subtracting the prediction block from the current block, and the M × N difference data is encoded and transmitted. The motion vector between the position of and the position of the candidate area is also transmitted. The decoder regenerates the prediction region using the received motion vector, and reconstructs the original block by adding the prediction region and the reconstructed M × N difference data.

Such motion estimation reuses the data in the search area in a single-port memory with 32 bits of bandwidth, and accesses 95 times per 4 × 4 blocks if the search area is [-8, +7]. Should be. In QCIF (176 x 144) video, there are 1584 4 × 4 blocks, which requires access to 150,480 memories per frame of QCIF video. In addition, when the search area is set to [-15, +16], the memory should be accessed 324 times per 4 × 4 block, and the memory should be accessed 513,216 times per frame of QCIF image.

3 and 4 show the calculation of the amount of calculation for each block of the conventional encoder and the decoder. The motion estimation occupies the largest portion with 39% of the calculation amount and the motion compensation with 29% of the calculation amount. As such, motion estimation and compensation can maintain a high quality image with a small amount of transmission data. However, there is a problem in that the amount of computation is large enough to account for 39% of encoding operations and the number of memory accesses is high, resulting in high computational power and power consumption.

In order to solve the problems described above, the present invention shares one search area with a motion estimation part that uses a large amount of computation and power consumption for various multimedia codecs such as MPEG-2, MPEG-4 and H.264 / AVC next-generation multimedia codecs. By providing a motion estimation method for estimating the motion of adjacent M × N blocks and the motion estimation operation circuit thereof, it is possible to reduce the amount of computation and power consumption used in the multimedia codec.

Another object of the present invention is to reduce the number of memory accesses by sharing the search area itself using similarity of MVp between adjacent blocks without reusing data in the search area in order to reduce the amount of computation and memory access in motion estimation. It is done.

In order to achieve the above object, the present invention provides a method for executing a motion estimation operation used in an MPEG-2, MPEG-4, or H.264 / AVC multimedia codec, wherein one M of each adjacent M × N blocks is provided. A motion estimation calculation method for a multimedia codec is further provided by sharing a search area of × N blocks to perform motion estimation of adjacent M × N blocks.

In addition, in an operation circuit for performing motion estimation operation used in the MPEG-2, MPEG-4, or H.264 / AVC multimedia codec, a 4x4 block is composed of four rows, and is arranged in four 36x36 search areas. 144 8-bit registers capable of storing three rows of pixel data; A divider for combining and outputting data values from a register which stores data of each row of the current block and data of the search area; A SAD operation unit for obtaining a difference value between the input pixel data of the current block and the pixel data of the search area; A switching block for outputting the output SAD values sequentially and a buffer for storing the SAD values received from the switching blocks; A switching block for feeding back the SAD value or sequentially outputting the SAD value of the last completed 4 × 4 block so as to become the SAD value of the completed 4 × 4 block; It provides a motion estimation algorithm for a multimedia codec comprising a SAD comparison operation unit for outputting the SAD value and the position of the block having the smallest SAD while sequentially comparing the SAD value of the input 4 × 4 block. .

The motion estimation algorithm used in various multimedia codecs according to the present invention first generates four addresses of neighboring 4 × 4 blocks of the current frame, inputs them into a memory in which the current frame is stored, and outputs four four from the memory. 4 Stores the data of the current block in each register. In order to find the block that best matches the 4 4 × 4 current blocks of the current frame in the reference frame, an MVp of the first block of the 4 4 × 4 current blocks is generated, and a predetermined region in the reference frame is created based on the generated MVp. Set the search area for. Next, when the search area is determined, an address of each data in the search area is generated, inputted into a memory in which a reference frame is stored, data in the search area output from the memory, and data of four 4 × 4 current blocks stored in a register. Obtain 4 × 1 SAD values of four blocks in units of 4 × 1 between. After that, each 4 × 1 SAD value obtained through the operation is added to generate a 4 × 4 SAD value. The reference block having the smallest SAD value among the SAD values for each of the four 4x4 current blocks is the most identical block, and the data of the 4x4 block and the 4x4 current block of the most identical reference frame are the same. The data of the error block is generated by subtracting the data. In addition, the MVs of the four 4 × 4 current blocks are generated by calculating MVs based on the MVp of the first block, respectively, and the error blocks and the MVs of the four 4 × 4 current blocks generated are encoded and transmitted to estimate the motion. The operation ends.

Hereinafter, with reference to the accompanying drawings will be described in more detail for each calculation process of the present invention.

First, FIG. 5 shows a block that most matches a current block in a search region of a current block formed in a reference frame in the method for executing a motion estimation operation used in an MPEG-2, MPEG-4, or H.264 / AVC multimedia codec. When MVp is generated, all data in the search area must be read from the memory to form a search area around the MVp in the reference frame and find the most matching block in the search area. This process is the same for all blocks, but since the positions of the MVp, which are the centers of the search areas, are similar to each other in the case of adjacent blocks, each search area is not used separately. Can be used.

Next, FIG. 6 illustrates a region overlapped with each other between search areas of the current block and three adjacent blocks, and a dotted area is a region where the search areas of adjacent blocks overlap.

  QCIF video ± 16 ± 8 ± 5 ± 3 Akiyo 100 100 99.8906 99.7475 Bridge close 100 99.9663 99.3406 97.7609 Carphone 99.8906 97.1661 91.8042 83.2407 Clare 99.9747 98.6700 93.5943 86.1728 Coastguard 99.9663 97.7581 91.9978 74.3406 Foreman 99.9832 98.8047 96.1700 91.8575 Granma 99.9074 97.4270 93.9113 89.2424 suzie 99.7980 95.4321 86.8642 72.8423 Table tennis 99.9579 98.5269 92.9181 83.6785 trevor 99.9832 99.8485 98.8861 96.5544

Table 1 shows the probability that the MVp of adjacent blocks B2, B3, and B4 is located in a predetermined region (± 16, ± 8, ± 5, ± 3) of the 4 × 4 current block (B1) MVp. The probability that adjacent blocks (B2, B3, B4) are found in the ± 16 region of the current block (B1) is over 99%, and 95 percent or more in the ± 8 region. Therefore, instead of reading all the search areas of the adjacent blocks B2, B3, and B4 from the memory, only the search area of the current block B1 is set as the search area of the adjacent blocks B2, B3, and B4, and the current block search is performed. Find the closest block of adjacent blocks (B2, B3, B4) in the area. Therefore, this method can reduce the memory access by 75% compared to the conventional full search method, thereby reducing the power consumption.

Next, FIG. 7 shows a process of finding the most matching blocks of three blocks adjacent to the current block in the search area of the current block. The center of the search area is the MVp of the current block, and after finding the best matching block of the current block and neighboring blocks, four MV and four error block data are generated.

As an example, when the search area of the current block 4x4 is [-16, +15], the size of the search area is 36x36. Since the adjacent block is 4 × 4, when MVp = 0, the search area of B1 is equivalent to moving the search area of the current block 4 pixels to the right, and the search area of B2 moves the search area of the current block 4 pixels below. Same as Finally, the search area of B3 is equivalent to moving the search area of the current block 4 pixels to the right diagonal.

Accordingly, the size of the entire search region including the search region of each adjacent block is 40 × 40. Table 2 shows the PSNR (Peek Signal To Noise Rate) when the size of the search area to be shared is 40 × 40 and 36 × 36. In Table 2, when the search area to be shared by each block is 40 x 40 including the search area of the adjacent block, when the search area 36 × 36 itself of the current block is shared and the average error of the PSNR is almost ± 0.07 dB. same. Therefore, the search area of the first block in the upper left corner can be shared and used to find the most matching blocks of four adjacent 4x4 blocks.

QCIF video PSNR mean in search area 36 × 36 PSNR mean in search area 40 x 40 Akiyo 43.1963 43.2263 Bridge close 38.2670 38.3170 carphone 33.6620 33.6720 Clare 44.0709 43.9909 Coastguard 32.4164 32.5364 Foreman 35.2080 35.2780 Granma 41.5239 41.4339 Grasses 26.7602 26.8002 Miss am 41.6294 41.5694 Suzie 38.5248 38.6148 Table tennis 30.6401 30.7201 trevor 36.3952 36.3752

In addition, Table 3 shows the number of memory accesses when sharing the proposed search area and not using the search area when calculating a QCIF (Quarter Common Intermediate Format) frame in 4 × 4 block units. As shown in Table 3, memory access can be reduced by 75% when shared search areas are used.

Use search area of each block Share search area of adjacent blocks Size of navigation area [-8, +7] [-15, +16] [-8, +7] [-15, +16] Memory access count 150,480 513,216 37,620 128,304

Next, FIG. 8 shows an operation circuit for motion estimation using the memory reuse of the present invention. Since 4 × 4 blocks are composed of four rows, four rows of pixel data can be stored in a 36 × 36 search area. 144 8-bit registers 110, a divider 120 that combines and outputs data values from the registers 110 storing data of each row of the current block and data of the search area, and a pixel of the input current block. Received from the SAD calculator 130, 140, 150, 160 for calculating the difference between the data and the pixel data of the search area, and the switching block 170 and the switching block 170 for sequentially storing the output SAD values. Buffers for storing SAD values (180, 190, 200, 210), which feed back the SAD value to be the SAD value of the completed 4 × 4 block or sequentially output the SAD value of the final 4 × 4 block The switching block 220 is composed of a SAD comparison operation unit 230, 240, 250, 260 to sequentially output the SAD value and the position of the block having the smallest SAD value while sequentially comparing the SAD value of the input 4 × 4 block .

Since the 4 × 4 block is composed of four rows, four rows of pixel data in the 36 × 36 search region are sequentially stored in the 144 registers 110, and the SAD value of the final 4 × 4 block is subsequently processed. At the same time, the pixel data of the register is shifted left by 36 bits and the pixel data of the next row is sequentially input. The three blocks adjacent to the current block are simultaneously calculated in the same way, and the calculation method of the current block first calculates four SADs at the same time by 4 pixels per cycle.

Next, FIG. 9 illustrates a structure of a calculation unit for obtaining SAD values of a 4x1 block, and includes adders 300, 310, 320, for obtaining SAD values by receiving pixel data of a reference block and pixel data of a current block. 330, a pipeline register 340 that temporarily stores the calculated results, adders 350 and 360 for adding SAD values of 4 pixels, and a pipeline that temporarily stores the calculated results. A register 370 and an adder 380 for finally adding SAD values of 4x1 pixel data.

10 shows a structure of a buffer for storing SAD values of a 4x1 block, a demultiplexer 400 for receiving the calculated SAD values of the 4x1 block and selectively storing them in a buffer; Finally, the adders 410, 420, 430, and 440 for adding the SAD value previously stored to obtain the SAD value of the 4 × 4 block and the SAD value of the currently input 4 × 1 block, and the calculated result It is composed of buffers 450, 460, 470, and 480 for storing.

11 illustrates SAD operations between pixel data in a search region of a reference frame and pixel data of a current block using a motion estimation algorithm used in a multimedia codec according to the present invention. Each shift is shifted right by one register, and after four shifts, the operation is shifted right by twelve registers. Since there are 32 4 × 4 blocks in four rows of the reference frame, after 8 cycles, the 32 SADs that computed one row of the current block and one row of the reference frame through the SAD calculator 1 (130) are Buffer_1-0. Is stored in Buffer_1-35 (180), and 4 pixels of 2 rows of the current block are calculated in the same manner. All rows are calculated in the same way for the current block, and after 32 cycles, each buffer 180 stores the final SAD values for the 32 blocks in which the SAD values of each row are accumulated. SAD operator 1 130 calculates the current block B1 with the pixel data of the reference frame, SAD operator 2 140 is the adjacent block B2, SAD operator 3 150 is the adjacent block B3, and SAD operator 4 160 is the adjacent. SAD operation is performed on the block B4 with the pixel data of the reference frame. Thereafter, the SAD 1 comparison operator 230 outputs the SAD value of the minimum value among the SAD values stored in the Buffer_1-0 to the Buffer-1_35 (180). SAD 2 comparison operation unit 240 is from Buffer_2-0 to Buffer-2_35 (190), SAD 3 comparison operation unit 250 from Buffer_3-0 to Buffer-3_35 (200), SAD 4 comparison operation unit 260 from Buffer_4-0 SAD values of the minimum values among the values stored in the buffer-4_35 (210) are output.

As described above, the present invention has been described with reference to the embodiments shown in the drawings, but it is only for illustrating the invention, and those skilled in the art to which the present invention pertains various modifications or equivalents from the detailed description of the invention. It will be appreciated that one embodiment is possible. Therefore, the true scope of the present invention should be determined by the technical spirit of the claims.

The present invention provides an efficient motion estimation calculation method used in various multimedia codecs such as MPEG-2, MPEG-4 and H.264 / AVC next-generation multimedia codec as described above, and provides an operation circuit for implementing the calculation method. The performance was improved by efficiently performing the motion estimation process that takes up a large amount of computation when implementing the 264 / AVC algorithm.

As shown in Table 4, the present invention can compare operation cycles between a memory reuse algorithm sharing a search area and a general full search method. For the [-8, +7] search region, it takes 514 clocks to find the SAD of the 4x4 block. For QCIF (176 x 144) images, there are 1584 4 × 4 blocks, so it takes 514 × 1584 = 814,176 clocks to process one frame with the normal full search method.

Navigation area size [-8, +7] [-16, +15] General pre-search algorithm Proposed algorithm General pre-search algorithm Proposed algorithm Clock required to find SAD of one 4 × 4 block 514 clock 514 clock 1163 clock 1163 clock QCIF (176x144) 814,176 clock 203,544 clocks 1,842,192 clock 460,548 clock 30 frames (1 reference frame) 24,425,280 clock 6,106,320 clock 55,265,760 clock 13,816,440 clock 5 reference frames 122,126,400 clocks 30,531,600 clock 276,328,800 clock 69,082,200 clock

In the method according to the present invention, since 4 4 × 4 blocks are processed in parallel at the same time, 814,176 / 4 = 203,544 clocks are required. Therefore, in case of motion estimation calculation of 30 frames per second with one reference frame, the general pre-search method should operate at 24MHz, and the proposed method should operate at 6MHz. In addition, when the motion estimation operation is performed at 30 frames per second with 5 reference frames, the general full search method should operate at 122 MHz and the proposed method should operate at 30 MHz. In the case of the [-16, +15] search region, a 1163 clock is required to obtain a SAD of a 4 × 4 block. The general full search method requires 1,842,192 clocks to process one frame of QCIF image, and the proposed method requires 1,842,192 / 4 = 460,548 clocks because 4 4 × 4 blocks are processed in parallel at the same time. Therefore, in case of motion estimation calculation of 30 frames per second with one reference frame, it should be 55MHz and 13MHz in the proposed full search method, and in case of 5 reference frames, 276MHz, 69MHz in the proposed scheme. The proposed method is an efficient method that can reduce the power consumption by 75% compared to the conventional method because the operating frequency is used about 1/4 of the conventional full search method.

In addition, as shown in Table 5, the present invention can compare the PSNR between the memory reuse algorithm sharing the search area and the previous search algorithm of H.264 / AVC. In other words, the average error of PSNR is similar to each other by ± 0.05dB. Therefore, the proposed memory reuse algorithm is an efficient structure that reduces the number of memory accesses by 75% compared to the general H.264 / AVC search algorithm with almost no loss of image quality.

QCIF video H.264 / AVC (dB) Proposed Algorithm (dB) Akiyo 43.1963 43.2013 Bridge close 38.2670 38.2675 carphone 33.6620 33.6099 Clare 44.0709 44.9770 Coastguard 32.4164 32.4070 Foreman 35.2080 35.1961 Granma 41.5239 41.5221 Grasses 26.7602 26.7453 Miss am 41.6294 41.5164 Suzie 38.5248 38.4887 Table tennis 30.6401 30.6095 trevor 36.3952 36.3968

Claims (6)

Efficient Motion Estimation Algorithm for MPEG-2, MPEG-4 and H.264 / AVC Next Generation Multimedia Codec A method of calculating motion estimation used in various multimedia codecs comprising sharing a search area of one M × N block among each adjacent M × N blocks to perform motion estimation of adjacent M × N blocks. . The method of claim 1, When the M × N block is 4 × 4 blocks, A motion estimation operation method for various multimedia codecs, comprising: performing a motion estimation operation of three adjacent blocks by sharing a search area of the upper left 4 × 4 block among four adjacent 4 × 4 blocks; . Efficient Motion Estimation Algorithm for MPEG-2, MPEG-4 and H.264 / AVC Next Generation Multimedia Codec Generating four addresses of four neighboring 4x4 blocks of the current frame, inputting them into a memory in which the current frame is stored, and storing data of four 4x4 current blocks output from the memory in each register; In order to find the block that most closely matches the 4 4 4 current blocks of the current frame in the reference frame, an MVp of the first block of the 4 4 4 4 current blocks is generated, and a constant within the reference frame based on the generated MVp. Determining a search area of the area; When the search area is determined, an address of each data in the search area is generated and inputted into a memory in which a reference frame is stored, and 4 between the data in the search area output from the memory and the data of four 4 × 4 current blocks stored in the register. Obtaining 4 × 1 SAD values of four blocks in units of 1 ×, and then generating 4 × 4 SAD values by adding respective 4 × 1 SAD values obtained through operations; The reference block having the smallest SAD value among the SAD values for each of the four 4x4 current blocks is the most identical block, and the data of the 4x4 block and the 4x4 current block of the most identical reference frame are the same. Subtracting the data to generate data of an error block; MV of the four 4 × 4 current blocks are generated by calculating MVs based on MVp of the first block, respectively, and the error blocks and MVs of the generated 4 4 × 4 current blocks are encoded and transmitted. Motion estimation algorithm used in various multimedia codecs, characterized in that. In the arithmetic circuit which performs the motion estimation operation used for MPEG-2, MPEG-4 or H.264 / AVC multimedia codec, 144 8-bit registers each consisting of four rows of 4 × 4 blocks, capable of storing four rows of pixel data in a 36 × 36 search area; A divider for combining and outputting data values from a register which stores data of each row of the current block and data of the search area; A SAD operation unit for obtaining a difference value between the input pixel data of the current block and the pixel data of the search area; A switching block for outputting the output SAD value so as to be sequentially stored; A buffer for storing the SAD value received from the switching block; A switching block for feeding back the SAD value or sequentially outputting the SAD value of the last completed 4 × 4 block so as to become the SAD value of the completed 4 × 4 block;  Motion estimation algorithm used in various multimedia codecs comprising a SAD comparison operation unit for outputting the SAD value and the position of the block having the smallest SAD value while sequentially comparing the SAD value of the input 4 × 4 block. The method of claim 4, wherein SAD calculation unit for calculating the SAD data received from the distributor, Each adder is connected to a pipeline register installed between the parallel adders in order to obtain the SADs of the internal reference block 4 × 1 pixels and the current block 4 × 1 pixels. And pipeline registers are motion estimation computing circuits used in various multimedia codecs, characterized in that connected by a connecting line. The method of claim 4, wherein The buffer for storing the SAD value of each block, One demultiplexer for storing SAD values of each 4 × 1 block, 36 adders and 36 buffers connected in parallel to the bottom of the demultiplexer, and a connection line connecting the motions used in various multimedia codecs Estimation Computation Circuit.

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