KR100973083B1 - Motion vector extractor based array and method thereof - Google Patents

Abstract

The motion vector extractor includes an interface / router block for interfacing with an external memory to receive frame data, and an internal memory and a register adapter to simultaneously perform read and write operations. According to the present invention, the frame data required for performing the motion estimation is copied to a faster internal memory, and the frame data for a SAD (Sum of Absolute Difference) operation is copied from the internal memory to the register adapter. Therefore, the operational efficiency can be improved by minimizing the delay time caused by the read and write operations of the memory. In addition, by providing a pipeline register that is variably controlled in each operation block, it is possible to reduce the power consumption according to the existing consistent pipeline structure.

Description

Motion vector extractor based array and method

The present invention relates to a motion vector extractor, and more particularly, to an array-based motion vector extractor and a method for real-time coding of scalable video coding (SVC) for universal media services.

In the recent trend of convergence of broadcasting media and communication media, digital TV and digital set-top boxes (STBs) are emerging as home media servers that integrate broadcasting contents, commercial contents (communications, internet, etc.) and home-grown contents. There is a situation.

In particular, the rapid transition to the ubiquitous era of the entire society is accelerating the convergence of the broadcasting and telecommunications media service industry. Therefore, in order to proactively cope with this, the compatibility of broadcasting and telecommunication media contents, the accessibility of media contents, and the distribution of media contents There is an urgent need for the development of core and convergence technologies in the universal media services industry based on digital TV, which is adaptable and safe.

In addition, the boundaries of the broadcasting and communication media industries are breaking down within and outside the home due to the spread of home networks linking broadcast communication networks and the proliferation of media information devices integrating broadcast communication media. It should be deployed to receive desired media contents anytime and anywhere through various media devices.

However, in the existing media services, media such as broadcast contents, internet media contents, and information device contents do not have mutual compatibility in terms of different media formats, transmissions, and service methods. The response to the situation is insufficient.

As shown in FIG. 1, existing media codecs are MPEG-2 used for digital broadcasting, HDTV and DVD, Internet streaming, MPEG-4 and WMV9 used for video files (DviX, Xvid, etc.), and recently DMB, MPEG-4 AVC / H.264 and the like adopted in DVB-H, HD-DVD, and the like exist.

Since most of these media codecs have a standard for a specific purpose, they are difficult to interoperate with each other, and it is difficult to directly apply them to general environments such as various networks and heterogeneous terminals.

In addition, in the existing mixed environment such as various media standards such as digital broadcasting, Internet, various wireless terminals, and various media codecs, digital TV integrates various heterogeneous media standards and enables users to access media more easily. It is required to be.

Meanwhile, with the development of the Internet, mobile terminals, and wireless communication technologies, video services are available in PDAs, PMPs, mobile phones, and the like, so that transcoding technologies between existing codec technologies are used to provide seamless video services to various networks and heterogeneous terminals. Although a solution has been developed, this solution is applied to only a few applications because real-time transcoding is required to be applied to dynamic network environments as well as degradation of image quality due to transcoding between existing codecs.

Therefore, it is possible to overcome the limitations of existing codecs and solutions, and at the same time, media convergence of broadcasting communication is possible, and universal media that can provide universal media service suitable for ubiquitous environment shared in various network environments at any time, anywhere and any device. Development of codec technology is urgently needed.

Therefore, in the case of an encoder using a scalable video coding (SVC) technology that has been developed to solve the above-mentioned problems, the operating frequency is raised to encode a maximum HD level image in real time. In this case, power consumption due to a consistent pipeline structure is increased and in some cases, real-time processing may not be performed due to performance differences of video sources.

In addition, since the efficiency of integration decreases due to excessive use of frame memory, and delay time caused by read and write operations of the memory affects real-time operation, a method of effectively processing the same is required.

Disclosure of Invention An object of the present invention is to solve the conventional problems as described above, an array-based motion for real-time coding of scalable video coding (SVC) for Universal Media Service (UMS) A vector extractor and its method are provided.

In order to achieve the above object, a motion extractor according to an aspect of the present invention is an internal memory block for receiving and storing previous frame data divided in units of specific blocks in parallel, and the previous frame divided in units of the stored specific blocks. Performs SAD (Sum of Absolute Difference) operation by receiving register data of parallel structure and receiving parallel output of data, and parallel frame configured to receive current frame data and previous frame data provided from the register adapter. A SAD operation unit including a plurality of SAD tree blocks, and configured in parallel to receive a current SAD value output from a corresponding SAD tree block among the plurality of SAD tree blocks, and a previously calculated SAD value and the current SAD. A comparison year that includes a number of comparators, each comparing a value Portion and include a motion vector merging arranged to merge the motion vector (motion vector) values for each pixel based upon the comparison results received from the plurality of comparators.

According to another aspect of the present invention, a motion extractor includes an interface / router for interfacing with an external memory and a read and write operation for receiving frame data stored in the external memory as the previous frame data through the interface / router block. A register adapter and a controller for controlling the overall operation of the interface / router, the internal memory and the register adapter having an internal memory and a register group for copying the previous frame data stored in the internal memory to perform the SAD operation. Include.

According to another aspect of the present invention, there is provided a method of extracting a motion vector, by receiving frame data from an external memory, dividing the frame data (hereinafter, referred to as previous frame data) corresponding to a previous frame into a specific block unit, and Receiving and storing the previous frame data divided into parallel in parallel; receiving the previous frame data divided into the stored specific block units in parallel and storing the same in the pipelined register adapter; Performing a sum of absolute difference (SAD) operation by receiving current frame data (hereinafter, referred to as current frame data) and previous frame data corresponding to a current frame through a plurality of SAD tree blocks, respectively; The current SAD value that is the result of the SAD operation through the comparator of And a step of comparing the SAD value computed for each of the existing and aligning and merging the motion vector (motion vector) values for each pixel based upon the comparison results received from the plurality of comparators.

According to the present invention, the motion vector extractor of the present invention includes an interface / router block for interfacing with an external memory to receive frame data, and an internal memory and a register adapter simultaneously performing read and write operations. According to the present invention, the frame data required for performing the motion estimation is copied to a faster internal memory, and the frame data for a SAD (Sum of Absolute Difference) operation is copied from the internal memory to the register adapter. Therefore, the operational efficiency can be improved by minimizing the delay time caused by the read and write operations of the memory. In addition, by providing a pipeline register that is variably controlled in each operation block, it is possible to reduce the power consumption according to the existing consistent pipeline structure.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. In addition, in describing this invention, the same code | symbol is attached | subjected and the repeated description is abbreviate | omitted.

First, before describing the embodiment of the present invention, a description will be given of a structure of flexible video coding for adaptive bitstream generation.

2 is a block diagram showing an entire core encoder for flexible video coding for generating an adaptive bitstream.

Universal Media Coding (UMC) encoder generates a video stream for providing Universal Media Service (UMS) through various media contents and various types of media devices.

In order to provide adaptive bitstreams for various situations, the UMC encoder focused on features suitable for UMS services based on scalable video coding (SVC) technology.

As shown in FIG. 2, the flexible video coding uses a Hierarchical P / B structure for temporal scalability. Since it is necessary to provide UMS service to multiple terminals based on digital broadcasting service, it is necessary to service the highest HD video and support various resolutions below it.

In addition, in the profile defined by the current standardized SVC standard, the profile for mobile terminals is based on the H.264 / AVC baseline profile as the svc baseline profile. Therefore, the UMC coding of the SD or lower for the terminal is encoded only by I / P-slice, and only the HD-class video is encoded by I / B / P-slice by adopting Hier. P / B mixed structure is applied.

Hereinafter, the array-based motion vector extractor for real-time encoding of the universal media codec as described above will be described in detail.

3 is a block diagram of an array based motion vector extractor according to an embodiment of the present invention.

The motion estimation process in image compression increases computational complexity in the process of increasing the compression efficiency. In order to process this increased amount of computation in a timely manner and to reduce implementation complexity, prediction is generally divided into two processes. That is, it is divided into integer estimation and fractional estimation. First, rough estimation is performed through the integer estimation process, and more sophisticated estimation is performed through fractional motion estimation.

The motion vector extractor 10 shown in FIG. 3 is a processing unit for processing the integer estimating process, and is a critical path in an encoding process by using a parallel structure based on a conventional Sum of Absolute difference (SAD) tree. Appropriately distributed according to the application. Therefore, the array-based motion vector extractor 100 according to the embodiment of the present invention solves a problem in that HD-quality images are not encoded in real time due to the delay time of reading and writing the memory. To this end, the array-based motion vector extractor 100 according to the embodiment of the present invention includes an interface / router block 10 for interfacing with external memory, an internal memory block 12, and a register. It is characterized in that it comprises a register adapter block (14).

More specifically, the array-based motion vector extractor 100 according to the embodiment of the present invention may include the reference array block 16 (Ref.array) and the current array block (aside from the blocks 10, 12, 14). 28, Cur.array), a plurality of SAD tree blocks 18, a plurality of comparator blocks 20, a motion vector merger 22, an address generator 24, an address generator, a data buffer 26, Data buffer) and the controller 30 further.

The interface / router block 10 serves as a controller of the external memory (eg, a frame buffer), that is, interfacing to receive YUV (YCbCr / YPbPr) data of HD or SD class.

In detail, the interface / router block 10 receives YUV data (hereinafter, referred to as frame data) from the external memory in units of frames and receives frame data (previous frame data) corresponding to the previous frame in units of specific blocks (eg, 4x4). The previous frame data divided into specific block units are temporarily distributed and stored temporarily in the internal memory block 12. At the same time, the interface / router block 10 temporarily stores frame data (current frame data) corresponding to the current frame in the data buffer 26.

The internal memory block 12 may be implemented with a plurality of SRAMs configured in parallel, and when the internal memory block 12 is implemented with a plurality of SRAMs, each of the SRAMs may be implemented by the address generator 24. In response to the generated address value, the previous frame data divided into specific block units are primarily distributed and stored. In this case, each of the SRAMs may be implemented as dual port SRAMs in order to minimize delay time according to read time and write time. In the case of single port SRAM, data read and write operations cannot occur at the same time. In the case of dual port SRAM, both read and write operations can be performed simultaneously. The delay time due to the write operation can be minimized.

The register adapter block 14 is a register group for a pipeline. The register adapter block 14 receives previous frame data divided in a specific block unit into the internal memory block 12 to control the controller 30. The reference array block 16 is then transferred to the reference array block 16. At this time, the data buffer 26 transfers the current frame data stored under the control of the controller 30 to the current array block 28.

The reference array block 16 serves as a kind of memory for storing previous frame data received from the register adapter block 14, and stores the previous frame data stored in the plurality of SAD tree blocks 18 under the control of the controller 30. ).

The current array block 28 serves as a kind of memory for storing current frame data received from the data buffer, and the plurality of SAD tree blocks are stored as reference frame data using the current frame data stored under the control of the controller 30. (18).

The plurality of SAD tree blocks 18 are configured in parallel, and each of the SAD tree blocks 18 performs SAD operations on macro frame units from previous frame data and current frame data received from the reference array block 28 and the current array block 28, respectively. The minimum value of the calculated results is output as the current SAD value.

The plurality of comparator blocks 20 are configured in parallel, the same number as the number of the plurality of SAD tree blocks 18. Each comparison block 20 receives the current SAD value output from the corresponding SAD tree block, compares the previously calculated SAD value with the current SAD value, and transfers the comparison result to the motion vector merger 22. .

As described above, in the present embodiment, all the pixels corresponding to one frame are calculated in macroblock units by the plurality of SAD tree blocks 18 and the plurality of comparator blocks 20 respectively configured in parallel. At this time, the controller 30 simultaneously controls all the SAD tree blocks and the comparator blocks. That is, it is controlled collectively according to the resolution and complexity of the input image. On the other hand, in the case of an SD TV, the plurality of SAD tree blocks 18 and the plurality of comparator blocks are each implemented with 16 units.

The motion vector merger 22 merges and sorts the motion vector values of each pixel as one frame based on the comparison result values transmitted from the plurality of comparator blocks 20. Here, the Mosher vector value means the distance to the macro block most similar to the current macro block.

The controller 30 controls each of the blocks 10, 12, 14, 16, 18, 20, 22, 24, 26, 28 as described above. In particular, the controller 30 controls the configuration of the macro block of the SAD tree.

In addition, in this embodiment, an enable controller register (or pipeline register) is designed at the end (or output end) of each block of the SAD tree block 18, the comparator block 20, and the motion vector merger 22. The controller 30 controls the designed enable controller register to variably adjust the pipeline stage.

As a result, the motion vector extractor 100 according to the embodiment of the present invention controls the pipeline register by designing the pipeline registers designed for each operation block 18, 20, 22 by the controller, thereby controlling the pipeline, thereby increasing the computational efficiency. To maximize power consumption and reduce power consumption due to a consistent pipeline structure.

The motion vector extractor according to an embodiment of the present invention extracts a motion vector according to the above integer estimation technique by using a parallel structure based on a Sum of Absolute difference (SAD) tree to apply a critical path in the encoding process. Distribute accordingly. If the motion vector extractor according to the embodiment of the present invention is applied to an SD TV, a motion vector is determined through 16 SAD trees and a comparator path.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary.

1 is a view showing various media codecs required in the next generation DTV.

2 is a block diagram showing an entire core encoder for flexible video coding for generating an adaptive bitstream.

3 is a block diagram of an array based motion vector extractor according to an embodiment of the present invention.

Claims (12)

For universal media coding, interface with an external memory storing previous frame data and current frame data of various media contents, sequentially receiving the previous frame data and the current frame data stored in the external memory, and specifying the previous frame data. An interface / router block divided into block units and outputting in parallel; Through the interface / router block, the previous frame data divided into the specific block units are received and stored in parallel from the external memory, and the delay time due to the read operation and the write operation of the previous frame data stored in the external memory is stored. An internal memory block including dual port RAM for simultaneously reading and writing to reduce the memory; A register adapter having a pipelined structure to simultaneously receive and simultaneously output previous frame data divided into the specific block units stored in the dual port RAM; A data buffer for temporarily receiving current frame data stored in the external memory through the interface / router block and temporarily storing the current frame data; A reference array block for sorting the previous frame data copied to the register adapter; A current array block configured to receive and arrange the current frame data through the interface / router block and the data buffer; 16 current SAD trees arranged in parallel and provided via the interface / router block, the data buffer and the current array block, and through the interface / router block, the register adapter and the reference array block. A SAD operation unit including a plurality of SAD tree blocks each receiving previous frame data provided and performing SAD (Sum of Absolute difference) operations in parallel in macroblock units; A plurality of SAD tree blocks configured in parallel to receive 16 current SAD values outputted from the corresponding SAD tree blocks to form 16 comparison paths for comparing the SAD values previously calculated with the current SAD values, respectively. A comparison operation unit comprising a comparator of; A motion vector merger for merging and aligning motion vector values of each pixel based on comparison results from the plurality of comparators to perform real-time encoding of stretchable video coding; And A controller for variably controlling a register of a pipeline structure provided at outputs of the plurality of SAD tree blocks, the plurality of comparators, and the motion vector merger; Motion vector extractor comprising a. delete The motion vector extractor of claim 1, wherein each of the previous frame data and the current frame data is YUV (YCbCr / YPbPr) data. delete delete delete The motion vector of claim 1, wherein the motion vector for real-time encoding of stretchable video coding is extracted from the previous frame data and the current frame data according to an integer estimation technique through the SAD operation. Extractor. delete delete delete delete delete

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