KR100896127B1 - Plated bumps coated with tin and flip chip bonding method using them - Google Patents

Abstract

The present invention provides a method of forming a bump coated with a chip or a substrate connecting solder having a predetermined thickness or less on a chip, a substrate, or both sides of the chip and the substrate in order to improve the bonding performance of the chip and the substrate on which the plated bump is used. The present invention relates to a method of bonding a chip or a substrate on which the same bumps are formed by a thermocompression bonding method. According to the present invention, a tin or tin alloy solder having a thickness of 0.5 μm or less is coated on a bump of an upper substrate or a lower substrate or both an upper substrate and a lower substrate to form a solder and a bump in a composite structure, and then using a transition liquid diffusion bonding method. It provides a joining method that enables direct joining of high reliability bumps with existing joining devices without investing in new equipment.

Flip Chip, Bump, Solder, Tin, Intermetallic Compound, Transition Liquid Diffusion Bonding

Description

Solder-coated electrolytic plating bumps and flip chip bonding method using the same {Plated bumps coated with tin and flip chip bonding method using them}

The present invention relates to a bump forming and bonding method, and more particularly, in order to improve the bonding performance of the chip and the substrate, a bump coated with a chip or a substrate connecting solder having a predetermined thickness or less on both sides of the chip, the substrate or the chip and the substrate is coated. A method of forming and a method of joining a chip or a substrate having such bumps by a transition liquid diffusion bonding method.

Flip chip package is a representative package type that best meets the trend of miniaturization, multifunctionality and light weight and shortening of electronic components. Flip chip packages are much smaller than conventional wire bonding methods, have excellent electrical characteristics, and are reported to be excellent in terms of reliability, and electronic companies are actively considering their introduction. The flip chip package refers to a type in which a semiconductor chip and a printed circuit board (PCB) substrate are directly bonded by using metal bumps. Gold bumps and copper are used as metal bumps.

In Korean Patent No. 10-0604334, gold, nickel, silver, or copper bumps are formed on a pad of a wafer or a substrate, and in the case of flip chip bonding, ultrasonic energy having a frequency in the range of 70 to 250 kHz is transferred to the chip. Apply ultrasound on the X-axis in the collet of the flip chip bonder and apply ultrasound on the Y-axis in the block of the flip chip bonder, or apply ultrasound on the Y-axis in the block of the flip chip bonder and apply ultrasound on the X-axis in the block of the flip chip bonder or collet The present invention discloses a flip chip bonding method in which the bonding force between chips and substrates is rapidly and rapidly bonded by intersecting each other in the same axial direction in the and blocks. However, in this case, a facility investment for the ultrasonic bonding apparatus is required in the flip chip bonding process, and thus, the unit cost of the process increases. In addition, the frequency of the ultrasonic wave applied as needed is also 18 ~ 150 kHz range in this study is different from the conventional technology and the frequency range.

In addition, a method of bonding a flip chip by tin plating on a metallic bump has been published [Ref. Y. Tomita, T. Morifuji, T. Ando, M. Tago, R. Kajiwara, Y. Nemoto, T. Fujii, Y. Kitayama, K. Takahashi. Electronic Components and Technology Conference, 353-360 (2001). The prior art flip chip junction is a structure of a general bump, and after electroless plating is performed on the copper bumps on both the upper and lower sides so that the sum of the thicknesses of the plating layers is 1.0 µm, the bonding is performed using a thermocompression method. In the prior art, a large amount of intermetallic compound is generated and grown on the junction interface between the bumps and the bumps and the sides of the bumps as indicated by the arrows in FIG. 1, which is a major cause of the decrease in the bonding strength and the signal transmission ability. Can act as

The present invention is to solve the problems of the prior art as described above, an object of the present invention is to eliminate the investment in equipment for the bonding apparatus in the upper substrate and lower substrate bonding process, the product manufacturing cost is reduced, the upper substrate and the lower The purpose of the present invention is to improve the bonding strength and the signal transmission capability by preventing the intermetallic compound from being generated at the bonding interface between the bumps and the bumps and the side surfaces of the bumps when the substrates are bonded.

In order to achieve the above object, the present invention is to form a solder and bump in a composite structure by coating a tin or tin alloy solder with a total thickness of less than 0.5㎛ on the upper substrate or the lower substrate or the bump of both the upper substrate and the lower substrate By using the transition liquid diffusion bonding method, the present invention provides a bonding method that enables direct bonding between high reliability bumps even with existing bonding apparatus without investing in new equipment.

The inter-substrate bonding method using the bumps coated with tin or tin alloy of the present invention comprises the steps of: (a) plating pure tin or tin alloy on the surface to be plated of the upper substrate, (b) dicing the upper substrate to separate Obtaining a chip, and (c) joining the obtained chip and the lower substrate by applying heat and pressure.

Specifically, the junction formation process includes a) the formation and growth of an intermetallic compound due to the reaction between the solder and the pad by heat, pressure, and ultrasonic energy, and b) the diffusion of the solder into the bump 14 and the pad 24. Continually generated and depleted of solder to inhibit the formation of further intermetallic compounds, c) continuous bump and pad or inter-bump diffusion, d) the intermetallic compound layer is decomposed again, e) Dissolved in the pad, the intermetallic compound between the bump and the pad becomes very thin or disappears, and f) homogenization, or aging, or due to ambient heat during use, g) the remaining intermetallic compound is finally dissolved or further The thickness becomes thinner.

As described above, the flip chip joint manufactured according to the present invention exhibits excellent bonding strength and reliability compared to the prior art. In addition, the joining method according to the present invention enables high reliability bump-to-bump direct joining even with existing joining devices without additional equipment investment. Therefore, the present invention has the advantage of forming a fine pitch flip chip joint having low production cost and excellent bonding strength and electrical properties. The technology of the present invention is very useful because of its wide application range such as core memory and non-memory chip bonding, horizontal and vertical multi-chip stacking of high-end electronic devices such as mobile multimedia electronic devices such as mobile phones and flat panel display devices.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

 As used herein, the term "substrate" may refer to both the upper substrate and the lower substrate, or may be either of these. In this embodiment, the upper substrate and the lower substrate may be composed of an intrinsic semiconductor wafer such as silicon or germanium, an impurity semiconductor wafer such as GaAs or InP, and a combination of glass and ceramic or polymer substrates such as rigid printed circuit boards and flexible circuit boards. have.

In addition, the lower substrate uses only platinum, nickel, aluminum, gold, silver or copper pads, or organic solderability preservative (OSP), electroless silver plating, electrolytic or electroless tin-bismuth plating to improve the storage and reliability of the substrate. It can be coated with electroless tin-silver plating, electroless nickel / gold plating, electrolytic nickel / gold or solder.

[Plating bump formation]

2A to 2E illustrate forming a plating bump on an upper substrate according to the present invention. Specifically, FIGS. 2A and 2B form a conductive thin film and use a photoresist or a dry film to form a bump. Figure 2c and 2d is a view showing the process of forming a wall for plating, forming a bump, coating a tin or alloy solder on the formed bump, Figure 2e is a photoresist or dry film to remove the present invention According to the drawing is a solder bump coated plating.

In order to form the plating bumps 14 on the upper substrate according to the present invention, as shown in FIG. 2A, a conductive thin film 18 was formed on the upper substrate 10. When the bumps 14 are formed by electroless plating, vapor deposition, or sputtering, only the bumps 14 are formed on the conductive thin film 18, and when the bumps 14 are formed by using electroplating, they are energized. The circuit is formed of a conductive material 18 on the front surface or a portion of the upper substrate 10 so as to be able to do so. In order to form the bumps 14, using the photoresist 20 or dry film as shown in FIG. An alloy element composed of nickel, gold, copper, silver, platinum, chromium, titanium, tungsten, cobalt, or a combination thereof having a high reactivity with the solder is subjected to bumps 14 using electrolytic or electroless plating or sputtering or vapor deposition. Formed. An alloy solder made of a pure material such as tin, silver, bismuth, copper, indium, iron, magnesium, aluminum, or the like, or a combination thereof, having a thickness of 0.5 μm or less using the electrolytic or electroless plating method as shown in FIG. 22) was formed.

Optionally, mechanical or chemical polishing, cutting, or chemical mechanical polishing (CMP) processes are performed to homogenize the height of the bumps 14 to make the heights of the bumps 14 uniform. If the height of the bumps 14 is uniform, the thickness of the solder coated on the bumps 14 may be reduced. Next, as shown in FIG. 2E, the photoresist 20 or the dry film is removed to complete the lower substrate on which the plating bumps are formed.

Optionally, the size of the bumps of the upper substrate may be larger or smaller than the size of the pads or bumps of the lower substrate. In this manner, the upper substrate on which the solder plating bumps are formed is diced to obtain individual chips.

 [Transition Liquid Diffusion Bonding]

2F shows a schematic view of the lower substrate 12. 2G to 2I illustrate a process of bonding the upper substrate and the lower substrate according to the present invention. As shown in FIG. 1F, the lower substrate 12 is composed of a pad 24 and a surface treatment layer 26. The pad 24 may be made of an alloying element made of nickel, gold, copper, silver, platinum, chromium, titanium, tungsten, cobalt, or a combination thereof, and the surface treatment layer 26 may have a storage stability and reliability of a substrate. It may be made of Organic Solderability Preservative (OSP), Electroless Silver Plating, Electroless Nickel / Gold Plating, Electrolytic Nickel / Gold or Solder. The surface treatment layer 26 may be omitted.

The sum of the coating thickness of the bump-like solder formed in the plating bump forming step of the upper substrate and the coating thickness of the solder that may be formed on the lower substrate 12 is preferably 0.5 μm or less.

 Hereinafter, the bonding process of the upper substrate and the lower substrate will be described in detail. As shown in FIG. 2G, the upper substrate 10 manufactured according to the present invention comes into contact with the lower substrate on the lower substrate 12. Optionally, if the height of the bumps 14 or the surface roughness of the substrate is not constant, a coining process is applied to apply a pressure of 1,000 MPa or less, so that the height between the upper pad and the lower substrate is made constant so that the bonding pressure is maintained. Save time and time.

 Figure 2h shows the initial stage of the bonding is done by applying heat and pressure. After aligning the upper and lower substrates, heat is applied at room temperature to 450 ° C. and 0 to 1,000 MPa pressure (based on the bump area). If necessary, the flux may be applied to either or both of the upper and lower substrates. If necessary, longitudinal or transverse ultrasonic waves of 10 to 150 kHz may be applied to the upper substrate, the lower substrate, or both, to reduce the bonding time, pressure, and temperature. As described above, applying heat, pressure or ultrasonic energy for bonding the upper substrate and the lower substrate causes bumps due to the reaction between the solder 22 and the pad 24 or the solder 22 and the surface treatment layer 26 during bonding. Intermetallic compound 28 is produced and grown between 14 and pad 24, which is shown in FIG. 2H.

 Next, the solder 22 continues to diffuse into the bumps 14 and the pads 24 to deplete the solder 22, and the intermetallic compound 28 layer is decomposed again and dissolved in the substrate and the pads, thereby causing bumps. The intermetallic compound 28 becomes very thin or disappears between the pad 14 and the pad 24. Continuous bonding or due to ambient heat during use, bumps 14 and pads 24 or diffusion between bumps continue to occur, causing intermetallic compounds to be dissolved or diffused together to form solder and bumps or solders and pads. Instead of atoms, you can create a reaction layer between bumps and pads or the atoms that make up bumps, solders, and pads. This serves to reinforce the joint and act as an element to improve the mechanical properties and reliability of the bump 14. Fig. 2i shows a cross section of the junction where the intermetallic compound is diffused into the bumps and the substrate and the intermetallic compound is removed at the junction using the junction method according to the invention as described above.

FIG. 3 is an SEM of a bonded section of an upper substrate 10 and a lower substrate 12 bonded using a method according to the present invention, using bumps 14 coated with tin or alloy solder prepared according to the present invention. (Scanning electron microscope) Picture. In FIG. 1, in which the SEM of the bonded cross section according to the prior art is shown in FIG. 1, the intermetallic compound 28 is present at the junction interface and the side of the bump, in the present invention, the nickel (Ni) bump and the copper (Cu) substrate are separated from each other. It can be seen that the layer of intermetallic compound 28 disappears due to the diffusion of the solder 22 into the bumps 14 and the substrate due to heat and pressure or ultrasonic energy applied during bonding.

 In addition, after the bonding time and the temperature is minimized to join, aging in the oven below the melting point of the solder 22 can be formed to form the final joint. The bonding process basically performs a flux-free process, and in some cases, the flux may be used to prevent oxidation of the substrate or to improve solderability. If flux is used, flush the flux after bonding. However, when no-clean flux is used, the washing process can be omitted.

A shear strength test was performed on the final junction thus prepared, and the results are shown in FIG. 4. As can be seen from the results derived from FIG. 4, it can be seen that the joint strength of the present invention is improved by about 100 times compared to the strength of the joint prepared in the prior art.

What has been described above has described one embodiment according to the present invention, and the present invention is not limited to the above-described embodiment, and as claimed in the following claims, without departing from the gist of the present invention, the field to which the present invention pertains. It will be said that the scope of the present invention to the extent that those skilled in the art can change.

1 is a cross-sectional photograph of a scanning electron microscope (SEM) of a joint according to the related art.

2A-2E illustrate forming plating bumps on an upper substrate in accordance with the present invention.

2F is a schematic view of the lower substrate.

2G to 2I illustrate a process of bonding the upper substrate and the lower substrate according to the present invention.

3 is a scanning electron microscope (SEM) cross-sectional photograph of a flip chip joint manufactured according to the present invention.

Figure 4 is a graph of the bond strength test results of the flip chip joint prepared according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: upper substrate 12: lower substrate

14: flip chip bump 18: conductive thin film

20: photoresist 22: solder

24: pad 26: surface treatment layer

28: intermetallic compound

Claims (9)

delete delete delete delete (a) forming a bump 14 on the upper substrate 10 on which the conductive thin film 18 is formed; (b) forming a solder (22) of 0.5 [mu] m or less on the bumps (14); (c) preparing a lower substrate 12 on which pads 24 are formed; (d) bonding the upper substrate 10 and the lower substrate 12 to each other; And (e) applying heat and pressure or heat, pressure, and ultrasonic waves to cause the solder 22 to diffuse into the bumps 14 and the pads 24 so as to dissipate, thereby extinguishing the solder layer and the intermetallic compound layer produced during bonding. Chip bonding method, characterized in that. The method of claim 5, wherein in the step (e) the heat is 25 ~ 450 ° C, the pressure is 0 to 1,000MPa range, the chip bonding method. The chip bonding according to claim 5, further comprising a coining step of applying a pressure of 1,000 MPa or less after the step (a) when the height of the bump 14 or the surface roughness of the substrate is not constant. Way. 6. The method of claim 5, comprising applying longitudinal or transverse ultrasonic waves to the upper substrate, the lower substrate, or both substrates. The chip bonding method according to claim 8, wherein the ultrasonic waves are applied as transverse or longitudinal ultrasonic waves in the range of 18 to 150 kHz for 0 to 30 seconds.

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