KR100892741B1 - Light emitting device of a nitride compound semiconductor and the fabrication method thereof - Google Patents

Abstract

A light emitting device of a nitride compound semiconductor and a fabrication method thereof are provided to effectively reduce the generation of the crack caused by the lattice constant of substrate by decreasing the crystallization stress between the substrate and the semiconductor layer. A prepared substrate is located inside a reaction chamber(S1). The substrate has the lattice constant which is similar to the nitride semiconductor layer formed on the substrate. The InGaN buffer layer is formed on the substrate(S2). An u-GaN(undoped-GaN) layer is formed on the InGaN buffer layer(S3). An n-type semiconductor layer, an active layer, and a p-type semiconductor layer are formed on the u-GaN layer(S4). Light emitting cells are formed by patterning the p-type semiconductor layer, the active layer, and the n-type semiconductor layer(S5). A part of n-type semiconductor layer is exposed by patterning the p-type semiconductor layer and the active layer of the light emitting cells(S6). A p-type Ohmic metal layer and an n-type Ohmic metal layer are formed on the p-type semiconductor layer and the n-type semiconductor layer(S7). A p-type pad and an n-type pad are formed on the light emitting cell(S9).

Description

LIGHT EMITTING DEVICE OF A NITRIDE COMPOUND SEMICONDUCTOR AND THE FABRICATION METHOD THEREOF

The present invention relates to a nitride semiconductor light emitting device and a method of manufacturing the same, and more particularly, to implement a buffer layer interposed between a substrate and a semiconductor layer as an InGaN buffer layer having an IN content of 5 atomic% or less in a light emitting device driven using an AC power source. The present invention relates to a nitride semiconductor light emitting device for reducing the occurrence of cracks and the like caused by the difference in lattice constant and thermal expansion coefficient of a substrate and a semiconductor layer, and a method of manufacturing the same.

A light emitting diode is a photoelectric conversion semiconductor device having a structure in which an N-type semiconductor and a P-type semiconductor are bonded to each other and emit light by recombination of electrons and holes. Such light emitting diodes are widely used as display devices and backlights. In addition, the light emitting diode consumes less power and has a longer lifespan than existing light bulbs or fluorescent lamps, thereby replacing its incandescent lamps and fluorescent lamps, thereby expanding its use area for general lighting.

The light emitting diode is repeatedly turned on and off in accordance with the direction of the current under AC power. Therefore, when the light emitting diode is directly connected to an AC power source, the light emitting diode does not emit light continuously and is easily broken by reverse current.

In order to solve the problem of the light emitting diode, a light emitting diode that can be directly connected to a high voltage AC power source is disclosed in International Publication No. WO 2004/023568 (Al) "Light-Emitting Device Having Light-Emitting Components". EMITTING ELEMENTS, which was disclosed by SAKAI et. Al.

According to WO 2004/023568 (Al), the LEDs are two-dimensionally connected in series on an insulating substrate such as a sapphire substrate to form an LED array. These two LED arrays are connected in anti-parallel on the sapphire substrate. As a result, a single chip light emitting device that can be driven by an AC power supply is provided.

In general, nitrides of Group III elements, such as gallium nitride (GaN) and aluminum nitride (AlN), have excellent thermal stability and have a direct transition energy band structure. As a lot of attention. In particular, blue and green light emitting devices using gallium nitride (GaN) have been used in various applications such as large-scale color flat panel display devices, traffic lights, indoor lighting, high density light sources, high resolution output systems, and optical communications.

The nitride semiconductor layer of the group III element is a metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) on a heterogeneous substrate such as sapphire or silicon carbide (SiC) having a hexagonal structure Grown through the process. However, when a nitride semiconductor layer of a group III element is formed on a dissimilar substrate, cracks or warpage occur in the semiconductor layer due to a difference in lattice constant and thermal expansion coefficient between the semiconductor layer and the substrate, and a potential (dislocation) is generated. Cracks, distortions and dislocations in the semiconductor layer deteriorate the characteristics of the light emitting device. Therefore, a buffer layer is generally used to relieve stress due to the lattice constant and thermal expansion coefficient difference between the substrate and the semiconductor layer.

According to the prior art, by forming a buffer layer between the semiconductor layer and the substrate, it is possible to reduce the occurrence of cracks due to the difference in lattice constant and thermal expansion coefficient between the substrate and the semiconductor layer.

However, the buffer layer grown at low temperature mainly grows perpendicularly to the substrate and thus has a columnar structure. On the other hand, the semiconductor layer is affected by the crystal structure, crystalline and column size distribution of the buffer layer located below. That is, crystal defects of the buffer layer are transferred to the semiconductor layer on the buffer layer. Therefore, crystal defects in accordance with the columnar structure of the buffer layer appear as crystal defects in the semiconductor layer.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the crystal defects of a semiconductor layer grown thereon when a buffer layer is created between a substrate and a semiconductor layer to fabricate a nitride semiconductor light emitting device driven using an AC power source. A nitride semiconductor light emitting device including a buffer layer and a method of manufacturing the same are provided.

In order to achieve these problems, according to one aspect of the present invention, in a nitride semiconductor light emitting device operated by an AC power source, one substrate, an InGaN buffer layer formed on the one substrate, and a first conductivity type semiconductor layer And a GaN-based semiconductor layer having an active layer and a second conductivity type semiconductor layer, and including a plurality of light emitting cells connected in series through a metal wire in a state of being electrically separated from the InGaN buffer layer, wherein the InGaN buffer layer The content is smaller than the In content of the active layer and provides a nitride semiconductor light emitting device, characterized in that greater than zero.

Preferably, the InGaN buffer layer has an In content of 2 to 3 atomic%.

Preferably, the InGaN buffer layer includes InGaN buffer layers formed in multiple layers on the substrate, wherein each layer of the InGaN buffer layers is characterized in that the content of In decreases as it approaches the first conductive semiconductor layer from the substrate. .

Preferably, the plurality of light emitting cells are arranged in two rows in parallel, and the first and second columns are arranged in opposite directions to each other.

Preferably, each of the light emitting cells includes a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer, and the light emitting cells are formed of the first conductivity type semiconductor layers and the second conductivity type of adjacent light emitting cells. The semiconductor layers are each electrically connected in series by metal wires.

According to another aspect of the present invention, there is provided a method of manufacturing a nitride semiconductor light emitting device operating by an alternating current power source, comprising: preparing a substrate, forming an InGaN buffer layer on the substrate, and forming a first conductivity type on the InGaN buffer layer. Forming a GaN-based semiconductor layer having a semiconductor layer, an active layer, and a second conductivity-type semiconductor layer; and forming a plurality of light emitting cells connected in series through a metal wire in a state in which the GaN-based semiconductor layer is electrically separated from each other. Including the step, wherein the In content of the InGaN buffer layer provides a method for manufacturing a nitride semiconductor light emitting device, characterized in that less than the In content of the active layer and greater than zero.

Preferably, the InGaN buffer layer has an In content of 2 to 3 atomic%.

Preferably, the forming of the InGaN buffer layer, InGaN buffer layer is formed in a multi-layer on the substrate, each layer of the InGaN buffer layer is reduced in the content of In closer to the first conductive semiconductor layer from the substrate Has characteristics.

According to an embodiment of the present invention, in the intervening buffer layer between the substrate and the semiconductor layer, the buffer layer is embodied as an InGaN buffer layer smaller than the In content of the active layer, for example, having an In content of greater than 0 and less than 5 atomic%. By reducing the interfacial gap and crystal stress between the semiconductor layer and the semiconductor layer, it is possible to effectively reduce the occurrence of cracks due to the difference in lattice constant and thermal expansion coefficient between the substrate and the semiconductor layer.

In addition, the semiconductor layer is influenced by the crystal structure, crystalline and column size distribution of the buffer layer disposed below. That is, crystal defects of the buffer layer are transferred to the semiconductor layer on the buffer layer. According to the exemplary embodiment of the present invention, as the crystal defects of the buffer layer are reduced, the crystal defects of the semiconductor layer are also reduced, thereby improving the light yield of the nitride light emitting device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention to those skilled in the art will fully convey.

Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, widths, lengths, thicknesses, and the like of components may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 is a cross-sectional view of a nitride semiconductor light emitting device according to an embodiment of the present invention.

Referring to FIG. 1, the light emitting device of the present invention includes a substrate 110, an InGaN buffer layer 120 formed on the substrate 110, a u-GaN layer 130 formed on the InGaN buffer layer 120, and u. A plurality of light emitting cells 100-1 to 100-n patterned on the GaN layer 130 and metal wirings for connecting the plurality of light emitting cells 100-1 to 100-n in series ( 180-1 to 180-n-1).

The substrate 110 may be a sapphire, spinel, Si substrate, SiC substrate, ZnO substrate, GaAs substrate, GaN substrate, or the like.

The InGaN buffer layer 120 is used to mitigate the lattice mismatch between the semiconductor layers to be formed thereon and the substrate 110. In addition, the light emitting cells should be electrically separated from each other.

In the present embodiment, the InGaN buffer layer 120 has an In content smaller than the In content of the active layer 150, for example, 5 atomic% or less, and optimally has an In content of 2 to 3 atomic%. .

Meanwhile, each of the plurality of light emitting cells 100-1 to 100-n includes a nitride semiconductor layer PN bonded.

In the present embodiment, each of the light emitting cells includes an N-type semiconductor layer 140, an active layer 150 formed in a predetermined region on the N-type semiconductor layer 140, and a P-type semiconductor formed on the active layer 150. Layer 160. At least a portion of an upper surface of the N-type semiconductor layer 140 is exposed. Ohmic metal layers 170 and 175 may be formed on the N-type semiconductor layer 140 and the P-type semiconductor layer 160. Also, on the N-type semiconductor layer 140 or the P-type semiconductor layer 160 1x 10 ¹⁹ ~ 1 x 10 ²² / cm ³ A high concentration N-type semiconductor tunneling layer or a semi-metal layer may be formed, and a transparent electrode layer (not shown) may be further formed thereon.

The N-type semiconductor layer 140 may be a GaN-based implanted N-type impurity, for example, an N-type Al _x In _y Ga _{1- xy} N (0 <x, y, x + y <1) film, but is not limited thereto. It may be formed of various semiconductor layers. In addition, the P-type semiconductor layer 160 may be a GaN-based, for example, P-type Al _x In _y Ga _1-xy N (0 <x, y, x + y <1) film into which P-type impurities are injected. It is not limited and may be formed of various semiconductor layers.

The N-type semiconductor layer 140 and the P-type semiconductor layer 160 may be an In _x Ga _{1- x} N (0 <x <1) film or an Al _x Ga _1-x N (0 <x <1) film. have.

The N-type semiconductor layer 140 may be formed by doping silicon (Si), and the P-type semiconductor layer 160 may be formed by doping zinc (Zn) or magnesium (Mg).

The active layer 150 is an area where electrons and holes are recombined, and includes InGaN. The content of In in the active layer 150 may be 10 to 20 atomic%. The emission wavelength emitted from the light emitting cell may be determined according to the type of material constituting the active layer 150. The active layer 150 may be a multilayer film in which a quantum well layer and a barrier layer are repeatedly formed. The barrier layer and the well layer may be binary to quaternary compound semiconductor layers represented by general formula Al _x In _y Ga _1-xy N (0 ≦ x, y, x + y <1).

The light emitting cells are connected in series through metal wires 180-1 to 180-n-1. In the present embodiment, the metal wires are connected in series with the number of light emitting cells 100-1 to 100-n that can be driven by an AC power supply. That is, the number of light emitting cells 100 to be connected in series is limited by an AC driving voltage / current applied to the light emitting device and a voltage required to drive a single light emitting cell. For example, under a 220V AC voltage, about 67 LEDs for driving 3.3V may be connected in series. In addition, at 110V AC voltage, approximately 34V driving light emitting cells may be connected in series.

As shown in FIG. 1, in a light emitting device in which n light emitting cells 100-1 to 100-n are connected in series, an N-type semiconductor layer 140 and a second of the first light emitting cell 100-1 are provided. The P-type semiconductor layer 160 of the light emitting cell 100-2 is connected through the first metal wiring 180-1, and the N-type semiconductor layer 140 and the third of the second light emitting cell 100-2 are connected. The P-type semiconductor layer (not shown) of the light emitting cell (not shown) is connected through the second metal wire 180-2. The n-type semiconductor layer 160 of the n-th light emitting cell (not shown) and the P-type semiconductor layer 160 of the n-th light emitting cell 100-n -1 are n-n metal wiring. Connected via (180-n-2), the N-type semiconductor layer 140 of the n-th light emitting cell 100-n-1 and the P-type semiconductor layer 160 of the n-th light emitting cell 100-n ) Is connected via the n-th metal wiring 180-n-1.

The series-connected light emitting cells constitute an LED array, as disclosed in WO 2004/023568 (Al). On the other hand, the light emitting device has two LED arrays connected in parallel to each other, can be used for illumination under AC power. A P-type pad for electrically connecting an AC power source to the P-type semiconductor layer 160 of the first light emitting cell 100-1 and the N-type semiconductor layer 140 of the n-th light emitting cell 100-n, respectively; An N-type pad (not shown) may be formed.

2 is a flowchart illustrating a method of forming a nitride semiconductor light emitting device according to an embodiment of the present invention, and FIGS. 3 to 7 illustrate a method of manufacturing a light emitting device according to an embodiment of the present invention. It is a section for.

2 and 3, the substrate 110 is prepared and placed in the reaction chamber (S1). The substrate 110 has a lattice constant similar to that of the nitride semiconductor layer to be formed thereon. The substrate 110 may be a sapphire, spinel, Si substrate, SiC substrate, ZnO substrate, GaAs substrate, GaN substrate, or the like.

An InGaN buffer layer 120 is formed on the substrate 110 (S2).

The InGaN buffer layer 120 may include metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE) or molecular beam growth (MBE), metal organic chemical vapor deposition It can be formed using a growth method (metalorganic chemical vapor phase epitaxy, MOCVPE) and the like. In this case, the InGaN buffer layer 120 has an In content of 5 atomic% or less, and optimally has an In content of 2 to 3 atomic%.

The InGaN buffer layer 120 may be grown using any of the above-described crystal growth methods at a pressure of about 10 torr to about 780 torr at 400 ° C to 500 ° C.

The source gas for forming the InGaN buffer layer 120 uses trimethyl indium (TMI, In (CH ₃ ) ₃ ), gallium, trimethylgallium (TMG) and / or triethyl galiun (TEG). Ammonia (NH ₃ ) is used as the reaction gas. These source gases and reactants are introduced into the reaction chamber, and an InGaN buffer layer 120 having an In content of 5 atomic% or less is formed at 400 to 500 ° C.

Thereafter, an u-GaN (undoped-GaN) layer 130 is formed on the InGaN buffer layer 120 having an In content of 5 atomic% or less (S3) (FIG. 4).

The u-GaN 130 is used to selectively form GaN-based semiconductor layers 140, 150, and 160 formed of GaN-based material thereon, and may be selectively adopted.

After the u-GaN layer 130 is formed, an N-type semiconductor layer 140, an active layer 150, and a P-type semiconductor layer 160 are formed on the u-GaN layer 130 (S4) (FIG. 5). . These semiconductor layers 140, 150, 160 may be formed continuously in the same process chamber. The N-type semiconductor layer 140, the active layer 150, and the P-type semiconductor layer 160 may be formed using a MOCVD, MBE, or HVPE method, and may be formed in multiple layers, respectively. 1 x 10 ¹⁹ to 1 x 10 ²² / cm ^{3 on the} N-type semiconductor layer 140 or the P-type semiconductor layer 160 A high concentration N-type semiconductor tunneling layer or a semimetal layer may be formed, and a transparent electrode layer (not shown) may be further formed thereon.

Referring to FIG. 6, the P-type semiconductor layer 160, the active layer 150, and the N-type semiconductor layer 140 are patterned to form separate light emitting cells 100-1 to 100-n (S5). . Each of these layers can be patterned using photo and etching techniques. For example, a photoresist pattern is formed on the P-type semiconductor layer 160, and the P-type semiconductor layer 160, the active layer 150, and the N-type semiconductor layer 140 are sequentially etched using the photoresist pattern as an etching mask. Accordingly, separated light emitting cells are formed.

In this case, the InGaN buffer layer 120 and the u-GaN 130 may be etched to expose a part of the substrate 110.

Referring to FIG. 7, a portion of the upper surface of the N-type semiconductor layer 140 is exposed by patterning the P-type semiconductor layer 160 and the active layer 150 of the separated light emitting cells 100-1 to 100-n. (S6). The patterning process may be performed using a photo and etching process. That is, a photoresist pattern is formed on the substrate 110 having the separated light emitting cells 100-1 to 100-n, and the photoresist pattern is used as an etching mask to form the P-type semiconductor layer 160 and the active layer 150. Etch a part of). As a result, the N-type semiconductor layer 140 is exposed to a portion where the P-type semiconductor layer and the active layer are etched.

The etching process may be performed by a wet or dry etching process. The dry etching process may be a dry etching process using plasma.

The P-type ohmic metal layer 170 and the N-type ohmic metal layer 175 are formed on the P-type semiconductor layer 160 and the N-type semiconductor layer 140, respectively (S7).

The ohmic metal layers 170 and 175 may be formed using a metal deposition process after opening a region where the ohmic metal layers 170 and 175 are to be formed using a photoresist pattern (not shown). The P-type ohmic metal layer 170 and the N-type ohmic metal layer 175 may be formed by the same process, or may be formed by separate processes. The ohmic metal layers 170 and 175 may be formed of at least one material layer of Pb, Sn, Au, Ge, Cu, Bi, Cd, Zn, Ag, Ni, and Ti.

 Thereafter, the N-type ohmic metal layers 175 and the P-type ohmic metal layers 170 of the adjacent light emitting cells are connected to the metal wires 180-1 to 180-n-1 (S8). The metal wires may be formed through an air bridge process or a step-cover process. This completes the light emitting element of FIG.

 The air bridge process is disclosed in International Publication No. WO 2004/023568 (Al), which is briefly described. First, a first photoresist pattern having an opening exposing the ohmic metal layers 170 and 175 is formed on a substrate on which the light emitting cells and the ohmic metal layers 170 and 175 are formed. Thereafter, the metal material layer is thinly formed by using an electron beam evaporation technique. The metal material layer is formed on the entire surface of the opening and the first photoresist pattern. Subsequently, a second photoresist pattern is formed to expose regions between adjacent light emitting cells to be connected and the metal material layer of the openings. Thereafter, gold and the like are formed using a plating technique, and then the first and second photoresist patterns are removed with a solution such as solvent. As a result, only wirings connecting adjacent light emitting cells remain, and all other metal material layers and photoresist patterns are removed.

 Meanwhile, the step cover process includes forming an insulating layer on a substrate having light emitting cells and an ohmic metal layer. The insulating layer is patterned using photolithography and etching techniques to form openings that expose the ohmic metal layers 170 and 175 on the P-type semiconductor layer and the N-type semiconductor layer. Subsequently, an electron beam deposition technique or the like is used to form a metal layer filling the opening and covering the insulating layer. Thereafter, the metal layer is patterned using photolithography and etching techniques to form interconnects that connect adjacent light emitting cells. Such a step cover process is possible in various modifications. Using the step cover process, the wiring is supported by the insulating layer, thereby increasing the reliability of the wiring.

Meanwhile, P-type pads and N-type pads are formed in the light emitting cells 100-1 and 100-n positioned at both ends to connect to the AC power source (S9).

In the drawings, the light emitting cells are shown arranged in a row, but for convenience of description, the light emitting cells may have various shapes on a plane, as shown in International Publication No. WO 2004/023568 (Al). Can be arranged as.

Each of the light emitting cells 100-1 to 100-n may be arranged in various forms. In this embodiment, the light emitting cells 100-1 to 100-n are arranged in two rows in the light emitting diode package 100, and the first and second columns have polarities. They may be arranged in opposite directions to each other. Therefore, when the AC power is applied, the light emitting cells perform light emitting operations in the positive voltage section because current flows in the first column, and in the negative voltage section, light emitting cells perform light emitting operation in the second column. As a result, the first column and the second column alternately perform the light emission operation.

8 is a graph showing crystallinity of a semiconductor layer formed according to an embodiment of the present invention and a semiconductor layer formed according to a comparative example. In the graph, one embodiment of the present invention uses an InGaN buffer layer having an In content of 5 atomic% or less, and a comparative example uses an AlN buffer layer.

In order to show the crystallinity improvement of the semiconductor layer according to an embodiment of the present invention, a semiconductor layer formed using an InGaN buffer layer having an In content of 5 atomic% or less according to one embodiment of the present invention, and an AlN buffer layer according to a comparative example The degree of crystal distortion was measured for the semiconductor layer formed by using X-ray.

Referring to FIG. 8, the FWHM-Full Width Half Maximum, which is a measure of crystallinity, is displayed on the Y axis in order to compare the crystallinity of semiconductor layers according to an embodiment of the present invention and a comparative example. The full width at half maximum indicates crystallinity, and the smaller the value is, the smaller the defects are and the better the crystallinity is. In the graph, 002 and 201 indicate crystal directions. The X axis represents the content of In.

As described through the graph, the semiconductor layer formed using the InGaN buffer layer having an In content of 5 atomic% or less according to an embodiment of the present invention can be confirmed that the crystallinity is improved compared to the AlN buffer layer according to the comparative example. The crystallinity is determined by the number of defects, which in turn affects the luminous intensity. The smaller the half width, the smaller the number of defects, which means that the luminous intensity can be improved.

The present invention has been described with reference to preferred embodiments. However, those skilled in the art will understand that many other embodiments other than those specifically described also fall within the spirit and scope of the invention.

For example, in an embodiment of the present invention, the InGaN buffer layer having an In content of 5 atomic% or less formed on a substrate has been described as a single layer, but may be implemented as a plurality of layers. In addition, the plurality of layers may reduce the In content as the substrate approaches the semiconductor layer.

1 is a cross-sectional view of a nitride semiconductor light emitting device according to an embodiment of the present invention.

2 is a process flowchart illustrating a method of manufacturing a nitride semiconductor light emitting device according to an embodiment of the present invention.

3 to 7 are cross-sectional views illustrating a method of manufacturing a nitride semiconductor light emitting device according to an embodiment of the present invention.

8 is a graph showing crystallinity of a semiconductor layer formed according to an embodiment of the present invention and a semiconductor layer formed according to a comparative example.

<Description of the symbols for the main parts of the drawings>

100-1-100-n: light emitting cell 110: substrate

120: InGaN buffer layer 130: u-GaN layer

130-1: N-type semiconductor layer 130-2, 130-N: P-type semiconductor layer

140: N-type semiconductor layer 150: active layer

160: P-type semiconductor layer 170, 175: ohmic metal layer

180-1-180-n-1: Metal Wiring

Claims (8)

In a nitride semiconductor light emitting device operating by an AC power source, With one substrate, An InGaN buffer layer formed on the one substrate, Comprising a GaN-based semiconductor layer having a first conductivity type semiconductor layer, an active layer containing InGaN, a second conductivity type semiconductor layer, a plurality of light emission in series through a metal wiring in a state formed electrically separated from the InGaN buffer layer Include cells, The In content of the InGaN buffer layer is a nitride semiconductor light emitting device, characterized in that less than the In content of the active layer and greater than zero. The nitride semiconductor light emitting device of claim 1, wherein the InGaN buffer layer has an In content of 2 to 3 atomic%. The method according to claim 1, The InGaN buffer layer, InGaN buffer layers formed in multiple layers on the substrate, Each layer of the InGaN buffer layer is characterized in that the content of In decreases toward the first conductive semiconductor layer from the substrate. The method according to claim 1, The plurality of light emitting cells are arranged in parallel in two columns, The nitride semiconductor light emitting device of which the first and second columns are arranged in opposite directions to each other. The method according to claim 1, Each of the light emitting cells includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The light emitting cells are nitride semiconductor light emitting devices of which the first conductive semiconductor layers and the second conductive semiconductor layers of adjacent light emitting cells are electrically connected in series by metal wires, respectively. In the manufacturing method of the nitride semiconductor light emitting element operated by the AC power source, Preparing a substrate; Forming an InGaN buffer layer on the substrate; Forming a GaN-based semiconductor layer having a first conductivity type semiconductor layer, an active layer containing InGaN, and a second conductivity type semiconductor layer on the InGaN buffer layer; Patterning the GaN-based semiconductor layer to form a plurality of light emitting cells connected in series through a metal wire in an electrically separated state; The In content of the InGaN buffer layer is a nitride semiconductor light emitting device manufacturing method, characterized in that less than the In content of the active layer and greater than zero. The method of claim 6, wherein the InGaN buffer layer has an In content of 2 to 3 atomic%. The method according to claim 6, Forming the InGaN buffer layer, To form a multi-layer InGaN buffer layer on the substrate, And each layer of the InGaN buffer layer is characterized in that the content of In decreases as it approaches the first conductive semiconductor layer from the substrate.

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